1 /* 2 * Copyright (C) 2013 Huawei Ltd. 3 * Author: Jiang Liu <liuj97@gmail.com> 4 * 5 * Copyright (C) 2014 Zi Shen Lim <zlim.lnx@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASM_INSN_H 20 #define __ASM_INSN_H 21 #include <linux/types.h> 22 23 /* A64 instructions are always 32 bits. */ 24 #define AARCH64_INSN_SIZE 4 25 26 #ifndef __ASSEMBLY__ 27 /* 28 * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a 29 * Section C3.1 "A64 instruction index by encoding": 30 * AArch64 main encoding table 31 * Bit position 32 * 28 27 26 25 Encoding Group 33 * 0 0 - - Unallocated 34 * 1 0 0 - Data processing, immediate 35 * 1 0 1 - Branch, exception generation and system instructions 36 * - 1 - 0 Loads and stores 37 * - 1 0 1 Data processing - register 38 * 0 1 1 1 Data processing - SIMD and floating point 39 * 1 1 1 1 Data processing - SIMD and floating point 40 * "-" means "don't care" 41 */ 42 enum aarch64_insn_encoding_class { 43 AARCH64_INSN_CLS_UNKNOWN, /* UNALLOCATED */ 44 AARCH64_INSN_CLS_DP_IMM, /* Data processing - immediate */ 45 AARCH64_INSN_CLS_DP_REG, /* Data processing - register */ 46 AARCH64_INSN_CLS_DP_FPSIMD, /* Data processing - SIMD and FP */ 47 AARCH64_INSN_CLS_LDST, /* Loads and stores */ 48 AARCH64_INSN_CLS_BR_SYS, /* Branch, exception generation and 49 * system instructions */ 50 }; 51 52 enum aarch64_insn_hint_op { 53 AARCH64_INSN_HINT_NOP = 0x0 << 5, 54 AARCH64_INSN_HINT_YIELD = 0x1 << 5, 55 AARCH64_INSN_HINT_WFE = 0x2 << 5, 56 AARCH64_INSN_HINT_WFI = 0x3 << 5, 57 AARCH64_INSN_HINT_SEV = 0x4 << 5, 58 AARCH64_INSN_HINT_SEVL = 0x5 << 5, 59 }; 60 61 enum aarch64_insn_imm_type { 62 AARCH64_INSN_IMM_ADR, 63 AARCH64_INSN_IMM_26, 64 AARCH64_INSN_IMM_19, 65 AARCH64_INSN_IMM_16, 66 AARCH64_INSN_IMM_14, 67 AARCH64_INSN_IMM_12, 68 AARCH64_INSN_IMM_9, 69 AARCH64_INSN_IMM_MAX 70 }; 71 72 enum aarch64_insn_register_type { 73 AARCH64_INSN_REGTYPE_RT, 74 AARCH64_INSN_REGTYPE_RN, 75 AARCH64_INSN_REGTYPE_RM, 76 }; 77 78 enum aarch64_insn_register { 79 AARCH64_INSN_REG_0 = 0, 80 AARCH64_INSN_REG_1 = 1, 81 AARCH64_INSN_REG_2 = 2, 82 AARCH64_INSN_REG_3 = 3, 83 AARCH64_INSN_REG_4 = 4, 84 AARCH64_INSN_REG_5 = 5, 85 AARCH64_INSN_REG_6 = 6, 86 AARCH64_INSN_REG_7 = 7, 87 AARCH64_INSN_REG_8 = 8, 88 AARCH64_INSN_REG_9 = 9, 89 AARCH64_INSN_REG_10 = 10, 90 AARCH64_INSN_REG_11 = 11, 91 AARCH64_INSN_REG_12 = 12, 92 AARCH64_INSN_REG_13 = 13, 93 AARCH64_INSN_REG_14 = 14, 94 AARCH64_INSN_REG_15 = 15, 95 AARCH64_INSN_REG_16 = 16, 96 AARCH64_INSN_REG_17 = 17, 97 AARCH64_INSN_REG_18 = 18, 98 AARCH64_INSN_REG_19 = 19, 99 AARCH64_INSN_REG_20 = 20, 100 AARCH64_INSN_REG_21 = 21, 101 AARCH64_INSN_REG_22 = 22, 102 AARCH64_INSN_REG_23 = 23, 103 AARCH64_INSN_REG_24 = 24, 104 AARCH64_INSN_REG_25 = 25, 105 AARCH64_INSN_REG_26 = 26, 106 AARCH64_INSN_REG_27 = 27, 107 AARCH64_INSN_REG_28 = 28, 108 AARCH64_INSN_REG_29 = 29, 109 AARCH64_INSN_REG_FP = 29, /* Frame pointer */ 110 AARCH64_INSN_REG_30 = 30, 111 AARCH64_INSN_REG_LR = 30, /* Link register */ 112 AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */ 113 AARCH64_INSN_REG_SP = 31 /* Stack pointer: as load/store base reg */ 114 }; 115 116 enum aarch64_insn_variant { 117 AARCH64_INSN_VARIANT_32BIT, 118 AARCH64_INSN_VARIANT_64BIT 119 }; 120 121 enum aarch64_insn_condition { 122 AARCH64_INSN_COND_EQ = 0x0, /* == */ 123 AARCH64_INSN_COND_NE = 0x1, /* != */ 124 AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */ 125 AARCH64_INSN_COND_CC = 0x3, /* unsigned < */ 126 AARCH64_INSN_COND_MI = 0x4, /* < 0 */ 127 AARCH64_INSN_COND_PL = 0x5, /* >= 0 */ 128 AARCH64_INSN_COND_VS = 0x6, /* overflow */ 129 AARCH64_INSN_COND_VC = 0x7, /* no overflow */ 130 AARCH64_INSN_COND_HI = 0x8, /* unsigned > */ 131 AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */ 132 AARCH64_INSN_COND_GE = 0xa, /* signed >= */ 133 AARCH64_INSN_COND_LT = 0xb, /* signed < */ 134 AARCH64_INSN_COND_GT = 0xc, /* signed > */ 135 AARCH64_INSN_COND_LE = 0xd, /* signed <= */ 136 AARCH64_INSN_COND_AL = 0xe, /* always */ 137 }; 138 139 enum aarch64_insn_branch_type { 140 AARCH64_INSN_BRANCH_NOLINK, 141 AARCH64_INSN_BRANCH_LINK, 142 AARCH64_INSN_BRANCH_RETURN, 143 AARCH64_INSN_BRANCH_COMP_ZERO, 144 AARCH64_INSN_BRANCH_COMP_NONZERO, 145 }; 146 147 enum aarch64_insn_size_type { 148 AARCH64_INSN_SIZE_8, 149 AARCH64_INSN_SIZE_16, 150 AARCH64_INSN_SIZE_32, 151 AARCH64_INSN_SIZE_64, 152 }; 153 154 enum aarch64_insn_ldst_type { 155 AARCH64_INSN_LDST_LOAD_REG_OFFSET, 156 AARCH64_INSN_LDST_STORE_REG_OFFSET, 157 }; 158 159 #define __AARCH64_INSN_FUNCS(abbr, mask, val) \ 160 static __always_inline bool aarch64_insn_is_##abbr(u32 code) \ 161 { return (code & (mask)) == (val); } \ 162 static __always_inline u32 aarch64_insn_get_##abbr##_value(void) \ 163 { return (val); } 164 165 __AARCH64_INSN_FUNCS(str_reg, 0x3FE0EC00, 0x38206800) 166 __AARCH64_INSN_FUNCS(ldr_reg, 0x3FE0EC00, 0x38606800) 167 __AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) 168 __AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) 169 __AARCH64_INSN_FUNCS(cbz, 0xFE000000, 0x34000000) 170 __AARCH64_INSN_FUNCS(cbnz, 0xFE000000, 0x35000000) 171 __AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000) 172 __AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001) 173 __AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) 174 __AARCH64_INSN_FUNCS(smc, 0xFFE0001F, 0xD4000003) 175 __AARCH64_INSN_FUNCS(brk, 0xFFE0001F, 0xD4200000) 176 __AARCH64_INSN_FUNCS(hint, 0xFFFFF01F, 0xD503201F) 177 __AARCH64_INSN_FUNCS(br, 0xFFFFFC1F, 0xD61F0000) 178 __AARCH64_INSN_FUNCS(blr, 0xFFFFFC1F, 0xD63F0000) 179 __AARCH64_INSN_FUNCS(ret, 0xFFFFFC1F, 0xD65F0000) 180 181 #undef __AARCH64_INSN_FUNCS 182 183 bool aarch64_insn_is_nop(u32 insn); 184 185 int aarch64_insn_read(void *addr, u32 *insnp); 186 int aarch64_insn_write(void *addr, u32 insn); 187 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn); 188 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type, 189 u32 insn, u64 imm); 190 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr, 191 enum aarch64_insn_branch_type type); 192 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr, 193 enum aarch64_insn_register reg, 194 enum aarch64_insn_variant variant, 195 enum aarch64_insn_branch_type type); 196 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr, 197 enum aarch64_insn_condition cond); 198 u32 aarch64_insn_gen_hint(enum aarch64_insn_hint_op op); 199 u32 aarch64_insn_gen_nop(void); 200 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg, 201 enum aarch64_insn_branch_type type); 202 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg, 203 enum aarch64_insn_register base, 204 enum aarch64_insn_register offset, 205 enum aarch64_insn_size_type size, 206 enum aarch64_insn_ldst_type type); 207 208 bool aarch64_insn_hotpatch_safe(u32 old_insn, u32 new_insn); 209 210 int aarch64_insn_patch_text_nosync(void *addr, u32 insn); 211 int aarch64_insn_patch_text_sync(void *addrs[], u32 insns[], int cnt); 212 int aarch64_insn_patch_text(void *addrs[], u32 insns[], int cnt); 213 #endif /* __ASSEMBLY__ */ 214 215 #endif /* __ASM_INSN_H */ 216