1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2012 ARM Ltd.
4  */
5 #ifndef __ASM_HW_BREAKPOINT_H
6 #define __ASM_HW_BREAKPOINT_H
7 
8 #include <asm/cputype.h>
9 #include <asm/cpufeature.h>
10 #include <asm/sysreg.h>
11 #include <asm/virt.h>
12 
13 #ifdef __KERNEL__
14 
15 struct arch_hw_breakpoint_ctrl {
16 	u32 __reserved	: 19,
17 	len		: 8,
18 	type		: 2,
19 	privilege	: 2,
20 	enabled		: 1;
21 };
22 
23 struct arch_hw_breakpoint {
24 	u64 address;
25 	u64 trigger;
26 	struct arch_hw_breakpoint_ctrl ctrl;
27 };
28 
29 /* Privilege Levels */
30 #define AARCH64_BREAKPOINT_EL1	1
31 #define AARCH64_BREAKPOINT_EL0	2
32 
33 #define DBG_HMC_HYP		(1 << 13)
34 
35 static inline u32 encode_ctrl_reg(struct arch_hw_breakpoint_ctrl ctrl)
36 {
37 	u32 val = (ctrl.len << 5) | (ctrl.type << 3) | (ctrl.privilege << 1) |
38 		ctrl.enabled;
39 
40 	if (is_kernel_in_hyp_mode() && ctrl.privilege == AARCH64_BREAKPOINT_EL1)
41 		val |= DBG_HMC_HYP;
42 
43 	return val;
44 }
45 
46 static inline void decode_ctrl_reg(u32 reg,
47 				   struct arch_hw_breakpoint_ctrl *ctrl)
48 {
49 	ctrl->enabled	= reg & 0x1;
50 	reg >>= 1;
51 	ctrl->privilege	= reg & 0x3;
52 	reg >>= 2;
53 	ctrl->type	= reg & 0x3;
54 	reg >>= 2;
55 	ctrl->len	= reg & 0xff;
56 }
57 
58 /* Breakpoint */
59 #define ARM_BREAKPOINT_EXECUTE	0
60 
61 /* Watchpoints */
62 #define ARM_BREAKPOINT_LOAD	1
63 #define ARM_BREAKPOINT_STORE	2
64 #define AARCH64_ESR_ACCESS_MASK	(1 << 6)
65 
66 /* Lengths */
67 #define ARM_BREAKPOINT_LEN_1	0x1
68 #define ARM_BREAKPOINT_LEN_2	0x3
69 #define ARM_BREAKPOINT_LEN_3	0x7
70 #define ARM_BREAKPOINT_LEN_4	0xf
71 #define ARM_BREAKPOINT_LEN_5	0x1f
72 #define ARM_BREAKPOINT_LEN_6	0x3f
73 #define ARM_BREAKPOINT_LEN_7	0x7f
74 #define ARM_BREAKPOINT_LEN_8	0xff
75 
76 /* Kernel stepping */
77 #define ARM_KERNEL_STEP_NONE	0
78 #define ARM_KERNEL_STEP_ACTIVE	1
79 #define ARM_KERNEL_STEP_SUSPEND	2
80 
81 /*
82  * Limits.
83  * Changing these will require modifications to the register accessors.
84  */
85 #define ARM_MAX_BRP		16
86 #define ARM_MAX_WRP		16
87 
88 /* Virtual debug register bases. */
89 #define AARCH64_DBG_REG_BVR	0
90 #define AARCH64_DBG_REG_BCR	(AARCH64_DBG_REG_BVR + ARM_MAX_BRP)
91 #define AARCH64_DBG_REG_WVR	(AARCH64_DBG_REG_BCR + ARM_MAX_BRP)
92 #define AARCH64_DBG_REG_WCR	(AARCH64_DBG_REG_WVR + ARM_MAX_WRP)
93 
94 /* Debug register names. */
95 #define AARCH64_DBG_REG_NAME_BVR	bvr
96 #define AARCH64_DBG_REG_NAME_BCR	bcr
97 #define AARCH64_DBG_REG_NAME_WVR	wvr
98 #define AARCH64_DBG_REG_NAME_WCR	wcr
99 
100 /* Accessor macros for the debug registers. */
101 #define AARCH64_DBG_READ(N, REG, VAL) do {\
102 	VAL = read_sysreg(dbg##REG##N##_el1);\
103 } while (0)
104 
105 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\
106 	write_sysreg(VAL, dbg##REG##N##_el1);\
107 } while (0)
108 
109 struct task_struct;
110 struct notifier_block;
111 struct perf_event_attr;
112 struct perf_event;
113 struct pmu;
114 
115 extern int arch_bp_generic_fields(struct arch_hw_breakpoint_ctrl ctrl,
116 				  int *gen_len, int *gen_type, int *offset);
117 extern int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw);
118 extern int hw_breakpoint_arch_parse(struct perf_event *bp,
119 				    const struct perf_event_attr *attr,
120 				    struct arch_hw_breakpoint *hw);
121 extern int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
122 					   unsigned long val, void *data);
123 
124 extern int arch_install_hw_breakpoint(struct perf_event *bp);
125 extern void arch_uninstall_hw_breakpoint(struct perf_event *bp);
126 extern void hw_breakpoint_pmu_read(struct perf_event *bp);
127 extern int hw_breakpoint_slots(int type);
128 
129 #ifdef CONFIG_HAVE_HW_BREAKPOINT
130 extern void hw_breakpoint_thread_switch(struct task_struct *next);
131 extern void ptrace_hw_copy_thread(struct task_struct *task);
132 #else
133 static inline void hw_breakpoint_thread_switch(struct task_struct *next)
134 {
135 }
136 static inline void ptrace_hw_copy_thread(struct task_struct *task)
137 {
138 }
139 #endif
140 
141 /* Determine number of BRP registers available. */
142 static inline int get_num_brps(void)
143 {
144 	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
145 	return 1 +
146 		cpuid_feature_extract_unsigned_field(dfr0,
147 						ID_AA64DFR0_BRPS_SHIFT);
148 }
149 
150 /* Determine number of WRP registers available. */
151 static inline int get_num_wrps(void)
152 {
153 	u64 dfr0 = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
154 	return 1 +
155 		cpuid_feature_extract_unsigned_field(dfr0,
156 						ID_AA64DFR0_WRPS_SHIFT);
157 }
158 
159 #endif	/* __KERNEL__ */
160 #endif	/* __ASM_BREAKPOINT_H */
161