1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 ARM Ltd. 4 */ 5 #ifndef __ASM_FP_H 6 #define __ASM_FP_H 7 8 #include <asm/errno.h> 9 #include <asm/ptrace.h> 10 #include <asm/processor.h> 11 #include <asm/sigcontext.h> 12 #include <asm/sysreg.h> 13 14 #ifndef __ASSEMBLY__ 15 16 #include <linux/bitmap.h> 17 #include <linux/build_bug.h> 18 #include <linux/bug.h> 19 #include <linux/cache.h> 20 #include <linux/init.h> 21 #include <linux/stddef.h> 22 #include <linux/types.h> 23 24 #ifdef CONFIG_COMPAT 25 /* Masks for extracting the FPSR and FPCR from the FPSCR */ 26 #define VFP_FPSCR_STAT_MASK 0xf800009f 27 #define VFP_FPSCR_CTRL_MASK 0x07f79f00 28 /* 29 * The VFP state has 32x64-bit registers and a single 32-bit 30 * control/status register. 31 */ 32 #define VFP_STATE_SIZE ((32 * 8) + 4) 33 #endif 34 35 struct task_struct; 36 37 extern void fpsimd_save_state(struct user_fpsimd_state *state); 38 extern void fpsimd_load_state(struct user_fpsimd_state *state); 39 40 extern void fpsimd_thread_switch(struct task_struct *next); 41 extern void fpsimd_flush_thread(void); 42 43 extern void fpsimd_signal_preserve_current_state(void); 44 extern void fpsimd_preserve_current_state(void); 45 extern void fpsimd_restore_current_state(void); 46 extern void fpsimd_update_current_state(struct user_fpsimd_state const *state); 47 48 extern void fpsimd_bind_state_to_cpu(struct user_fpsimd_state *state, 49 void *sve_state, unsigned int sve_vl); 50 51 extern void fpsimd_flush_task_state(struct task_struct *target); 52 extern void fpsimd_save_and_flush_cpu_state(void); 53 54 /* Maximum VL that SVE/SME VL-agnostic software can transparently support */ 55 #define VL_ARCH_MAX 0x100 56 57 /* Offset of FFR in the SVE register dump */ 58 static inline size_t sve_ffr_offset(int vl) 59 { 60 return SVE_SIG_FFR_OFFSET(sve_vq_from_vl(vl)) - SVE_SIG_REGS_OFFSET; 61 } 62 63 static inline void *sve_pffr(struct thread_struct *thread) 64 { 65 return (char *)thread->sve_state + sve_ffr_offset(thread_get_sve_vl(thread)); 66 } 67 68 extern void sve_save_state(void *state, u32 *pfpsr, int save_ffr); 69 extern void sve_load_state(void const *state, u32 const *pfpsr, 70 int restore_ffr); 71 extern void sve_flush_live(bool flush_ffr, unsigned long vq_minus_1); 72 extern unsigned int sve_get_vl(void); 73 extern void sve_set_vq(unsigned long vq_minus_1); 74 75 struct arm64_cpu_capabilities; 76 extern void sve_kernel_enable(const struct arm64_cpu_capabilities *__unused); 77 78 extern u64 read_zcr_features(void); 79 80 /* 81 * Helpers to translate bit indices in sve_vq_map to VQ values (and 82 * vice versa). This allows find_next_bit() to be used to find the 83 * _maximum_ VQ not exceeding a certain value. 84 */ 85 static inline unsigned int __vq_to_bit(unsigned int vq) 86 { 87 return SVE_VQ_MAX - vq; 88 } 89 90 static inline unsigned int __bit_to_vq(unsigned int bit) 91 { 92 return SVE_VQ_MAX - bit; 93 } 94 95 96 struct vl_info { 97 enum vec_type type; 98 const char *name; /* For display purposes */ 99 100 /* Minimum supported vector length across all CPUs */ 101 int min_vl; 102 103 /* Maximum supported vector length across all CPUs */ 104 int max_vl; 105 int max_virtualisable_vl; 106 107 /* 108 * Set of available vector lengths, 109 * where length vq encoded as bit __vq_to_bit(vq): 110 */ 111 DECLARE_BITMAP(vq_map, SVE_VQ_MAX); 112 113 /* Set of vector lengths present on at least one cpu: */ 114 DECLARE_BITMAP(vq_partial_map, SVE_VQ_MAX); 115 }; 116 117 #ifdef CONFIG_ARM64_SVE 118 119 extern void sve_alloc(struct task_struct *task); 120 extern void fpsimd_release_task(struct task_struct *task); 121 extern void fpsimd_sync_to_sve(struct task_struct *task); 122 extern void sve_sync_to_fpsimd(struct task_struct *task); 123 extern void sve_sync_from_fpsimd_zeropad(struct task_struct *task); 124 125 extern int vec_set_vector_length(struct task_struct *task, enum vec_type type, 126 unsigned long vl, unsigned long flags); 127 128 extern int sve_set_current_vl(unsigned long arg); 129 extern int sve_get_current_vl(void); 130 131 static inline void sve_user_disable(void) 132 { 133 sysreg_clear_set(cpacr_el1, CPACR_EL1_ZEN_EL0EN, 0); 134 } 135 136 static inline void sve_user_enable(void) 137 { 138 sysreg_clear_set(cpacr_el1, 0, CPACR_EL1_ZEN_EL0EN); 139 } 140 141 #define sve_cond_update_zcr_vq(val, reg) \ 142 do { \ 143 u64 __zcr = read_sysreg_s((reg)); \ 144 u64 __new = __zcr & ~ZCR_ELx_LEN_MASK; \ 145 __new |= (val) & ZCR_ELx_LEN_MASK; \ 146 if (__zcr != __new) \ 147 write_sysreg_s(__new, (reg)); \ 148 } while (0) 149 150 /* 151 * Probing and setup functions. 152 * Calls to these functions must be serialised with one another. 153 */ 154 enum vec_type; 155 156 extern void __init vec_init_vq_map(enum vec_type type); 157 extern void vec_update_vq_map(enum vec_type type); 158 extern int vec_verify_vq_map(enum vec_type type); 159 extern void __init sve_setup(void); 160 161 extern __ro_after_init struct vl_info vl_info[ARM64_VEC_MAX]; 162 163 static inline void write_vl(enum vec_type type, u64 val) 164 { 165 u64 tmp; 166 167 switch (type) { 168 #ifdef CONFIG_ARM64_SVE 169 case ARM64_VEC_SVE: 170 tmp = read_sysreg_s(SYS_ZCR_EL1) & ~ZCR_ELx_LEN_MASK; 171 write_sysreg_s(tmp | val, SYS_ZCR_EL1); 172 break; 173 #endif 174 default: 175 WARN_ON_ONCE(1); 176 break; 177 } 178 } 179 180 static inline int vec_max_vl(enum vec_type type) 181 { 182 return vl_info[type].max_vl; 183 } 184 185 static inline int vec_max_virtualisable_vl(enum vec_type type) 186 { 187 return vl_info[type].max_virtualisable_vl; 188 } 189 190 static inline int sve_max_vl(void) 191 { 192 return vec_max_vl(ARM64_VEC_SVE); 193 } 194 195 static inline int sve_max_virtualisable_vl(void) 196 { 197 return vec_max_virtualisable_vl(ARM64_VEC_SVE); 198 } 199 200 /* Ensure vq >= SVE_VQ_MIN && vq <= SVE_VQ_MAX before calling this function */ 201 static inline bool vq_available(enum vec_type type, unsigned int vq) 202 { 203 return test_bit(__vq_to_bit(vq), vl_info[type].vq_map); 204 } 205 206 static inline bool sve_vq_available(unsigned int vq) 207 { 208 return vq_available(ARM64_VEC_SVE, vq); 209 } 210 211 #else /* ! CONFIG_ARM64_SVE */ 212 213 static inline void sve_alloc(struct task_struct *task) { } 214 static inline void fpsimd_release_task(struct task_struct *task) { } 215 static inline void sve_sync_to_fpsimd(struct task_struct *task) { } 216 static inline void sve_sync_from_fpsimd_zeropad(struct task_struct *task) { } 217 218 static inline int sve_max_virtualisable_vl(void) 219 { 220 return 0; 221 } 222 223 static inline int sve_set_current_vl(unsigned long arg) 224 { 225 return -EINVAL; 226 } 227 228 static inline int sve_get_current_vl(void) 229 { 230 return -EINVAL; 231 } 232 233 static inline int sve_max_vl(void) 234 { 235 return -EINVAL; 236 } 237 238 static inline bool sve_vq_available(unsigned int vq) { return false; } 239 240 static inline void sve_user_disable(void) { BUILD_BUG(); } 241 static inline void sve_user_enable(void) { BUILD_BUG(); } 242 243 #define sve_cond_update_zcr_vq(val, reg) do { } while (0) 244 245 static inline void vec_init_vq_map(enum vec_type t) { } 246 static inline void vec_update_vq_map(enum vec_type t) { } 247 static inline int vec_verify_vq_map(enum vec_type t) { return 0; } 248 static inline void sve_setup(void) { } 249 250 #endif /* ! CONFIG_ARM64_SVE */ 251 252 #ifdef CONFIG_ARM64_SME 253 254 static inline void sme_smstart_sm(void) 255 { 256 asm volatile(__msr_s(SYS_SVCR_SMSTART_SM_EL0, "xzr")); 257 } 258 259 static inline void sme_smstop_sm(void) 260 { 261 asm volatile(__msr_s(SYS_SVCR_SMSTOP_SM_EL0, "xzr")); 262 } 263 264 static inline void sme_smstop(void) 265 { 266 asm volatile(__msr_s(SYS_SVCR_SMSTOP_SMZA_EL0, "xzr")); 267 } 268 269 #else 270 271 static inline void sme_smstart_sm(void) { } 272 static inline void sme_smstop_sm(void) { } 273 static inline void sme_smstop(void) { } 274 275 #endif /* ! CONFIG_ARM64_SME */ 276 277 /* For use by EFI runtime services calls only */ 278 extern void __efi_fpsimd_begin(void); 279 extern void __efi_fpsimd_end(void); 280 281 #endif 282 283 #endif 284