153631b54SCatalin Marinas /* 253631b54SCatalin Marinas * Copyright (C) 2012 ARM Ltd. 353631b54SCatalin Marinas * 453631b54SCatalin Marinas * This program is free software; you can redistribute it and/or modify 553631b54SCatalin Marinas * it under the terms of the GNU General Public License version 2 as 653631b54SCatalin Marinas * published by the Free Software Foundation. 753631b54SCatalin Marinas * 853631b54SCatalin Marinas * This program is distributed in the hope that it will be useful, 953631b54SCatalin Marinas * but WITHOUT ANY WARRANTY; without even the implied warranty of 1053631b54SCatalin Marinas * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1153631b54SCatalin Marinas * GNU General Public License for more details. 1253631b54SCatalin Marinas * 1353631b54SCatalin Marinas * You should have received a copy of the GNU General Public License 1453631b54SCatalin Marinas * along with this program. If not, see <http://www.gnu.org/licenses/>. 1553631b54SCatalin Marinas */ 1653631b54SCatalin Marinas #ifndef __ASM_FP_H 1753631b54SCatalin Marinas #define __ASM_FP_H 1853631b54SCatalin Marinas 1953631b54SCatalin Marinas #include <asm/ptrace.h> 2053631b54SCatalin Marinas 2153631b54SCatalin Marinas #ifndef __ASSEMBLY__ 2253631b54SCatalin Marinas 2353631b54SCatalin Marinas /* 2453631b54SCatalin Marinas * FP/SIMD storage area has: 2553631b54SCatalin Marinas * - FPSR and FPCR 2653631b54SCatalin Marinas * - 32 128-bit data registers 2753631b54SCatalin Marinas * 286ba1bc82SWill Deacon * Note that user_fpsimd forms a prefix of this structure, which is 296ba1bc82SWill Deacon * relied upon in the ptrace FP/SIMD accessors. 3053631b54SCatalin Marinas */ 3153631b54SCatalin Marinas struct fpsimd_state { 3253631b54SCatalin Marinas union { 3353631b54SCatalin Marinas struct user_fpsimd_state user_fpsimd; 3453631b54SCatalin Marinas struct { 3553631b54SCatalin Marinas __uint128_t vregs[32]; 3653631b54SCatalin Marinas u32 fpsr; 3753631b54SCatalin Marinas u32 fpcr; 3853631b54SCatalin Marinas }; 3953631b54SCatalin Marinas }; 4053631b54SCatalin Marinas }; 4153631b54SCatalin Marinas 4253631b54SCatalin Marinas #if defined(__KERNEL__) && defined(CONFIG_COMPAT) 4353631b54SCatalin Marinas /* Masks for extracting the FPSR and FPCR from the FPSCR */ 4453631b54SCatalin Marinas #define VFP_FPSCR_STAT_MASK 0xf800009f 4553631b54SCatalin Marinas #define VFP_FPSCR_CTRL_MASK 0x07f79f00 4653631b54SCatalin Marinas /* 4753631b54SCatalin Marinas * The VFP state has 32x64-bit registers and a single 32-bit 4853631b54SCatalin Marinas * control/status register. 4953631b54SCatalin Marinas */ 5053631b54SCatalin Marinas #define VFP_STATE_SIZE ((32 * 8) + 4) 5153631b54SCatalin Marinas #endif 5253631b54SCatalin Marinas 5353631b54SCatalin Marinas struct task_struct; 5453631b54SCatalin Marinas 5553631b54SCatalin Marinas extern void fpsimd_save_state(struct fpsimd_state *state); 5653631b54SCatalin Marinas extern void fpsimd_load_state(struct fpsimd_state *state); 5753631b54SCatalin Marinas 5853631b54SCatalin Marinas extern void fpsimd_thread_switch(struct task_struct *next); 5953631b54SCatalin Marinas extern void fpsimd_flush_thread(void); 6053631b54SCatalin Marinas 6153631b54SCatalin Marinas #endif 6253631b54SCatalin Marinas 6353631b54SCatalin Marinas #endif 64