1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ASM_ESR_H 8 #define __ASM_ESR_H 9 10 #include <asm/memory.h> 11 #include <asm/sysreg.h> 12 13 #define ESR_ELx_EC_UNKNOWN (0x00) 14 #define ESR_ELx_EC_WFx (0x01) 15 /* Unallocated EC: 0x02 */ 16 #define ESR_ELx_EC_CP15_32 (0x03) 17 #define ESR_ELx_EC_CP15_64 (0x04) 18 #define ESR_ELx_EC_CP14_MR (0x05) 19 #define ESR_ELx_EC_CP14_LS (0x06) 20 #define ESR_ELx_EC_FP_ASIMD (0x07) 21 #define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */ 22 #define ESR_ELx_EC_PAC (0x09) /* EL2 and above */ 23 /* Unallocated EC: 0x0A - 0x0B */ 24 #define ESR_ELx_EC_CP14_64 (0x0C) 25 /* Unallocated EC: 0x0d */ 26 #define ESR_ELx_EC_ILL (0x0E) 27 /* Unallocated EC: 0x0F - 0x10 */ 28 #define ESR_ELx_EC_SVC32 (0x11) 29 #define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */ 30 #define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */ 31 /* Unallocated EC: 0x14 */ 32 #define ESR_ELx_EC_SVC64 (0x15) 33 #define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */ 34 #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */ 35 #define ESR_ELx_EC_SYS64 (0x18) 36 #define ESR_ELx_EC_SVE (0x19) 37 /* Unallocated EC: 0x1A - 0x1E */ 38 #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */ 39 #define ESR_ELx_EC_IABT_LOW (0x20) 40 #define ESR_ELx_EC_IABT_CUR (0x21) 41 #define ESR_ELx_EC_PC_ALIGN (0x22) 42 /* Unallocated EC: 0x23 */ 43 #define ESR_ELx_EC_DABT_LOW (0x24) 44 #define ESR_ELx_EC_DABT_CUR (0x25) 45 #define ESR_ELx_EC_SP_ALIGN (0x26) 46 /* Unallocated EC: 0x27 */ 47 #define ESR_ELx_EC_FP_EXC32 (0x28) 48 /* Unallocated EC: 0x29 - 0x2B */ 49 #define ESR_ELx_EC_FP_EXC64 (0x2C) 50 /* Unallocated EC: 0x2D - 0x2E */ 51 #define ESR_ELx_EC_SERROR (0x2F) 52 #define ESR_ELx_EC_BREAKPT_LOW (0x30) 53 #define ESR_ELx_EC_BREAKPT_CUR (0x31) 54 #define ESR_ELx_EC_SOFTSTP_LOW (0x32) 55 #define ESR_ELx_EC_SOFTSTP_CUR (0x33) 56 #define ESR_ELx_EC_WATCHPT_LOW (0x34) 57 #define ESR_ELx_EC_WATCHPT_CUR (0x35) 58 /* Unallocated EC: 0x36 - 0x37 */ 59 #define ESR_ELx_EC_BKPT32 (0x38) 60 /* Unallocated EC: 0x39 */ 61 #define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */ 62 /* Unallocted EC: 0x3B */ 63 #define ESR_ELx_EC_BRK64 (0x3C) 64 /* Unallocated EC: 0x3D - 0x3F */ 65 #define ESR_ELx_EC_MAX (0x3F) 66 67 #define ESR_ELx_EC_SHIFT (26) 68 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 69 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 70 71 #define ESR_ELx_IL_SHIFT (25) 72 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 73 #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) 74 75 /* ISS field definitions shared by different classes */ 76 #define ESR_ELx_WNR_SHIFT (6) 77 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 78 79 /* Asynchronous Error Type */ 80 #define ESR_ELx_IDS_SHIFT (24) 81 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) 82 #define ESR_ELx_AET_SHIFT (10) 83 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) 84 85 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) 86 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) 87 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) 88 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) 89 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) 90 91 /* Shared ISS field definitions for Data/Instruction aborts */ 92 #define ESR_ELx_SET_SHIFT (11) 93 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 94 #define ESR_ELx_FnV_SHIFT (10) 95 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 96 #define ESR_ELx_EA_SHIFT (9) 97 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 98 #define ESR_ELx_S1PTW_SHIFT (7) 99 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 100 101 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 102 #define ESR_ELx_FSC (0x3F) 103 #define ESR_ELx_FSC_TYPE (0x3C) 104 #define ESR_ELx_FSC_EXTABT (0x10) 105 #define ESR_ELx_FSC_SERROR (0x11) 106 #define ESR_ELx_FSC_ACCESS (0x08) 107 #define ESR_ELx_FSC_FAULT (0x04) 108 #define ESR_ELx_FSC_PERM (0x0C) 109 110 /* ISS field definitions for Data Aborts */ 111 #define ESR_ELx_ISV_SHIFT (24) 112 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 113 #define ESR_ELx_SAS_SHIFT (22) 114 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 115 #define ESR_ELx_SSE_SHIFT (21) 116 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 117 #define ESR_ELx_SRT_SHIFT (16) 118 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 119 #define ESR_ELx_SF_SHIFT (15) 120 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 121 #define ESR_ELx_AR_SHIFT (14) 122 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 123 #define ESR_ELx_CM_SHIFT (8) 124 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 125 126 /* ISS field definitions for exceptions taken in to Hyp */ 127 #define ESR_ELx_CV (UL(1) << 24) 128 #define ESR_ELx_COND_SHIFT (20) 129 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 130 #define ESR_ELx_WFx_ISS_TI (UL(1) << 0) 131 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) 132 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 133 #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) 134 135 #define DISR_EL1_IDS (UL(1) << 24) 136 /* 137 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean 138 * different things in the future... 139 */ 140 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 141 142 /* ESR value templates for specific events */ 143 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI) 144 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 145 ESR_ELx_WFx_ISS_WFI) 146 147 /* BRK instruction trap from AArch64 state */ 148 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff 149 150 /* ISS field definitions for System instruction traps */ 151 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 152 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 153 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 154 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 155 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 156 157 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 158 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 159 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 160 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 161 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 162 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 163 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 164 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 165 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 166 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 167 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 168 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 169 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 170 ESR_ELx_SYS64_ISS_OP1_MASK | \ 171 ESR_ELx_SYS64_ISS_OP2_MASK | \ 172 ESR_ELx_SYS64_ISS_CRN_MASK | \ 173 ESR_ELx_SYS64_ISS_CRM_MASK) 174 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 175 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 176 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 177 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 178 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 179 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 180 181 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 182 ESR_ELx_SYS64_ISS_DIR_MASK) 183 #define ESR_ELx_SYS64_ISS_RT(esr) \ 184 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) 185 /* 186 * User space cache operations have the following sysreg encoding 187 * in System instructions. 188 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) 189 */ 190 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 191 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 192 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 193 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 194 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 195 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 196 197 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 198 ESR_ELx_SYS64_ISS_OP1_MASK | \ 199 ESR_ELx_SYS64_ISS_OP2_MASK | \ 200 ESR_ELx_SYS64_ISS_CRN_MASK | \ 201 ESR_ELx_SYS64_ISS_DIR_MASK) 202 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 203 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 204 ESR_ELx_SYS64_ISS_DIR_WRITE) 205 /* 206 * User space MRS operations which are supported for emulation 207 * have the following sysreg encoding in System instructions. 208 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) 209 */ 210 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 211 ESR_ELx_SYS64_ISS_OP1_MASK | \ 212 ESR_ELx_SYS64_ISS_CRN_MASK | \ 213 ESR_ELx_SYS64_ISS_DIR_MASK) 214 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ 215 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ 216 ESR_ELx_SYS64_ISS_DIR_READ) 217 218 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 219 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 220 ESR_ELx_SYS64_ISS_DIR_READ) 221 222 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 223 ESR_ELx_SYS64_ISS_DIR_READ) 224 225 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 226 ESR_ELx_SYS64_ISS_DIR_READ) 227 228 #define esr_sys64_to_sysreg(e) \ 229 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 230 ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 231 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 232 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 233 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 234 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 235 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 236 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 237 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 238 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 239 240 #define esr_cp15_to_sysreg(e) \ 241 sys_reg(3, \ 242 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 243 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 244 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 245 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 246 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 247 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 248 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 249 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 250 251 /* 252 * ISS field definitions for floating-point exception traps 253 * (FP_EXC_32/FP_EXC_64). 254 * 255 * (The FPEXC_* constants are used instead for common bits.) 256 */ 257 258 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23) 259 260 /* 261 * ISS field definitions for CP15 accesses 262 */ 263 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 264 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 265 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 266 267 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 268 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) 269 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 270 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) 271 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 272 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) 273 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 274 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) 275 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 276 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) 277 278 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ 279 ESR_ELx_CP15_32_ISS_OP2_MASK | \ 280 ESR_ELx_CP15_32_ISS_CRN_MASK | \ 281 ESR_ELx_CP15_32_ISS_CRM_MASK | \ 282 ESR_ELx_CP15_32_ISS_DIR_MASK) 283 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ 284 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ 285 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ 286 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ 287 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) 288 289 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 290 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 291 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 292 293 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 294 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) 295 296 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 297 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) 298 299 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 300 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) 301 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 302 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) 303 304 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ 305 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ 306 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) 307 308 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ 309 ESR_ELx_CP15_64_ISS_CRM_MASK | \ 310 ESR_ELx_CP15_64_ISS_DIR_MASK) 311 312 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ 313 ESR_ELx_CP15_64_ISS_DIR_READ) 314 315 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ 316 ESR_ELx_CP15_32_ISS_DIR_READ) 317 318 #ifndef __ASSEMBLY__ 319 #include <asm/types.h> 320 321 static inline bool esr_is_data_abort(u32 esr) 322 { 323 const u32 ec = ESR_ELx_EC(esr); 324 325 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 326 } 327 328 const char *esr_get_class_string(u32 esr); 329 #endif /* __ASSEMBLY */ 330 331 #endif /* __ASM_ESR_H */ 332