1 /* 2 * Copyright (C) 2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __ASM_ESR_H 19 #define __ASM_ESR_H 20 21 #include <asm/memory.h> 22 #include <asm/sysreg.h> 23 24 #define ESR_ELx_EC_UNKNOWN (0x00) 25 #define ESR_ELx_EC_WFx (0x01) 26 /* Unallocated EC: 0x02 */ 27 #define ESR_ELx_EC_CP15_32 (0x03) 28 #define ESR_ELx_EC_CP15_64 (0x04) 29 #define ESR_ELx_EC_CP14_MR (0x05) 30 #define ESR_ELx_EC_CP14_LS (0x06) 31 #define ESR_ELx_EC_FP_ASIMD (0x07) 32 #define ESR_ELx_EC_CP10_ID (0x08) 33 /* Unallocated EC: 0x09 - 0x0B */ 34 #define ESR_ELx_EC_CP14_64 (0x0C) 35 /* Unallocated EC: 0x0d */ 36 #define ESR_ELx_EC_ILL (0x0E) 37 /* Unallocated EC: 0x0F - 0x10 */ 38 #define ESR_ELx_EC_SVC32 (0x11) 39 #define ESR_ELx_EC_HVC32 (0x12) 40 #define ESR_ELx_EC_SMC32 (0x13) 41 /* Unallocated EC: 0x14 */ 42 #define ESR_ELx_EC_SVC64 (0x15) 43 #define ESR_ELx_EC_HVC64 (0x16) 44 #define ESR_ELx_EC_SMC64 (0x17) 45 #define ESR_ELx_EC_SYS64 (0x18) 46 #define ESR_ELx_EC_SVE (0x19) 47 /* Unallocated EC: 0x1A - 0x1E */ 48 #define ESR_ELx_EC_IMP_DEF (0x1f) 49 #define ESR_ELx_EC_IABT_LOW (0x20) 50 #define ESR_ELx_EC_IABT_CUR (0x21) 51 #define ESR_ELx_EC_PC_ALIGN (0x22) 52 /* Unallocated EC: 0x23 */ 53 #define ESR_ELx_EC_DABT_LOW (0x24) 54 #define ESR_ELx_EC_DABT_CUR (0x25) 55 #define ESR_ELx_EC_SP_ALIGN (0x26) 56 /* Unallocated EC: 0x27 */ 57 #define ESR_ELx_EC_FP_EXC32 (0x28) 58 /* Unallocated EC: 0x29 - 0x2B */ 59 #define ESR_ELx_EC_FP_EXC64 (0x2C) 60 /* Unallocated EC: 0x2D - 0x2E */ 61 #define ESR_ELx_EC_SERROR (0x2F) 62 #define ESR_ELx_EC_BREAKPT_LOW (0x30) 63 #define ESR_ELx_EC_BREAKPT_CUR (0x31) 64 #define ESR_ELx_EC_SOFTSTP_LOW (0x32) 65 #define ESR_ELx_EC_SOFTSTP_CUR (0x33) 66 #define ESR_ELx_EC_WATCHPT_LOW (0x34) 67 #define ESR_ELx_EC_WATCHPT_CUR (0x35) 68 /* Unallocated EC: 0x36 - 0x37 */ 69 #define ESR_ELx_EC_BKPT32 (0x38) 70 /* Unallocated EC: 0x39 */ 71 #define ESR_ELx_EC_VECTOR32 (0x3A) 72 /* Unallocted EC: 0x3B */ 73 #define ESR_ELx_EC_BRK64 (0x3C) 74 /* Unallocated EC: 0x3D - 0x3F */ 75 #define ESR_ELx_EC_MAX (0x3F) 76 77 #define ESR_ELx_EC_SHIFT (26) 78 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 79 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 80 81 #define ESR_ELx_IL_SHIFT (25) 82 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 83 #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) 84 85 /* ISS field definitions shared by different classes */ 86 #define ESR_ELx_WNR_SHIFT (6) 87 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 88 89 /* Shared ISS field definitions for Data/Instruction aborts */ 90 #define ESR_ELx_SET_SHIFT (11) 91 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 92 #define ESR_ELx_FnV_SHIFT (10) 93 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 94 #define ESR_ELx_EA_SHIFT (9) 95 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 96 #define ESR_ELx_S1PTW_SHIFT (7) 97 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 98 99 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 100 #define ESR_ELx_FSC (0x3F) 101 #define ESR_ELx_FSC_TYPE (0x3C) 102 #define ESR_ELx_FSC_EXTABT (0x10) 103 #define ESR_ELx_FSC_ACCESS (0x08) 104 #define ESR_ELx_FSC_FAULT (0x04) 105 #define ESR_ELx_FSC_PERM (0x0C) 106 107 /* ISS field definitions for Data Aborts */ 108 #define ESR_ELx_ISV_SHIFT (24) 109 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 110 #define ESR_ELx_SAS_SHIFT (22) 111 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 112 #define ESR_ELx_SSE_SHIFT (21) 113 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 114 #define ESR_ELx_SRT_SHIFT (16) 115 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 116 #define ESR_ELx_SF_SHIFT (15) 117 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 118 #define ESR_ELx_AR_SHIFT (14) 119 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 120 #define ESR_ELx_CM_SHIFT (8) 121 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 122 123 /* ISS field definitions for exceptions taken in to Hyp */ 124 #define ESR_ELx_CV (UL(1) << 24) 125 #define ESR_ELx_COND_SHIFT (20) 126 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 127 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 128 #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) 129 130 /* ESR value templates for specific events */ 131 132 /* BRK instruction trap from AArch64 state */ 133 #define ESR_ELx_VAL_BRK64(imm) \ 134 ((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | \ 135 ((imm) & 0xffff)) 136 137 /* ISS field definitions for System instruction traps */ 138 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 139 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 140 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 141 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 142 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 143 144 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 145 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 146 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 147 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 148 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 149 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 150 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 151 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 152 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 153 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 154 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 155 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 156 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 157 ESR_ELx_SYS64_ISS_OP1_MASK | \ 158 ESR_ELx_SYS64_ISS_OP2_MASK | \ 159 ESR_ELx_SYS64_ISS_CRN_MASK | \ 160 ESR_ELx_SYS64_ISS_CRM_MASK) 161 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 162 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 163 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 164 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 165 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 166 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 167 168 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 169 ESR_ELx_SYS64_ISS_DIR_MASK) 170 /* 171 * User space cache operations have the following sysreg encoding 172 * in System instructions. 173 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0) 174 */ 175 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 176 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 177 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 178 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 179 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 180 181 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 182 ESR_ELx_SYS64_ISS_OP1_MASK | \ 183 ESR_ELx_SYS64_ISS_OP2_MASK | \ 184 ESR_ELx_SYS64_ISS_CRN_MASK | \ 185 ESR_ELx_SYS64_ISS_DIR_MASK) 186 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 187 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 188 ESR_ELx_SYS64_ISS_DIR_WRITE) 189 190 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 191 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 192 ESR_ELx_SYS64_ISS_DIR_READ) 193 194 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 195 ESR_ELx_SYS64_ISS_DIR_READ) 196 197 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 198 ESR_ELx_SYS64_ISS_DIR_READ) 199 200 #define esr_sys64_to_sysreg(e) \ 201 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 202 ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 203 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 204 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 205 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 206 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 207 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 208 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 209 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 210 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 211 212 #define esr_cp15_to_sysreg(e) \ 213 sys_reg(3, \ 214 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 215 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 216 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 217 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 218 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 219 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 220 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 221 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 222 223 #ifndef __ASSEMBLY__ 224 #include <asm/types.h> 225 226 static inline bool esr_is_data_abort(u32 esr) 227 { 228 const u32 ec = ESR_ELx_EC(esr); 229 230 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 231 } 232 233 const char *esr_get_class_string(u32 esr); 234 #endif /* __ASSEMBLY */ 235 236 #endif /* __ASM_ESR_H */ 237