1 /* 2 * Copyright (C) 2013 - ARM Ltd 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #ifndef __ASM_ESR_H 19 #define __ASM_ESR_H 20 21 #include <asm/memory.h> 22 #include <asm/sysreg.h> 23 24 #define ESR_ELx_EC_UNKNOWN (0x00) 25 #define ESR_ELx_EC_WFx (0x01) 26 /* Unallocated EC: 0x02 */ 27 #define ESR_ELx_EC_CP15_32 (0x03) 28 #define ESR_ELx_EC_CP15_64 (0x04) 29 #define ESR_ELx_EC_CP14_MR (0x05) 30 #define ESR_ELx_EC_CP14_LS (0x06) 31 #define ESR_ELx_EC_FP_ASIMD (0x07) 32 #define ESR_ELx_EC_CP10_ID (0x08) 33 /* Unallocated EC: 0x09 - 0x0B */ 34 #define ESR_ELx_EC_CP14_64 (0x0C) 35 /* Unallocated EC: 0x0d */ 36 #define ESR_ELx_EC_ILL (0x0E) 37 /* Unallocated EC: 0x0F - 0x10 */ 38 #define ESR_ELx_EC_SVC32 (0x11) 39 #define ESR_ELx_EC_HVC32 (0x12) 40 #define ESR_ELx_EC_SMC32 (0x13) 41 /* Unallocated EC: 0x14 */ 42 #define ESR_ELx_EC_SVC64 (0x15) 43 #define ESR_ELx_EC_HVC64 (0x16) 44 #define ESR_ELx_EC_SMC64 (0x17) 45 #define ESR_ELx_EC_SYS64 (0x18) 46 /* Unallocated EC: 0x19 - 0x1E */ 47 #define ESR_ELx_EC_IMP_DEF (0x1f) 48 #define ESR_ELx_EC_IABT_LOW (0x20) 49 #define ESR_ELx_EC_IABT_CUR (0x21) 50 #define ESR_ELx_EC_PC_ALIGN (0x22) 51 /* Unallocated EC: 0x23 */ 52 #define ESR_ELx_EC_DABT_LOW (0x24) 53 #define ESR_ELx_EC_DABT_CUR (0x25) 54 #define ESR_ELx_EC_SP_ALIGN (0x26) 55 /* Unallocated EC: 0x27 */ 56 #define ESR_ELx_EC_FP_EXC32 (0x28) 57 /* Unallocated EC: 0x29 - 0x2B */ 58 #define ESR_ELx_EC_FP_EXC64 (0x2C) 59 /* Unallocated EC: 0x2D - 0x2E */ 60 #define ESR_ELx_EC_SERROR (0x2F) 61 #define ESR_ELx_EC_BREAKPT_LOW (0x30) 62 #define ESR_ELx_EC_BREAKPT_CUR (0x31) 63 #define ESR_ELx_EC_SOFTSTP_LOW (0x32) 64 #define ESR_ELx_EC_SOFTSTP_CUR (0x33) 65 #define ESR_ELx_EC_WATCHPT_LOW (0x34) 66 #define ESR_ELx_EC_WATCHPT_CUR (0x35) 67 /* Unallocated EC: 0x36 - 0x37 */ 68 #define ESR_ELx_EC_BKPT32 (0x38) 69 /* Unallocated EC: 0x39 */ 70 #define ESR_ELx_EC_VECTOR32 (0x3A) 71 /* Unallocted EC: 0x3B */ 72 #define ESR_ELx_EC_BRK64 (0x3C) 73 /* Unallocated EC: 0x3D - 0x3F */ 74 #define ESR_ELx_EC_MAX (0x3F) 75 76 #define ESR_ELx_EC_SHIFT (26) 77 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 78 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 79 80 #define ESR_ELx_IL_SHIFT (25) 81 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 82 #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) 83 84 /* ISS field definitions shared by different classes */ 85 #define ESR_ELx_WNR_SHIFT (6) 86 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 87 88 /* Shared ISS field definitions for Data/Instruction aborts */ 89 #define ESR_ELx_SET_SHIFT (11) 90 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 91 #define ESR_ELx_FnV_SHIFT (10) 92 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 93 #define ESR_ELx_EA_SHIFT (9) 94 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 95 #define ESR_ELx_S1PTW_SHIFT (7) 96 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 97 98 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 99 #define ESR_ELx_FSC (0x3F) 100 #define ESR_ELx_FSC_TYPE (0x3C) 101 #define ESR_ELx_FSC_EXTABT (0x10) 102 #define ESR_ELx_FSC_ACCESS (0x08) 103 #define ESR_ELx_FSC_FAULT (0x04) 104 #define ESR_ELx_FSC_PERM (0x0C) 105 106 /* ISS field definitions for Data Aborts */ 107 #define ESR_ELx_ISV_SHIFT (24) 108 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 109 #define ESR_ELx_SAS_SHIFT (22) 110 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 111 #define ESR_ELx_SSE_SHIFT (21) 112 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 113 #define ESR_ELx_SRT_SHIFT (16) 114 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 115 #define ESR_ELx_SF_SHIFT (15) 116 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 117 #define ESR_ELx_AR_SHIFT (14) 118 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 119 #define ESR_ELx_CM_SHIFT (8) 120 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 121 122 /* ISS field definitions for exceptions taken in to Hyp */ 123 #define ESR_ELx_CV (UL(1) << 24) 124 #define ESR_ELx_COND_SHIFT (20) 125 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 126 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 127 #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1) 128 129 /* ESR value templates for specific events */ 130 131 /* BRK instruction trap from AArch64 state */ 132 #define ESR_ELx_VAL_BRK64(imm) \ 133 ((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL | \ 134 ((imm) & 0xffff)) 135 136 /* ISS field definitions for System instruction traps */ 137 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 138 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 139 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 140 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 141 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 142 143 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 144 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 145 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 146 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 147 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 148 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 149 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 150 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 151 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 152 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 153 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 154 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 155 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 156 ESR_ELx_SYS64_ISS_OP1_MASK | \ 157 ESR_ELx_SYS64_ISS_OP2_MASK | \ 158 ESR_ELx_SYS64_ISS_CRN_MASK | \ 159 ESR_ELx_SYS64_ISS_CRM_MASK) 160 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 161 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 162 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 163 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 164 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 165 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 166 167 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 168 ESR_ELx_SYS64_ISS_DIR_MASK) 169 /* 170 * User space cache operations have the following sysreg encoding 171 * in System instructions. 172 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0) 173 */ 174 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 175 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 176 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 177 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 178 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 179 180 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 181 ESR_ELx_SYS64_ISS_OP1_MASK | \ 182 ESR_ELx_SYS64_ISS_OP2_MASK | \ 183 ESR_ELx_SYS64_ISS_CRN_MASK | \ 184 ESR_ELx_SYS64_ISS_DIR_MASK) 185 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 186 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 187 ESR_ELx_SYS64_ISS_DIR_WRITE) 188 189 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 190 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 191 ESR_ELx_SYS64_ISS_DIR_READ) 192 193 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 194 ESR_ELx_SYS64_ISS_DIR_READ) 195 196 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 197 ESR_ELx_SYS64_ISS_DIR_READ) 198 199 #define esr_sys64_to_sysreg(e) \ 200 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 201 ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 202 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 203 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 204 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 205 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 206 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 207 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 208 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 209 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 210 211 #define esr_cp15_to_sysreg(e) \ 212 sys_reg(3, \ 213 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 214 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 215 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 216 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 217 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 218 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 219 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 220 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 221 222 #ifndef __ASSEMBLY__ 223 #include <asm/types.h> 224 225 static inline bool esr_is_data_abort(u32 esr) 226 { 227 const u32 ec = ESR_ELx_EC(esr); 228 229 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 230 } 231 232 const char *esr_get_class_string(u32 esr); 233 #endif /* __ASSEMBLY */ 234 235 #endif /* __ASM_ESR_H */ 236