1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ASM_ESR_H 8 #define __ASM_ESR_H 9 10 #include <asm/memory.h> 11 #include <asm/sysreg.h> 12 13 #define ESR_ELx_EC_UNKNOWN (0x00) 14 #define ESR_ELx_EC_WFx (0x01) 15 /* Unallocated EC: 0x02 */ 16 #define ESR_ELx_EC_CP15_32 (0x03) 17 #define ESR_ELx_EC_CP15_64 (0x04) 18 #define ESR_ELx_EC_CP14_MR (0x05) 19 #define ESR_ELx_EC_CP14_LS (0x06) 20 #define ESR_ELx_EC_FP_ASIMD (0x07) 21 #define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */ 22 #define ESR_ELx_EC_PAC (0x09) /* EL2 and above */ 23 /* Unallocated EC: 0x0A - 0x0B */ 24 #define ESR_ELx_EC_CP14_64 (0x0C) 25 #define ESR_ELx_EC_BTI (0x0D) 26 #define ESR_ELx_EC_ILL (0x0E) 27 /* Unallocated EC: 0x0F - 0x10 */ 28 #define ESR_ELx_EC_SVC32 (0x11) 29 #define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */ 30 #define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */ 31 /* Unallocated EC: 0x14 */ 32 #define ESR_ELx_EC_SVC64 (0x15) 33 #define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */ 34 #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */ 35 #define ESR_ELx_EC_SYS64 (0x18) 36 #define ESR_ELx_EC_SVE (0x19) 37 #define ESR_ELx_EC_ERET (0x1a) /* EL2 only */ 38 /* Unallocated EC: 0x1B */ 39 #define ESR_ELx_EC_FPAC (0x1C) /* EL1 and above */ 40 #define ESR_ELx_EC_SME (0x1D) 41 /* Unallocated EC: 0x1E */ 42 #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */ 43 #define ESR_ELx_EC_IABT_LOW (0x20) 44 #define ESR_ELx_EC_IABT_CUR (0x21) 45 #define ESR_ELx_EC_PC_ALIGN (0x22) 46 /* Unallocated EC: 0x23 */ 47 #define ESR_ELx_EC_DABT_LOW (0x24) 48 #define ESR_ELx_EC_DABT_CUR (0x25) 49 #define ESR_ELx_EC_SP_ALIGN (0x26) 50 /* Unallocated EC: 0x27 */ 51 #define ESR_ELx_EC_FP_EXC32 (0x28) 52 /* Unallocated EC: 0x29 - 0x2B */ 53 #define ESR_ELx_EC_FP_EXC64 (0x2C) 54 /* Unallocated EC: 0x2D - 0x2E */ 55 #define ESR_ELx_EC_SERROR (0x2F) 56 #define ESR_ELx_EC_BREAKPT_LOW (0x30) 57 #define ESR_ELx_EC_BREAKPT_CUR (0x31) 58 #define ESR_ELx_EC_SOFTSTP_LOW (0x32) 59 #define ESR_ELx_EC_SOFTSTP_CUR (0x33) 60 #define ESR_ELx_EC_WATCHPT_LOW (0x34) 61 #define ESR_ELx_EC_WATCHPT_CUR (0x35) 62 /* Unallocated EC: 0x36 - 0x37 */ 63 #define ESR_ELx_EC_BKPT32 (0x38) 64 /* Unallocated EC: 0x39 */ 65 #define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */ 66 /* Unallocated EC: 0x3B */ 67 #define ESR_ELx_EC_BRK64 (0x3C) 68 /* Unallocated EC: 0x3D - 0x3F */ 69 #define ESR_ELx_EC_MAX (0x3F) 70 71 #define ESR_ELx_EC_SHIFT (26) 72 #define ESR_ELx_EC_WIDTH (6) 73 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT) 74 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT) 75 76 #define ESR_ELx_IL_SHIFT (25) 77 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT) 78 #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1) 79 #define ESR_ELx_ISS(esr) ((esr) & ESR_ELx_ISS_MASK) 80 81 /* ISS field definitions shared by different classes */ 82 #define ESR_ELx_WNR_SHIFT (6) 83 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT) 84 85 /* Asynchronous Error Type */ 86 #define ESR_ELx_IDS_SHIFT (24) 87 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT) 88 #define ESR_ELx_AET_SHIFT (10) 89 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT) 90 91 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT) 92 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT) 93 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT) 94 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT) 95 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT) 96 97 /* Shared ISS field definitions for Data/Instruction aborts */ 98 #define ESR_ELx_SET_SHIFT (11) 99 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT) 100 #define ESR_ELx_FnV_SHIFT (10) 101 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT) 102 #define ESR_ELx_EA_SHIFT (9) 103 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT) 104 #define ESR_ELx_S1PTW_SHIFT (7) 105 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT) 106 107 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */ 108 #define ESR_ELx_FSC (0x3F) 109 #define ESR_ELx_FSC_TYPE (0x3C) 110 #define ESR_ELx_FSC_LEVEL (0x03) 111 #define ESR_ELx_FSC_EXTABT (0x10) 112 #define ESR_ELx_FSC_MTE (0x11) 113 #define ESR_ELx_FSC_SERROR (0x11) 114 #define ESR_ELx_FSC_ACCESS (0x08) 115 #define ESR_ELx_FSC_FAULT (0x04) 116 #define ESR_ELx_FSC_PERM (0x0C) 117 118 /* ISS field definitions for Data Aborts */ 119 #define ESR_ELx_ISV_SHIFT (24) 120 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT) 121 #define ESR_ELx_SAS_SHIFT (22) 122 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT) 123 #define ESR_ELx_SSE_SHIFT (21) 124 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT) 125 #define ESR_ELx_SRT_SHIFT (16) 126 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT) 127 #define ESR_ELx_SF_SHIFT (15) 128 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT) 129 #define ESR_ELx_AR_SHIFT (14) 130 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT) 131 #define ESR_ELx_CM_SHIFT (8) 132 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT) 133 134 /* ISS field definitions for exceptions taken in to Hyp */ 135 #define ESR_ELx_CV (UL(1) << 24) 136 #define ESR_ELx_COND_SHIFT (20) 137 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT) 138 #define ESR_ELx_WFx_ISS_RN (UL(0x1F) << 5) 139 #define ESR_ELx_WFx_ISS_RV (UL(1) << 2) 140 #define ESR_ELx_WFx_ISS_TI (UL(3) << 0) 141 #define ESR_ELx_WFx_ISS_WFxT (UL(2) << 0) 142 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0) 143 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0) 144 #define ESR_ELx_xVC_IMM_MASK ((UL(1) << 16) - 1) 145 146 #define DISR_EL1_IDS (UL(1) << 24) 147 /* 148 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean 149 * different things in the future... 150 */ 151 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC) 152 153 /* ESR value templates for specific events */ 154 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | \ 155 (ESR_ELx_WFx_ISS_TI & ~ESR_ELx_WFx_ISS_WFxT)) 156 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \ 157 ESR_ELx_WFx_ISS_WFI) 158 159 /* BRK instruction trap from AArch64 state */ 160 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff 161 162 /* ISS field definitions for System instruction traps */ 163 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22 164 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT) 165 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1 166 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1 167 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0 168 169 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5 170 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT) 171 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1 172 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT) 173 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10 174 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT) 175 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14 176 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT) 177 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17 178 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT) 179 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20 180 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT) 181 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 182 ESR_ELx_SYS64_ISS_OP1_MASK | \ 183 ESR_ELx_SYS64_ISS_OP2_MASK | \ 184 ESR_ELx_SYS64_ISS_CRN_MASK | \ 185 ESR_ELx_SYS64_ISS_CRM_MASK) 186 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \ 187 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \ 188 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \ 189 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \ 190 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \ 191 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT)) 192 193 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \ 194 ESR_ELx_SYS64_ISS_DIR_MASK) 195 #define ESR_ELx_SYS64_ISS_RT(esr) \ 196 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT) 197 /* 198 * User space cache operations have the following sysreg encoding 199 * in System instructions. 200 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0) 201 */ 202 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14 203 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13 204 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12 205 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11 206 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10 207 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5 208 209 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 210 ESR_ELx_SYS64_ISS_OP1_MASK | \ 211 ESR_ELx_SYS64_ISS_OP2_MASK | \ 212 ESR_ELx_SYS64_ISS_CRN_MASK | \ 213 ESR_ELx_SYS64_ISS_DIR_MASK) 214 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \ 215 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \ 216 ESR_ELx_SYS64_ISS_DIR_WRITE) 217 /* 218 * User space MRS operations which are supported for emulation 219 * have the following sysreg encoding in System instructions. 220 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1) 221 */ 222 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \ 223 ESR_ELx_SYS64_ISS_OP1_MASK | \ 224 ESR_ELx_SYS64_ISS_CRN_MASK | \ 225 ESR_ELx_SYS64_ISS_DIR_MASK) 226 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \ 227 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \ 228 ESR_ELx_SYS64_ISS_DIR_READ) 229 230 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0) 231 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \ 232 ESR_ELx_SYS64_ISS_DIR_READ) 233 234 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \ 235 ESR_ELx_SYS64_ISS_DIR_READ) 236 237 #define ESR_ELx_SYS64_ISS_SYS_CNTVCTSS (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 6, 14, 0) | \ 238 ESR_ELx_SYS64_ISS_DIR_READ) 239 240 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \ 241 ESR_ELx_SYS64_ISS_DIR_READ) 242 243 #define esr_sys64_to_sysreg(e) \ 244 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \ 245 ESR_ELx_SYS64_ISS_OP0_SHIFT), \ 246 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 247 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 248 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 249 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 250 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 251 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 252 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 253 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 254 255 #define esr_cp15_to_sysreg(e) \ 256 sys_reg(3, \ 257 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \ 258 ESR_ELx_SYS64_ISS_OP1_SHIFT), \ 259 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \ 260 ESR_ELx_SYS64_ISS_CRN_SHIFT), \ 261 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \ 262 ESR_ELx_SYS64_ISS_CRM_SHIFT), \ 263 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \ 264 ESR_ELx_SYS64_ISS_OP2_SHIFT)) 265 266 /* 267 * ISS field definitions for floating-point exception traps 268 * (FP_EXC_32/FP_EXC_64). 269 * 270 * (The FPEXC_* constants are used instead for common bits.) 271 */ 272 273 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23) 274 275 /* 276 * ISS field definitions for CP15 accesses 277 */ 278 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1 279 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1 280 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0 281 282 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5 283 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT) 284 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1 285 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT) 286 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10 287 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) 288 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14 289 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) 290 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17 291 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) 292 293 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \ 294 ESR_ELx_CP15_32_ISS_OP2_MASK | \ 295 ESR_ELx_CP15_32_ISS_CRN_MASK | \ 296 ESR_ELx_CP15_32_ISS_CRM_MASK | \ 297 ESR_ELx_CP15_32_ISS_DIR_MASK) 298 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \ 299 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \ 300 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \ 301 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \ 302 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)) 303 304 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1 305 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1 306 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0 307 308 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5 309 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT) 310 311 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10 312 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT) 313 314 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16 315 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) 316 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1 317 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT) 318 319 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \ 320 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \ 321 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)) 322 323 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \ 324 ESR_ELx_CP15_64_ISS_CRM_MASK | \ 325 ESR_ELx_CP15_64_ISS_DIR_MASK) 326 327 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \ 328 ESR_ELx_CP15_64_ISS_DIR_READ) 329 330 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCTSS (ESR_ELx_CP15_64_ISS_SYS_VAL(9, 14) | \ 331 ESR_ELx_CP15_64_ISS_DIR_READ) 332 333 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\ 334 ESR_ELx_CP15_32_ISS_DIR_READ) 335 336 /* 337 * ISS values for SME traps 338 */ 339 340 #define ESR_ELx_SME_ISS_SME_DISABLED 0 341 #define ESR_ELx_SME_ISS_ILL 1 342 #define ESR_ELx_SME_ISS_SM_DISABLED 2 343 #define ESR_ELx_SME_ISS_ZA_DISABLED 3 344 345 #ifndef __ASSEMBLY__ 346 #include <asm/types.h> 347 348 static inline bool esr_is_data_abort(unsigned long esr) 349 { 350 const unsigned long ec = ESR_ELx_EC(esr); 351 352 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR; 353 } 354 355 const char *esr_get_class_string(unsigned long esr); 356 #endif /* __ASSEMBLY */ 357 358 #endif /* __ASM_ESR_H */ 359