1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM_KVM_INIT_H__ 8 #define __ARM_KVM_INIT_H__ 9 10 #ifndef __ASSEMBLY__ 11 #error Assembly-only header 12 #endif 13 14 #include <asm/kvm_arm.h> 15 #include <asm/ptrace.h> 16 #include <asm/sysreg.h> 17 #include <linux/irqchip/arm-gic-v3.h> 18 19 .macro __init_el2_sctlr 20 mov_q x0, INIT_SCTLR_EL2_MMU_OFF 21 msr sctlr_el2, x0 22 isb 23 .endm 24 25 .macro __init_el2_hcrx 26 mrs x0, id_aa64mmfr1_el1 27 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4 28 cbz x0, .Lskip_hcrx_\@ 29 mov_q x0, HCRX_HOST_FLAGS 30 msr_s SYS_HCRX_EL2, x0 31 .Lskip_hcrx_\@: 32 .endm 33 34 /* 35 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 36 * This is not necessary for VHE, since the host kernel runs in EL2, 37 * and EL0 accesses are configured in the later stage of boot process. 38 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 39 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 40 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 41 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 42 * EL2. 43 */ 44 .macro __init_el2_timers 45 mov x0, #3 // Enable EL1 physical timers 46 mrs x1, hcr_el2 47 and x1, x1, #HCR_E2H 48 cbz x1, .LnVHE_\@ 49 lsl x0, x0, #10 50 .LnVHE_\@: 51 msr cnthctl_el2, x0 52 msr cntvoff_el2, xzr // Clear virtual offset 53 .endm 54 55 .macro __init_el2_debug 56 mrs x1, id_aa64dfr0_el1 57 sbfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 58 cmp x0, #1 59 b.lt .Lskip_pmu_\@ // Skip if no PMU present 60 mrs x0, pmcr_el0 // Disable debug access traps 61 ubfx x0, x0, #11, #5 // to EL2 and allow access to 62 .Lskip_pmu_\@: 63 csel x2, xzr, x0, lt // all PMU counters from EL1 64 65 /* Statistical profiling */ 66 ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 67 cbz x0, .Lskip_spe_\@ // Skip if SPE not present 68 69 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, 70 and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) 71 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical 72 mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ 73 1 << PMSCR_EL2_PA_SHIFT) 74 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter 75 .Lskip_spe_el2_\@: 76 mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) 77 orr x2, x2, x0 // If we don't have VHE, then 78 // use EL1&0 translation. 79 80 .Lskip_spe_\@: 81 /* Trace buffer */ 82 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4 83 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present 84 85 mrs_s x0, SYS_TRBIDR_EL1 86 and x0, x0, TRBIDR_EL1_P 87 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2 88 89 mov x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT) 90 orr x2, x2, x0 // allow the EL1&0 translation 91 // to own it. 92 93 .Lskip_trace_\@: 94 msr mdcr_el2, x2 // Configure debug traps 95 .endm 96 97 /* LORegions */ 98 .macro __init_el2_lor 99 mrs x1, id_aa64mmfr1_el1 100 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4 101 cbz x0, .Lskip_lor_\@ 102 msr_s SYS_LORC_EL1, xzr 103 .Lskip_lor_\@: 104 .endm 105 106 /* Stage-2 translation */ 107 .macro __init_el2_stage2 108 msr vttbr_el2, xzr 109 .endm 110 111 /* GICv3 system register access */ 112 .macro __init_el2_gicv3 113 mrs x0, id_aa64pfr0_el1 114 ubfx x0, x0, #ID_AA64PFR0_EL1_GIC_SHIFT, #4 115 cbz x0, .Lskip_gicv3_\@ 116 117 mrs_s x0, SYS_ICC_SRE_EL2 118 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 119 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 120 msr_s SYS_ICC_SRE_EL2, x0 121 isb // Make sure SRE is now set 122 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 123 tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks 124 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICH_HCR_EL2 to defaults 125 .Lskip_gicv3_\@: 126 .endm 127 128 .macro __init_el2_hstr 129 msr hstr_el2, xzr // Disable CP15 traps to EL2 130 .endm 131 132 /* Virtual CPU ID registers */ 133 .macro __init_el2_nvhe_idregs 134 mrs x0, midr_el1 135 mrs x1, mpidr_el1 136 msr vpidr_el2, x0 137 msr vmpidr_el2, x1 138 .endm 139 140 /* Coprocessor traps */ 141 .macro __init_el2_cptr 142 mrs x1, hcr_el2 143 and x1, x1, #HCR_E2H 144 cbz x1, .LnVHE_\@ 145 mov x0, #(CPACR_EL1_FPEN_EL1EN | CPACR_EL1_FPEN_EL0EN) 146 b .Lset_cptr_\@ 147 .LnVHE_\@: 148 mov x0, #0x33ff 149 .Lset_cptr_\@: 150 msr cptr_el2, x0 // Disable copro. traps to EL2 151 .endm 152 153 /* Disable any fine grained traps */ 154 .macro __init_el2_fgt 155 mrs x1, id_aa64mmfr0_el1 156 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 157 cbz x1, .Lskip_fgt_\@ 158 159 mov x0, xzr 160 mrs x1, id_aa64dfr0_el1 161 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 162 cmp x1, #3 163 b.lt .Lset_debug_fgt_\@ 164 /* Disable PMSNEVFR_EL1 read and write traps */ 165 orr x0, x0, #(1 << 62) 166 167 .Lset_debug_fgt_\@: 168 msr_s SYS_HDFGRTR_EL2, x0 169 msr_s SYS_HDFGWTR_EL2, x0 170 171 mov x0, xzr 172 mrs x1, id_aa64pfr1_el1 173 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4 174 cbz x1, .Lset_pie_fgt_\@ 175 176 /* Disable nVHE traps of TPIDR2 and SMPRI */ 177 orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK 178 orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK 179 180 .Lset_pie_fgt_\@: 181 mrs_s x1, SYS_ID_AA64MMFR3_EL1 182 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 183 cbz x1, .Lset_fgt_\@ 184 185 /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ 186 orr x0, x0, #HFGxTR_EL2_nPIR_EL1 187 orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 188 189 .Lset_fgt_\@: 190 msr_s SYS_HFGRTR_EL2, x0 191 msr_s SYS_HFGWTR_EL2, x0 192 msr_s SYS_HFGITR_EL2, xzr 193 194 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU 195 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 196 cbz x1, .Lskip_fgt_\@ 197 198 msr_s SYS_HAFGRTR_EL2, xzr 199 .Lskip_fgt_\@: 200 .endm 201 202 .macro __init_el2_nvhe_prepare_eret 203 mov x0, #INIT_PSTATE_EL1 204 msr spsr_el2, x0 205 .endm 206 207 /** 208 * Initialize EL2 registers to sane values. This should be called early on all 209 * cores that were booted in EL2. Note that everything gets initialised as 210 * if VHE was not available. The kernel context will be upgraded to VHE 211 * if possible later on in the boot process 212 * 213 * Regs: x0, x1 and x2 are clobbered. 214 */ 215 .macro init_el2_state 216 __init_el2_sctlr 217 __init_el2_hcrx 218 __init_el2_timers 219 __init_el2_debug 220 __init_el2_lor 221 __init_el2_stage2 222 __init_el2_gicv3 223 __init_el2_hstr 224 __init_el2_nvhe_idregs 225 __init_el2_cptr 226 __init_el2_fgt 227 .endm 228 229 #ifndef __KVM_NVHE_HYPERVISOR__ 230 // This will clobber tmp1 and tmp2, and expect tmp1 to contain 231 // the id register value as read from the HW 232 .macro __check_override idreg, fld, width, pass, fail, tmp1, tmp2 233 ubfx \tmp1, \tmp1, #\fld, #\width 234 cbz \tmp1, \fail 235 236 adr_l \tmp1, \idreg\()_override 237 ldr \tmp2, [\tmp1, FTR_OVR_VAL_OFFSET] 238 ldr \tmp1, [\tmp1, FTR_OVR_MASK_OFFSET] 239 ubfx \tmp2, \tmp2, #\fld, #\width 240 ubfx \tmp1, \tmp1, #\fld, #\width 241 cmp \tmp1, xzr 242 and \tmp2, \tmp2, \tmp1 243 csinv \tmp2, \tmp2, xzr, ne 244 cbnz \tmp2, \pass 245 b \fail 246 .endm 247 248 // This will clobber tmp1 and tmp2 249 .macro check_override idreg, fld, pass, fail, tmp1, tmp2 250 mrs \tmp1, \idreg\()_el1 251 __check_override \idreg \fld 4 \pass \fail \tmp1 \tmp2 252 .endm 253 #else 254 // This will clobber tmp 255 .macro __check_override idreg, fld, width, pass, fail, tmp, ignore 256 ldr_l \tmp, \idreg\()_el1_sys_val 257 ubfx \tmp, \tmp, #\fld, #\width 258 cbnz \tmp, \pass 259 b \fail 260 .endm 261 262 .macro check_override idreg, fld, pass, fail, tmp, ignore 263 __check_override \idreg \fld 4 \pass \fail \tmp \ignore 264 .endm 265 #endif 266 267 .macro finalise_el2_state 268 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2 269 270 .Linit_sve_\@: /* SVE register access */ 271 mrs x0, cptr_el2 // Disable SVE traps 272 mrs x1, hcr_el2 273 and x1, x1, #HCR_E2H 274 cbz x1, .Lcptr_nvhe_\@ 275 276 // VHE case 277 orr x0, x0, #(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN) 278 b .Lset_cptr_\@ 279 280 .Lcptr_nvhe_\@: // nVHE case 281 bic x0, x0, #CPTR_EL2_TZ 282 .Lset_cptr_\@: 283 msr cptr_el2, x0 284 isb 285 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 286 msr_s SYS_ZCR_EL2, x1 // length for EL1. 287 288 .Lskip_sve_\@: 289 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2 290 291 .Linit_sme_\@: /* SME register access and priority mapping */ 292 mrs x0, cptr_el2 // Disable SME traps 293 bic x0, x0, #CPTR_EL2_TSM 294 msr cptr_el2, x0 295 isb 296 297 mrs x1, sctlr_el2 298 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps 299 msr sctlr_el2, x1 300 isb 301 302 mov x0, #0 // SMCR controls 303 304 // Full FP in SM? 305 mrs_s x1, SYS_ID_AA64SMFR0_EL1 306 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2 307 308 .Linit_sme_fa64_\@: 309 orr x0, x0, SMCR_ELx_FA64_MASK 310 .Lskip_sme_fa64_\@: 311 312 // ZT0 available? 313 mrs_s x1, SYS_ID_AA64SMFR0_EL1 314 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2 315 .Linit_sme_zt0_\@: 316 orr x0, x0, SMCR_ELx_EZT0_MASK 317 .Lskip_sme_zt0_\@: 318 319 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector 320 msr_s SYS_SMCR_EL2, x0 // length for EL1. 321 322 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported? 323 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1 324 cbz x1, .Lskip_sme_\@ 325 326 msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal 327 .Lskip_sme_\@: 328 .endm 329 330 #endif /* __ARM_KVM_INIT_H__ */ 331