1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM_KVM_INIT_H__ 8 #define __ARM_KVM_INIT_H__ 9 10 #ifndef __ASSEMBLY__ 11 #error Assembly-only header 12 #endif 13 14 #include <asm/kvm_arm.h> 15 #include <asm/ptrace.h> 16 #include <asm/sysreg.h> 17 #include <linux/irqchip/arm-gic-v3.h> 18 19 .macro __init_el2_sctlr 20 mov_q x0, INIT_SCTLR_EL2_MMU_OFF 21 msr sctlr_el2, x0 22 isb 23 .endm 24 25 /* 26 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 27 * This is not necessary for VHE, since the host kernel runs in EL2, 28 * and EL0 accesses are configured in the later stage of boot process. 29 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 30 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 31 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 32 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 33 * EL2. 34 */ 35 .macro __init_el2_timers 36 mrs x0, cnthctl_el2 37 orr x0, x0, #3 // Enable EL1 physical timers 38 msr cnthctl_el2, x0 39 msr cntvoff_el2, xzr // Clear virtual offset 40 .endm 41 42 .macro __init_el2_debug 43 mrs x1, id_aa64dfr0_el1 44 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4 45 cmp x0, #1 46 b.lt .Lskip_pmu_\@ // Skip if no PMU present 47 mrs x0, pmcr_el0 // Disable debug access traps 48 ubfx x0, x0, #11, #5 // to EL2 and allow access to 49 .Lskip_pmu_\@: 50 csel x2, xzr, x0, lt // all PMU counters from EL1 51 52 /* Statistical profiling */ 53 ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4 54 cbz x0, .Lskip_spe_\@ // Skip if SPE not present 55 56 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, 57 and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT) 58 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical 59 mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ 60 1 << SYS_PMSCR_EL2_PA_SHIFT) 61 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter 62 .Lskip_spe_el2_\@: 63 mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) 64 orr x2, x2, x0 // If we don't have VHE, then 65 // use EL1&0 translation. 66 67 .Lskip_spe_\@: 68 /* Trace buffer */ 69 ubfx x0, x1, #ID_AA64DFR0_TRBE_SHIFT, #4 70 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present 71 72 mrs_s x0, SYS_TRBIDR_EL1 73 and x0, x0, TRBIDR_PROG 74 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2 75 76 mov x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT) 77 orr x2, x2, x0 // allow the EL1&0 translation 78 // to own it. 79 80 .Lskip_trace_\@: 81 msr mdcr_el2, x2 // Configure debug traps 82 .endm 83 84 /* LORegions */ 85 .macro __init_el2_lor 86 mrs x1, id_aa64mmfr1_el1 87 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4 88 cbz x0, .Lskip_lor_\@ 89 msr_s SYS_LORC_EL1, xzr 90 .Lskip_lor_\@: 91 .endm 92 93 /* Stage-2 translation */ 94 .macro __init_el2_stage2 95 msr vttbr_el2, xzr 96 .endm 97 98 /* GICv3 system register access */ 99 .macro __init_el2_gicv3 100 mrs x0, id_aa64pfr0_el1 101 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4 102 cbz x0, .Lskip_gicv3_\@ 103 104 mrs_s x0, SYS_ICC_SRE_EL2 105 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 106 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 107 msr_s SYS_ICC_SRE_EL2, x0 108 isb // Make sure SRE is now set 109 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 110 tbz x0, #0, 1f // and check that it sticks 111 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 112 .Lskip_gicv3_\@: 113 .endm 114 115 .macro __init_el2_hstr 116 msr hstr_el2, xzr // Disable CP15 traps to EL2 117 .endm 118 119 /* Virtual CPU ID registers */ 120 .macro __init_el2_nvhe_idregs 121 mrs x0, midr_el1 122 mrs x1, mpidr_el1 123 msr vpidr_el2, x0 124 msr vmpidr_el2, x1 125 .endm 126 127 /* Coprocessor traps */ 128 .macro __init_el2_nvhe_cptr 129 mov x0, #0x33ff 130 msr cptr_el2, x0 // Disable copro. traps to EL2 131 .endm 132 133 /* SVE register access */ 134 .macro __init_el2_nvhe_sve 135 mrs x1, id_aa64pfr0_el1 136 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4 137 cbz x1, .Lskip_sve_\@ 138 139 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps 140 msr cptr_el2, x0 // Disable copro. traps to EL2 141 isb 142 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 143 msr_s SYS_ZCR_EL2, x1 // length for EL1. 144 .Lskip_sve_\@: 145 .endm 146 147 /* Disable any fine grained traps */ 148 .macro __init_el2_fgt 149 mrs x1, id_aa64mmfr0_el1 150 ubfx x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4 151 cbz x1, .Lskip_fgt_\@ 152 153 msr_s SYS_HDFGRTR_EL2, xzr 154 msr_s SYS_HDFGWTR_EL2, xzr 155 msr_s SYS_HFGRTR_EL2, xzr 156 msr_s SYS_HFGWTR_EL2, xzr 157 msr_s SYS_HFGITR_EL2, xzr 158 159 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU 160 ubfx x1, x1, #ID_AA64PFR0_AMU_SHIFT, #4 161 cbz x1, .Lskip_fgt_\@ 162 163 msr_s SYS_HAFGRTR_EL2, xzr 164 .Lskip_fgt_\@: 165 .endm 166 167 .macro __init_el2_nvhe_prepare_eret 168 mov x0, #INIT_PSTATE_EL1 169 msr spsr_el2, x0 170 .endm 171 172 /** 173 * Initialize EL2 registers to sane values. This should be called early on all 174 * cores that were booted in EL2. Note that everything gets initialised as 175 * if VHE was not evailable. The kernel context will be upgraded to VHE 176 * if possible later on in the boot process 177 * 178 * Regs: x0, x1 and x2 are clobbered. 179 */ 180 .macro init_el2_state 181 __init_el2_sctlr 182 __init_el2_timers 183 __init_el2_debug 184 __init_el2_lor 185 __init_el2_stage2 186 __init_el2_gicv3 187 __init_el2_hstr 188 __init_el2_nvhe_idregs 189 __init_el2_nvhe_cptr 190 __init_el2_nvhe_sve 191 __init_el2_fgt 192 __init_el2_nvhe_prepare_eret 193 .endm 194 195 #endif /* __ARM_KVM_INIT_H__ */ 196