1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM_KVM_INIT_H__ 8 #define __ARM_KVM_INIT_H__ 9 10 #ifndef __ASSEMBLY__ 11 #error Assembly-only header 12 #endif 13 14 #include <asm/kvm_arm.h> 15 #include <asm/ptrace.h> 16 #include <asm/sysreg.h> 17 #include <linux/irqchip/arm-gic-v3.h> 18 19 .macro __init_el2_sctlr 20 mov_q x0, INIT_SCTLR_EL2_MMU_OFF 21 msr sctlr_el2, x0 22 isb 23 .endm 24 25 /* 26 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 27 * This is not necessary for VHE, since the host kernel runs in EL2, 28 * and EL0 accesses are configured in the later stage of boot process. 29 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 30 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 31 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 32 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 33 * EL2. 34 */ 35 .macro __init_el2_timers mode 36 .ifeqs "\mode", "nvhe" 37 mrs x0, cnthctl_el2 38 orr x0, x0, #3 // Enable EL1 physical timers 39 msr cnthctl_el2, x0 40 .endif 41 msr cntvoff_el2, xzr // Clear virtual offset 42 .endm 43 44 .macro __init_el2_debug mode 45 mrs x1, id_aa64dfr0_el1 46 sbfx x0, x1, #ID_AA64DFR0_PMUVER_SHIFT, #4 47 cmp x0, #1 48 b.lt 1f // Skip if no PMU present 49 mrs x0, pmcr_el0 // Disable debug access traps 50 ubfx x0, x0, #11, #5 // to EL2 and allow access to 51 1: 52 csel x2, xzr, x0, lt // all PMU counters from EL1 53 54 /* Statistical profiling */ 55 ubfx x0, x1, #ID_AA64DFR0_PMSVER_SHIFT, #4 56 cbz x0, 3f // Skip if SPE not present 57 58 .ifeqs "\mode", "nvhe" 59 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, 60 and x0, x0, #(1 << SYS_PMBIDR_EL1_P_SHIFT) 61 cbnz x0, 2f // then permit sampling of physical 62 mov x0, #(1 << SYS_PMSCR_EL2_PCT_SHIFT | \ 63 1 << SYS_PMSCR_EL2_PA_SHIFT) 64 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter 65 2: 66 mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) 67 orr x2, x2, x0 // If we don't have VHE, then 68 // use EL1&0 translation. 69 .else 70 orr x2, x2, #MDCR_EL2_TPMS // For VHE, use EL2 translation 71 // and disable access from EL1 72 .endif 73 74 3: 75 msr mdcr_el2, x2 // Configure debug traps 76 .endm 77 78 /* LORegions */ 79 .macro __init_el2_lor 80 mrs x1, id_aa64mmfr1_el1 81 ubfx x0, x1, #ID_AA64MMFR1_LOR_SHIFT, 4 82 cbz x0, 1f 83 msr_s SYS_LORC_EL1, xzr 84 1: 85 .endm 86 87 /* Stage-2 translation */ 88 .macro __init_el2_stage2 89 msr vttbr_el2, xzr 90 .endm 91 92 /* GICv3 system register access */ 93 .macro __init_el2_gicv3 94 mrs x0, id_aa64pfr0_el1 95 ubfx x0, x0, #ID_AA64PFR0_GIC_SHIFT, #4 96 cbz x0, 1f 97 98 mrs_s x0, SYS_ICC_SRE_EL2 99 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 100 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 101 msr_s SYS_ICC_SRE_EL2, x0 102 isb // Make sure SRE is now set 103 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 104 tbz x0, #0, 1f // and check that it sticks 105 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICC_HCR_EL2 to defaults 106 1: 107 .endm 108 109 .macro __init_el2_hstr 110 msr hstr_el2, xzr // Disable CP15 traps to EL2 111 .endm 112 113 /* Virtual CPU ID registers */ 114 .macro __init_el2_nvhe_idregs 115 mrs x0, midr_el1 116 mrs x1, mpidr_el1 117 msr vpidr_el2, x0 118 msr vmpidr_el2, x1 119 .endm 120 121 /* Coprocessor traps */ 122 .macro __init_el2_nvhe_cptr 123 mov x0, #0x33ff 124 msr cptr_el2, x0 // Disable copro. traps to EL2 125 .endm 126 127 /* SVE register access */ 128 .macro __init_el2_nvhe_sve 129 mrs x1, id_aa64pfr0_el1 130 ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4 131 cbz x1, 1f 132 133 bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps 134 msr cptr_el2, x0 // Disable copro. traps to EL2 135 isb 136 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 137 msr_s SYS_ZCR_EL2, x1 // length for EL1. 138 1: 139 .endm 140 141 .macro __init_el2_nvhe_prepare_eret 142 mov x0, #INIT_PSTATE_EL1 143 msr spsr_el2, x0 144 .endm 145 146 /** 147 * Initialize EL2 registers to sane values. This should be called early on all 148 * cores that were booted in EL2. 149 * 150 * Regs: x0, x1 and x2 are clobbered. 151 */ 152 .macro init_el2_state mode 153 .ifnes "\mode", "vhe" 154 .ifnes "\mode", "nvhe" 155 .error "Invalid 'mode' argument" 156 .endif 157 .endif 158 159 __init_el2_sctlr 160 __init_el2_timers \mode 161 __init_el2_debug \mode 162 __init_el2_lor 163 __init_el2_stage2 164 __init_el2_gicv3 165 __init_el2_hstr 166 167 /* 168 * When VHE is not in use, early init of EL2 needs to be done here. 169 * When VHE _is_ in use, EL1 will not be used in the host and 170 * requires no configuration, and all non-hyp-specific EL2 setup 171 * will be done via the _EL1 system register aliases in __cpu_setup. 172 */ 173 .ifeqs "\mode", "nvhe" 174 __init_el2_nvhe_idregs 175 __init_el2_nvhe_cptr 176 __init_el2_nvhe_sve 177 __init_el2_nvhe_prepare_eret 178 .endif 179 .endm 180 181 #endif /* __ARM_KVM_INIT_H__ */ 182