1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM_KVM_INIT_H__ 8 #define __ARM_KVM_INIT_H__ 9 10 #ifndef __ASSEMBLY__ 11 #error Assembly-only header 12 #endif 13 14 #include <asm/kvm_arm.h> 15 #include <asm/ptrace.h> 16 #include <asm/sysreg.h> 17 #include <linux/irqchip/arm-gic-v3.h> 18 19 .macro __init_el2_sctlr 20 mov_q x0, INIT_SCTLR_EL2_MMU_OFF 21 msr sctlr_el2, x0 22 isb 23 .endm 24 25 .macro __init_el2_hcrx 26 mrs x0, id_aa64mmfr1_el1 27 ubfx x0, x0, #ID_AA64MMFR1_EL1_HCX_SHIFT, #4 28 cbz x0, .Lskip_hcrx_\@ 29 mov_q x0, HCRX_HOST_FLAGS 30 msr_s SYS_HCRX_EL2, x0 31 .Lskip_hcrx_\@: 32 .endm 33 34 /* 35 * Allow Non-secure EL1 and EL0 to access physical timer and counter. 36 * This is not necessary for VHE, since the host kernel runs in EL2, 37 * and EL0 accesses are configured in the later stage of boot process. 38 * Note that when HCR_EL2.E2H == 1, CNTHCTL_EL2 has the same bit layout 39 * as CNTKCTL_EL1, and CNTKCTL_EL1 accessing instructions are redefined 40 * to access CNTHCTL_EL2. This allows the kernel designed to run at EL1 41 * to transparently mess with the EL0 bits via CNTKCTL_EL1 access in 42 * EL2. 43 */ 44 .macro __init_el2_timers 45 mov x0, #3 // Enable EL1 physical timers 46 msr cnthctl_el2, x0 47 msr cntvoff_el2, xzr // Clear virtual offset 48 .endm 49 50 .macro __init_el2_debug 51 mrs x1, id_aa64dfr0_el1 52 sbfx x0, x1, #ID_AA64DFR0_EL1_PMUVer_SHIFT, #4 53 cmp x0, #1 54 b.lt .Lskip_pmu_\@ // Skip if no PMU present 55 mrs x0, pmcr_el0 // Disable debug access traps 56 ubfx x0, x0, #11, #5 // to EL2 and allow access to 57 .Lskip_pmu_\@: 58 csel x2, xzr, x0, lt // all PMU counters from EL1 59 60 /* Statistical profiling */ 61 ubfx x0, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 62 cbz x0, .Lskip_spe_\@ // Skip if SPE not present 63 64 mrs_s x0, SYS_PMBIDR_EL1 // If SPE available at EL2, 65 and x0, x0, #(1 << PMBIDR_EL1_P_SHIFT) 66 cbnz x0, .Lskip_spe_el2_\@ // then permit sampling of physical 67 mov x0, #(1 << PMSCR_EL2_PCT_SHIFT | \ 68 1 << PMSCR_EL2_PA_SHIFT) 69 msr_s SYS_PMSCR_EL2, x0 // addresses and physical counter 70 .Lskip_spe_el2_\@: 71 mov x0, #(MDCR_EL2_E2PB_MASK << MDCR_EL2_E2PB_SHIFT) 72 orr x2, x2, x0 // If we don't have VHE, then 73 // use EL1&0 translation. 74 75 .Lskip_spe_\@: 76 /* Trace buffer */ 77 ubfx x0, x1, #ID_AA64DFR0_EL1_TraceBuffer_SHIFT, #4 78 cbz x0, .Lskip_trace_\@ // Skip if TraceBuffer is not present 79 80 mrs_s x0, SYS_TRBIDR_EL1 81 and x0, x0, TRBIDR_EL1_P 82 cbnz x0, .Lskip_trace_\@ // If TRBE is available at EL2 83 84 mov x0, #(MDCR_EL2_E2TB_MASK << MDCR_EL2_E2TB_SHIFT) 85 orr x2, x2, x0 // allow the EL1&0 translation 86 // to own it. 87 88 .Lskip_trace_\@: 89 msr mdcr_el2, x2 // Configure debug traps 90 .endm 91 92 /* LORegions */ 93 .macro __init_el2_lor 94 mrs x1, id_aa64mmfr1_el1 95 ubfx x0, x1, #ID_AA64MMFR1_EL1_LO_SHIFT, 4 96 cbz x0, .Lskip_lor_\@ 97 msr_s SYS_LORC_EL1, xzr 98 .Lskip_lor_\@: 99 .endm 100 101 /* Stage-2 translation */ 102 .macro __init_el2_stage2 103 msr vttbr_el2, xzr 104 .endm 105 106 /* GICv3 system register access */ 107 .macro __init_el2_gicv3 108 mrs x0, id_aa64pfr0_el1 109 ubfx x0, x0, #ID_AA64PFR0_EL1_GIC_SHIFT, #4 110 cbz x0, .Lskip_gicv3_\@ 111 112 mrs_s x0, SYS_ICC_SRE_EL2 113 orr x0, x0, #ICC_SRE_EL2_SRE // Set ICC_SRE_EL2.SRE==1 114 orr x0, x0, #ICC_SRE_EL2_ENABLE // Set ICC_SRE_EL2.Enable==1 115 msr_s SYS_ICC_SRE_EL2, x0 116 isb // Make sure SRE is now set 117 mrs_s x0, SYS_ICC_SRE_EL2 // Read SRE back, 118 tbz x0, #0, .Lskip_gicv3_\@ // and check that it sticks 119 msr_s SYS_ICH_HCR_EL2, xzr // Reset ICH_HCR_EL2 to defaults 120 .Lskip_gicv3_\@: 121 .endm 122 123 .macro __init_el2_hstr 124 msr hstr_el2, xzr // Disable CP15 traps to EL2 125 .endm 126 127 /* Virtual CPU ID registers */ 128 .macro __init_el2_nvhe_idregs 129 mrs x0, midr_el1 130 mrs x1, mpidr_el1 131 msr vpidr_el2, x0 132 msr vmpidr_el2, x1 133 .endm 134 135 /* Coprocessor traps */ 136 .macro __init_el2_nvhe_cptr 137 mov x0, #0x33ff 138 msr cptr_el2, x0 // Disable copro. traps to EL2 139 .endm 140 141 /* Disable any fine grained traps */ 142 .macro __init_el2_fgt 143 mrs x1, id_aa64mmfr0_el1 144 ubfx x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4 145 cbz x1, .Lskip_fgt_\@ 146 147 mov x0, xzr 148 mrs x1, id_aa64dfr0_el1 149 ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 150 cmp x1, #3 151 b.lt .Lset_debug_fgt_\@ 152 /* Disable PMSNEVFR_EL1 read and write traps */ 153 orr x0, x0, #(1 << 62) 154 155 .Lset_debug_fgt_\@: 156 msr_s SYS_HDFGRTR_EL2, x0 157 msr_s SYS_HDFGWTR_EL2, x0 158 159 mov x0, xzr 160 mrs x1, id_aa64pfr1_el1 161 ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4 162 cbz x1, .Lset_pie_fgt_\@ 163 164 /* Disable nVHE traps of TPIDR2 and SMPRI */ 165 orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK 166 orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK 167 168 .Lset_pie_fgt_\@: 169 mrs_s x1, SYS_ID_AA64MMFR3_EL1 170 ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4 171 cbz x1, .Lset_fgt_\@ 172 173 /* Disable trapping of PIR_EL1 / PIRE0_EL1 */ 174 orr x0, x0, #HFGxTR_EL2_nPIR_EL1 175 orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1 176 177 .Lset_fgt_\@: 178 msr_s SYS_HFGRTR_EL2, x0 179 msr_s SYS_HFGWTR_EL2, x0 180 msr_s SYS_HFGITR_EL2, xzr 181 182 mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU 183 ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4 184 cbz x1, .Lskip_fgt_\@ 185 186 msr_s SYS_HAFGRTR_EL2, xzr 187 .Lskip_fgt_\@: 188 .endm 189 190 .macro __init_el2_nvhe_prepare_eret 191 mov x0, #INIT_PSTATE_EL1 192 msr spsr_el2, x0 193 .endm 194 195 /** 196 * Initialize EL2 registers to sane values. This should be called early on all 197 * cores that were booted in EL2. Note that everything gets initialised as 198 * if VHE was not available. The kernel context will be upgraded to VHE 199 * if possible later on in the boot process 200 * 201 * Regs: x0, x1 and x2 are clobbered. 202 */ 203 .macro init_el2_state 204 __init_el2_sctlr 205 __init_el2_hcrx 206 __init_el2_timers 207 __init_el2_debug 208 __init_el2_lor 209 __init_el2_stage2 210 __init_el2_gicv3 211 __init_el2_hstr 212 __init_el2_nvhe_idregs 213 __init_el2_nvhe_cptr 214 __init_el2_fgt 215 __init_el2_nvhe_prepare_eret 216 .endm 217 218 #ifndef __KVM_NVHE_HYPERVISOR__ 219 // This will clobber tmp1 and tmp2, and expect tmp1 to contain 220 // the id register value as read from the HW 221 .macro __check_override idreg, fld, width, pass, fail, tmp1, tmp2 222 ubfx \tmp1, \tmp1, #\fld, #\width 223 cbz \tmp1, \fail 224 225 adr_l \tmp1, \idreg\()_override 226 ldr \tmp2, [\tmp1, FTR_OVR_VAL_OFFSET] 227 ldr \tmp1, [\tmp1, FTR_OVR_MASK_OFFSET] 228 ubfx \tmp2, \tmp2, #\fld, #\width 229 ubfx \tmp1, \tmp1, #\fld, #\width 230 cmp \tmp1, xzr 231 and \tmp2, \tmp2, \tmp1 232 csinv \tmp2, \tmp2, xzr, ne 233 cbnz \tmp2, \pass 234 b \fail 235 .endm 236 237 // This will clobber tmp1 and tmp2 238 .macro check_override idreg, fld, pass, fail, tmp1, tmp2 239 mrs \tmp1, \idreg\()_el1 240 __check_override \idreg \fld 4 \pass \fail \tmp1 \tmp2 241 .endm 242 #else 243 // This will clobber tmp 244 .macro __check_override idreg, fld, width, pass, fail, tmp, ignore 245 ldr_l \tmp, \idreg\()_el1_sys_val 246 ubfx \tmp, \tmp, #\fld, #\width 247 cbnz \tmp, \pass 248 b \fail 249 .endm 250 251 .macro check_override idreg, fld, pass, fail, tmp, ignore 252 __check_override \idreg \fld 4 \pass \fail \tmp \ignore 253 .endm 254 #endif 255 256 .macro finalise_el2_state 257 check_override id_aa64pfr0, ID_AA64PFR0_EL1_SVE_SHIFT, .Linit_sve_\@, .Lskip_sve_\@, x1, x2 258 259 .Linit_sve_\@: /* SVE register access */ 260 mrs x0, cptr_el2 // Disable SVE traps 261 bic x0, x0, #CPTR_EL2_TZ 262 msr cptr_el2, x0 263 isb 264 mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector 265 msr_s SYS_ZCR_EL2, x1 // length for EL1. 266 267 .Lskip_sve_\@: 268 check_override id_aa64pfr1, ID_AA64PFR1_EL1_SME_SHIFT, .Linit_sme_\@, .Lskip_sme_\@, x1, x2 269 270 .Linit_sme_\@: /* SME register access and priority mapping */ 271 mrs x0, cptr_el2 // Disable SME traps 272 bic x0, x0, #CPTR_EL2_TSM 273 msr cptr_el2, x0 274 isb 275 276 mrs x1, sctlr_el2 277 orr x1, x1, #SCTLR_ELx_ENTP2 // Disable TPIDR2 traps 278 msr sctlr_el2, x1 279 isb 280 281 mov x0, #0 // SMCR controls 282 283 // Full FP in SM? 284 mrs_s x1, SYS_ID_AA64SMFR0_EL1 285 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_FA64_SHIFT, 1, .Linit_sme_fa64_\@, .Lskip_sme_fa64_\@, x1, x2 286 287 .Linit_sme_fa64_\@: 288 orr x0, x0, SMCR_ELx_FA64_MASK 289 .Lskip_sme_fa64_\@: 290 291 // ZT0 available? 292 mrs_s x1, SYS_ID_AA64SMFR0_EL1 293 __check_override id_aa64smfr0, ID_AA64SMFR0_EL1_SMEver_SHIFT, 4, .Linit_sme_zt0_\@, .Lskip_sme_zt0_\@, x1, x2 294 .Linit_sme_zt0_\@: 295 orr x0, x0, SMCR_ELx_EZT0_MASK 296 .Lskip_sme_zt0_\@: 297 298 orr x0, x0, #SMCR_ELx_LEN_MASK // Enable full SME vector 299 msr_s SYS_SMCR_EL2, x0 // length for EL1. 300 301 mrs_s x1, SYS_SMIDR_EL1 // Priority mapping supported? 302 ubfx x1, x1, #SMIDR_EL1_SMPS_SHIFT, #1 303 cbz x1, .Lskip_sme_\@ 304 305 msr_s SYS_SMPRIMAP_EL2, xzr // Make all priorities equal 306 .Lskip_sme_\@: 307 .endm 308 309 #endif /* __ARM_KVM_INIT_H__ */ 310