1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_CPUTYPE_H 17 #define __ASM_CPUTYPE_H 18 19 #define INVALID_HWID ULONG_MAX 20 21 #define MPIDR_UP_BITMASK (0x1 << 30) 22 #define MPIDR_MT_BITMASK (0x1 << 24) 23 #define MPIDR_HWID_BITMASK UL(0xff00ffffff) 24 25 #define MPIDR_LEVEL_BITS_SHIFT 3 26 #define MPIDR_LEVEL_BITS (1 << MPIDR_LEVEL_BITS_SHIFT) 27 #define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1) 28 29 #define MPIDR_LEVEL_SHIFT(level) \ 30 (((1 << level) >> 1) << MPIDR_LEVEL_BITS_SHIFT) 31 32 #define MPIDR_AFFINITY_LEVEL(mpidr, level) \ 33 ((mpidr >> MPIDR_LEVEL_SHIFT(level)) & MPIDR_LEVEL_MASK) 34 35 #define MIDR_REVISION_MASK 0xf 36 #define MIDR_REVISION(midr) ((midr) & MIDR_REVISION_MASK) 37 #define MIDR_PARTNUM_SHIFT 4 38 #define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT) 39 #define MIDR_PARTNUM(midr) \ 40 (((midr) & MIDR_PARTNUM_MASK) >> MIDR_PARTNUM_SHIFT) 41 #define MIDR_ARCHITECTURE_SHIFT 16 42 #define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT) 43 #define MIDR_ARCHITECTURE(midr) \ 44 (((midr) & MIDR_ARCHITECTURE_MASK) >> MIDR_ARCHITECTURE_SHIFT) 45 #define MIDR_VARIANT_SHIFT 20 46 #define MIDR_VARIANT_MASK (0xf << MIDR_VARIANT_SHIFT) 47 #define MIDR_VARIANT(midr) \ 48 (((midr) & MIDR_VARIANT_MASK) >> MIDR_VARIANT_SHIFT) 49 #define MIDR_IMPLEMENTOR_SHIFT 24 50 #define MIDR_IMPLEMENTOR_MASK (0xff << MIDR_IMPLEMENTOR_SHIFT) 51 #define MIDR_IMPLEMENTOR(midr) \ 52 (((midr) & MIDR_IMPLEMENTOR_MASK) >> MIDR_IMPLEMENTOR_SHIFT) 53 54 #define MIDR_CPU_MODEL(imp, partnum) \ 55 (((imp) << MIDR_IMPLEMENTOR_SHIFT) | \ 56 (0xf << MIDR_ARCHITECTURE_SHIFT) | \ 57 ((partnum) << MIDR_PARTNUM_SHIFT)) 58 59 #define MIDR_CPU_VAR_REV(var, rev) \ 60 (((var) << MIDR_VARIANT_SHIFT) | (rev)) 61 62 #define MIDR_CPU_MODEL_MASK (MIDR_IMPLEMENTOR_MASK | MIDR_PARTNUM_MASK | \ 63 MIDR_ARCHITECTURE_MASK) 64 65 #define MIDR_IS_CPU_MODEL_RANGE(midr, model, rv_min, rv_max) \ 66 ({ \ 67 u32 _model = (midr) & MIDR_CPU_MODEL_MASK; \ 68 u32 rv = (midr) & (MIDR_REVISION_MASK | MIDR_VARIANT_MASK); \ 69 \ 70 _model == (model) && rv >= (rv_min) && rv <= (rv_max); \ 71 }) 72 73 #define ARM_CPU_IMP_ARM 0x41 74 #define ARM_CPU_IMP_APM 0x50 75 #define ARM_CPU_IMP_CAVIUM 0x43 76 #define ARM_CPU_IMP_BRCM 0x42 77 #define ARM_CPU_IMP_QCOM 0x51 78 #define ARM_CPU_IMP_NVIDIA 0x4E 79 80 #define ARM_CPU_PART_AEM_V8 0xD0F 81 #define ARM_CPU_PART_FOUNDATION 0xD00 82 #define ARM_CPU_PART_CORTEX_A57 0xD07 83 #define ARM_CPU_PART_CORTEX_A72 0xD08 84 #define ARM_CPU_PART_CORTEX_A53 0xD03 85 #define ARM_CPU_PART_CORTEX_A73 0xD09 86 #define ARM_CPU_PART_CORTEX_A75 0xD0A 87 #define ARM_CPU_PART_CORTEX_A35 0xD04 88 #define ARM_CPU_PART_CORTEX_A55 0xD05 89 90 #define APM_CPU_PART_POTENZA 0x000 91 92 #define CAVIUM_CPU_PART_THUNDERX 0x0A1 93 #define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2 94 #define CAVIUM_CPU_PART_THUNDERX_83XX 0x0A3 95 #define CAVIUM_CPU_PART_THUNDERX2 0x0AF 96 97 #define BRCM_CPU_PART_VULCAN 0x516 98 99 #define QCOM_CPU_PART_FALKOR_V1 0x800 100 #define QCOM_CPU_PART_FALKOR 0xC00 101 #define QCOM_CPU_PART_KRYO 0x200 102 103 #define NVIDIA_CPU_PART_DENVER 0x003 104 #define NVIDIA_CPU_PART_CARMEL 0x004 105 106 #define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53) 107 #define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57) 108 #define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72) 109 #define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73) 110 #define MIDR_CORTEX_A75 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A75) 111 #define MIDR_CORTEX_A35 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A35) 112 #define MIDR_CORTEX_A55 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A55) 113 #define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX) 114 #define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX) 115 #define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX) 116 #define MIDR_CAVIUM_THUNDERX2 MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX2) 117 #define MIDR_BRCM_VULCAN MIDR_CPU_MODEL(ARM_CPU_IMP_BRCM, BRCM_CPU_PART_VULCAN) 118 #define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1) 119 #define MIDR_QCOM_FALKOR MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR) 120 #define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO) 121 #define MIDR_NVIDIA_DENVER MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_DENVER) 122 #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) 123 124 #ifndef __ASSEMBLY__ 125 126 #include <asm/sysreg.h> 127 128 #define read_cpuid(reg) read_sysreg_s(SYS_ ## reg) 129 130 /* 131 * Represent a range of MIDR values for a given CPU model and a 132 * range of variant/revision values. 133 * 134 * @model - CPU model as defined by MIDR_CPU_MODEL 135 * @rv_min - Minimum value for the revision/variant as defined by 136 * MIDR_CPU_VAR_REV 137 * @rv_max - Maximum value for the variant/revision for the range. 138 */ 139 struct midr_range { 140 u32 model; 141 u32 rv_min; 142 u32 rv_max; 143 }; 144 145 #define MIDR_RANGE(m, v_min, r_min, v_max, r_max) \ 146 { \ 147 .model = m, \ 148 .rv_min = MIDR_CPU_VAR_REV(v_min, r_min), \ 149 .rv_max = MIDR_CPU_VAR_REV(v_max, r_max), \ 150 } 151 152 #define MIDR_ALL_VERSIONS(m) MIDR_RANGE(m, 0, 0, 0xf, 0xf) 153 154 static inline bool is_midr_in_range(u32 midr, struct midr_range const *range) 155 { 156 return MIDR_IS_CPU_MODEL_RANGE(midr, range->model, 157 range->rv_min, range->rv_max); 158 } 159 160 static inline bool 161 is_midr_in_range_list(u32 midr, struct midr_range const *ranges) 162 { 163 while (ranges->model) 164 if (is_midr_in_range(midr, ranges++)) 165 return true; 166 return false; 167 } 168 169 /* 170 * The CPU ID never changes at run time, so we might as well tell the 171 * compiler that it's constant. Use this function to read the CPU ID 172 * rather than directly reading processor_id or read_cpuid() directly. 173 */ 174 static inline u32 __attribute_const__ read_cpuid_id(void) 175 { 176 return read_cpuid(MIDR_EL1); 177 } 178 179 static inline u64 __attribute_const__ read_cpuid_mpidr(void) 180 { 181 return read_cpuid(MPIDR_EL1); 182 } 183 184 static inline unsigned int __attribute_const__ read_cpuid_implementor(void) 185 { 186 return MIDR_IMPLEMENTOR(read_cpuid_id()); 187 } 188 189 static inline unsigned int __attribute_const__ read_cpuid_part_number(void) 190 { 191 return MIDR_PARTNUM(read_cpuid_id()); 192 } 193 194 static inline u32 __attribute_const__ read_cpuid_cachetype(void) 195 { 196 return read_cpuid(CTR_EL0); 197 } 198 #endif /* __ASSEMBLY__ */ 199 200 #endif 201