1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
4  */
5 
6 #ifndef __ASM_CPUFEATURE_H
7 #define __ASM_CPUFEATURE_H
8 
9 #include <asm/cpucaps.h>
10 #include <asm/cputype.h>
11 #include <asm/hwcap.h>
12 #include <asm/sysreg.h>
13 
14 #define MAX_CPU_FEATURES	64
15 #define cpu_feature(x)		KERNEL_HWCAP_ ## x
16 
17 #ifndef __ASSEMBLY__
18 
19 #include <linux/bug.h>
20 #include <linux/jump_label.h>
21 #include <linux/kernel.h>
22 
23 /*
24  * CPU feature register tracking
25  *
26  * The safe value of a CPUID feature field is dependent on the implications
27  * of the values assigned to it by the architecture. Based on the relationship
28  * between the values, the features are classified into 3 types - LOWER_SAFE,
29  * HIGHER_SAFE and EXACT.
30  *
31  * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
32  * for HIGHER_SAFE. It is expected that all CPUs have the same value for
33  * a field when EXACT is specified, failing which, the safe value specified
34  * in the table is chosen.
35  */
36 
37 enum ftr_type {
38 	FTR_EXACT,			/* Use a predefined safe value */
39 	FTR_LOWER_SAFE,			/* Smaller value is safe */
40 	FTR_HIGHER_SAFE,		/* Bigger value is safe */
41 	FTR_HIGHER_OR_ZERO_SAFE,	/* Bigger value is safe, but 0 is biggest */
42 };
43 
44 #define FTR_STRICT	true	/* SANITY check strict matching required */
45 #define FTR_NONSTRICT	false	/* SANITY check ignored */
46 
47 #define FTR_SIGNED	true	/* Value should be treated as signed */
48 #define FTR_UNSIGNED	false	/* Value should be treated as unsigned */
49 
50 #define FTR_VISIBLE	true	/* Feature visible to the user space */
51 #define FTR_HIDDEN	false	/* Feature is hidden from the user */
52 
53 #define FTR_VISIBLE_IF_IS_ENABLED(config)		\
54 	(IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
55 
56 struct arm64_ftr_bits {
57 	bool		sign;	/* Value is signed ? */
58 	bool		visible;
59 	bool		strict;	/* CPU Sanity check: strict matching required ? */
60 	enum ftr_type	type;
61 	u8		shift;
62 	u8		width;
63 	s64		safe_val; /* safe value for FTR_EXACT features */
64 };
65 
66 /*
67  * Describe the early feature override to the core override code:
68  *
69  * @val			Values that are to be merged into the final
70  *			sanitised value of the register. Only the bitfields
71  *			set to 1 in @mask are valid
72  * @mask		Mask of the features that are overridden by @val
73  *
74  * A @mask field set to full-1 indicates that the corresponding field
75  * in @val is a valid override.
76  *
77  * A @mask field set to full-0 with the corresponding @val field set
78  * to full-0 denotes that this field has no override
79  *
80  * A @mask field set to full-0 with the corresponding @val field set
81  * to full-1 denotes thath this field has an invalid override.
82  */
83 struct arm64_ftr_override {
84 	u64		val;
85 	u64		mask;
86 };
87 
88 /*
89  * @arm64_ftr_reg - Feature register
90  * @strict_mask		Bits which should match across all CPUs for sanity.
91  * @sys_val		Safe value across the CPUs (system view)
92  */
93 struct arm64_ftr_reg {
94 	const char			*name;
95 	u64				strict_mask;
96 	u64				user_mask;
97 	u64				sys_val;
98 	u64				user_val;
99 	struct arm64_ftr_override	*override;
100 	const struct arm64_ftr_bits	*ftr_bits;
101 };
102 
103 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
104 
105 /*
106  * CPU capabilities:
107  *
108  * We use arm64_cpu_capabilities to represent system features, errata work
109  * arounds (both used internally by kernel and tracked in cpu_hwcaps) and
110  * ELF HWCAPs (which are exposed to user).
111  *
112  * To support systems with heterogeneous CPUs, we need to make sure that we
113  * detect the capabilities correctly on the system and take appropriate
114  * measures to ensure there are no incompatibilities.
115  *
116  * This comment tries to explain how we treat the capabilities.
117  * Each capability has the following list of attributes :
118  *
119  * 1) Scope of Detection : The system detects a given capability by
120  *    performing some checks at runtime. This could be, e.g, checking the
121  *    value of a field in CPU ID feature register or checking the cpu
122  *    model. The capability provides a call back ( @matches() ) to
123  *    perform the check. Scope defines how the checks should be performed.
124  *    There are three cases:
125  *
126  *     a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
127  *        matches. This implies, we have to run the check on all the
128  *        booting CPUs, until the system decides that state of the
129  *        capability is finalised. (See section 2 below)
130  *		Or
131  *     b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
132  *        matches. This implies, we run the check only once, when the
133  *        system decides to finalise the state of the capability. If the
134  *        capability relies on a field in one of the CPU ID feature
135  *        registers, we use the sanitised value of the register from the
136  *        CPU feature infrastructure to make the decision.
137  *		Or
138  *     c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
139  *        feature. This category is for features that are "finalised"
140  *        (or used) by the kernel very early even before the SMP cpus
141  *        are brought up.
142  *
143  *    The process of detection is usually denoted by "update" capability
144  *    state in the code.
145  *
146  * 2) Finalise the state : The kernel should finalise the state of a
147  *    capability at some point during its execution and take necessary
148  *    actions if any. Usually, this is done, after all the boot-time
149  *    enabled CPUs are brought up by the kernel, so that it can make
150  *    better decision based on the available set of CPUs. However, there
151  *    are some special cases, where the action is taken during the early
152  *    boot by the primary boot CPU. (e.g, running the kernel at EL2 with
153  *    Virtualisation Host Extensions). The kernel usually disallows any
154  *    changes to the state of a capability once it finalises the capability
155  *    and takes any action, as it may be impossible to execute the actions
156  *    safely. A CPU brought up after a capability is "finalised" is
157  *    referred to as "Late CPU" w.r.t the capability. e.g, all secondary
158  *    CPUs are treated "late CPUs" for capabilities determined by the boot
159  *    CPU.
160  *
161  *    At the moment there are two passes of finalising the capabilities.
162  *      a) Boot CPU scope capabilities - Finalised by primary boot CPU via
163  *         setup_boot_cpu_capabilities().
164  *      b) Everything except (a) - Run via setup_system_capabilities().
165  *
166  * 3) Verification: When a CPU is brought online (e.g, by user or by the
167  *    kernel), the kernel should make sure that it is safe to use the CPU,
168  *    by verifying that the CPU is compliant with the state of the
169  *    capabilities finalised already. This happens via :
170  *
171  *	secondary_start_kernel()-> check_local_cpu_capabilities()
172  *
173  *    As explained in (2) above, capabilities could be finalised at
174  *    different points in the execution. Each newly booted CPU is verified
175  *    against the capabilities that have been finalised by the time it
176  *    boots.
177  *
178  *	a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
179  *	except for the primary boot CPU.
180  *
181  *	b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
182  *	user after the kernel boot are verified against the capability.
183  *
184  *    If there is a conflict, the kernel takes an action, based on the
185  *    severity (e.g, a CPU could be prevented from booting or cause a
186  *    kernel panic). The CPU is allowed to "affect" the state of the
187  *    capability, if it has not been finalised already. See section 5
188  *    for more details on conflicts.
189  *
190  * 4) Action: As mentioned in (2), the kernel can take an action for each
191  *    detected capability, on all CPUs on the system. Appropriate actions
192  *    include, turning on an architectural feature, modifying the control
193  *    registers (e.g, SCTLR, TCR etc.) or patching the kernel via
194  *    alternatives. The kernel patching is batched and performed at later
195  *    point. The actions are always initiated only after the capability
196  *    is finalised. This is usally denoted by "enabling" the capability.
197  *    The actions are initiated as follows :
198  *	a) Action is triggered on all online CPUs, after the capability is
199  *	finalised, invoked within the stop_machine() context from
200  *	enable_cpu_capabilitie().
201  *
202  *	b) Any late CPU, brought up after (1), the action is triggered via:
203  *
204  *	  check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
205  *
206  * 5) Conflicts: Based on the state of the capability on a late CPU vs.
207  *    the system state, we could have the following combinations :
208  *
209  *		x-----------------------------x
210  *		| Type  | System   | Late CPU |
211  *		|-----------------------------|
212  *		|  a    |   y      |    n     |
213  *		|-----------------------------|
214  *		|  b    |   n      |    y     |
215  *		x-----------------------------x
216  *
217  *     Two separate flag bits are defined to indicate whether each kind of
218  *     conflict can be allowed:
219  *		ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
220  *		ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
221  *
222  *     Case (a) is not permitted for a capability that the system requires
223  *     all CPUs to have in order for the capability to be enabled. This is
224  *     typical for capabilities that represent enhanced functionality.
225  *
226  *     Case (b) is not permitted for a capability that must be enabled
227  *     during boot if any CPU in the system requires it in order to run
228  *     safely. This is typical for erratum work arounds that cannot be
229  *     enabled after the corresponding capability is finalised.
230  *
231  *     In some non-typical cases either both (a) and (b), or neither,
232  *     should be permitted. This can be described by including neither
233  *     or both flags in the capability's type field.
234  *
235  *     In case of a conflict, the CPU is prevented from booting. If the
236  *     ARM64_CPUCAP_PANIC_ON_CONFLICT flag is specified for the capability,
237  *     then a kernel panic is triggered.
238  */
239 
240 
241 /*
242  * Decide how the capability is detected.
243  * On any local CPU vs System wide vs the primary boot CPU
244  */
245 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU		((u16)BIT(0))
246 #define ARM64_CPUCAP_SCOPE_SYSTEM		((u16)BIT(1))
247 /*
248  * The capabilitiy is detected on the Boot CPU and is used by kernel
249  * during early boot. i.e, the capability should be "detected" and
250  * "enabled" as early as possibly on all booting CPUs.
251  */
252 #define ARM64_CPUCAP_SCOPE_BOOT_CPU		((u16)BIT(2))
253 #define ARM64_CPUCAP_SCOPE_MASK			\
254 	(ARM64_CPUCAP_SCOPE_SYSTEM	|	\
255 	 ARM64_CPUCAP_SCOPE_LOCAL_CPU	|	\
256 	 ARM64_CPUCAP_SCOPE_BOOT_CPU)
257 
258 #define SCOPE_SYSTEM				ARM64_CPUCAP_SCOPE_SYSTEM
259 #define SCOPE_LOCAL_CPU				ARM64_CPUCAP_SCOPE_LOCAL_CPU
260 #define SCOPE_BOOT_CPU				ARM64_CPUCAP_SCOPE_BOOT_CPU
261 #define SCOPE_ALL				ARM64_CPUCAP_SCOPE_MASK
262 
263 /*
264  * Is it permitted for a late CPU to have this capability when system
265  * hasn't already enabled it ?
266  */
267 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU	((u16)BIT(4))
268 /* Is it safe for a late CPU to miss this capability when system has it */
269 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU	((u16)BIT(5))
270 /* Panic when a conflict is detected */
271 #define ARM64_CPUCAP_PANIC_ON_CONFLICT		((u16)BIT(6))
272 
273 /*
274  * CPU errata workarounds that need to be enabled at boot time if one or
275  * more CPUs in the system requires it. When one of these capabilities
276  * has been enabled, it is safe to allow any CPU to boot that doesn't
277  * require the workaround. However, it is not safe if a "late" CPU
278  * requires a workaround and the system hasn't enabled it already.
279  */
280 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM		\
281 	(ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
282 /*
283  * CPU feature detected at boot time based on system-wide value of a
284  * feature. It is safe for a late CPU to have this feature even though
285  * the system hasn't enabled it, although the feature will not be used
286  * by Linux in this case. If the system has enabled this feature already,
287  * then every late CPU must have it.
288  */
289 #define ARM64_CPUCAP_SYSTEM_FEATURE	\
290 	(ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
291 /*
292  * CPU feature detected at boot time based on feature of one or more CPUs.
293  * All possible conflicts for a late CPU are ignored.
294  * NOTE: this means that a late CPU with the feature will *not* cause the
295  * capability to be advertised by cpus_have_*cap()!
296  */
297 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE		\
298 	(ARM64_CPUCAP_SCOPE_LOCAL_CPU		|	\
299 	 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU	|	\
300 	 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
301 
302 /*
303  * CPU feature detected at boot time, on one or more CPUs. A late CPU
304  * is not allowed to have the capability when the system doesn't have it.
305  * It is Ok for a late CPU to miss the feature.
306  */
307 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE	\
308 	(ARM64_CPUCAP_SCOPE_LOCAL_CPU		|	\
309 	 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
310 
311 /*
312  * CPU feature used early in the boot based on the boot CPU. All secondary
313  * CPUs must match the state of the capability as detected by the boot CPU. In
314  * case of a conflict, a kernel panic is triggered.
315  */
316 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE		\
317 	(ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT)
318 
319 /*
320  * CPU feature used early in the boot based on the boot CPU. It is safe for a
321  * late CPU to have this feature even though the boot CPU hasn't enabled it,
322  * although the feature will not be used by Linux in this case. If the boot CPU
323  * has enabled this feature already, then every late CPU must have it.
324  */
325 #define ARM64_CPUCAP_BOOT_CPU_FEATURE                  \
326 	(ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
327 
328 struct arm64_cpu_capabilities {
329 	const char *desc;
330 	u16 capability;
331 	u16 type;
332 	bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
333 	/*
334 	 * Take the appropriate actions to configure this capability
335 	 * for this CPU. If the capability is detected by the kernel
336 	 * this will be called on all the CPUs in the system,
337 	 * including the hotplugged CPUs, regardless of whether the
338 	 * capability is available on that specific CPU. This is
339 	 * useful for some capabilities (e.g, working around CPU
340 	 * errata), where all the CPUs must take some action (e.g,
341 	 * changing system control/configuration). Thus, if an action
342 	 * is required only if the CPU has the capability, then the
343 	 * routine must check it before taking any action.
344 	 */
345 	void (*cpu_enable)(const struct arm64_cpu_capabilities *cap);
346 	union {
347 		struct {	/* To be used for erratum handling only */
348 			struct midr_range midr_range;
349 			const struct arm64_midr_revidr {
350 				u32 midr_rv;		/* revision/variant */
351 				u32 revidr_mask;
352 			} * const fixed_revs;
353 		};
354 
355 		const struct midr_range *midr_range_list;
356 		struct {	/* Feature register checking */
357 			u32 sys_reg;
358 			u8 field_pos;
359 			u8 min_field_value;
360 			u8 hwcap_type;
361 			bool sign;
362 			unsigned long hwcap;
363 		};
364 	};
365 
366 	/*
367 	 * An optional list of "matches/cpu_enable" pair for the same
368 	 * "capability" of the same "type" as described by the parent.
369 	 * Only matches(), cpu_enable() and fields relevant to these
370 	 * methods are significant in the list. The cpu_enable is
371 	 * invoked only if the corresponding entry "matches()".
372 	 * However, if a cpu_enable() method is associated
373 	 * with multiple matches(), care should be taken that either
374 	 * the match criteria are mutually exclusive, or that the
375 	 * method is robust against being called multiple times.
376 	 */
377 	const struct arm64_cpu_capabilities *match_list;
378 };
379 
380 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
381 {
382 	return cap->type & ARM64_CPUCAP_SCOPE_MASK;
383 }
384 
385 /*
386  * Generic helper for handling capabilities with multiple (match,enable) pairs
387  * of call backs, sharing the same capability bit.
388  * Iterate over each entry to see if at least one matches.
389  */
390 static inline bool
391 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
392 			       int scope)
393 {
394 	const struct arm64_cpu_capabilities *caps;
395 
396 	for (caps = entry->match_list; caps->matches; caps++)
397 		if (caps->matches(caps, scope))
398 			return true;
399 
400 	return false;
401 }
402 
403 static __always_inline bool is_vhe_hyp_code(void)
404 {
405 	/* Only defined for code run in VHE hyp context */
406 	return __is_defined(__KVM_VHE_HYPERVISOR__);
407 }
408 
409 static __always_inline bool is_nvhe_hyp_code(void)
410 {
411 	/* Only defined for code run in NVHE hyp context */
412 	return __is_defined(__KVM_NVHE_HYPERVISOR__);
413 }
414 
415 static __always_inline bool is_hyp_code(void)
416 {
417 	return is_vhe_hyp_code() || is_nvhe_hyp_code();
418 }
419 
420 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
421 extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
422 extern struct static_key_false arm64_const_caps_ready;
423 
424 /* ARM64 CAPS + alternative_cb */
425 #define ARM64_NPATCHABLE (ARM64_NCAPS + 1)
426 extern DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
427 
428 #define for_each_available_cap(cap)		\
429 	for_each_set_bit(cap, cpu_hwcaps, ARM64_NCAPS)
430 
431 bool this_cpu_has_cap(unsigned int cap);
432 void cpu_set_feature(unsigned int num);
433 bool cpu_have_feature(unsigned int num);
434 unsigned long cpu_get_elf_hwcap(void);
435 unsigned long cpu_get_elf_hwcap2(void);
436 
437 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name))
438 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name))
439 
440 static __always_inline bool system_capabilities_finalized(void)
441 {
442 	return static_branch_likely(&arm64_const_caps_ready);
443 }
444 
445 /*
446  * Test for a capability with a runtime check.
447  *
448  * Before the capability is detected, this returns false.
449  */
450 static inline bool cpus_have_cap(unsigned int num)
451 {
452 	if (num >= ARM64_NCAPS)
453 		return false;
454 	return test_bit(num, cpu_hwcaps);
455 }
456 
457 /*
458  * Test for a capability without a runtime check.
459  *
460  * Before capabilities are finalized, this returns false.
461  * After capabilities are finalized, this is patched to avoid a runtime check.
462  *
463  * @num must be a compile-time constant.
464  */
465 static __always_inline bool __cpus_have_const_cap(int num)
466 {
467 	if (num >= ARM64_NCAPS)
468 		return false;
469 	return static_branch_unlikely(&cpu_hwcap_keys[num]);
470 }
471 
472 /*
473  * Test for a capability without a runtime check.
474  *
475  * Before capabilities are finalized, this will BUG().
476  * After capabilities are finalized, this is patched to avoid a runtime check.
477  *
478  * @num must be a compile-time constant.
479  */
480 static __always_inline bool cpus_have_final_cap(int num)
481 {
482 	if (system_capabilities_finalized())
483 		return __cpus_have_const_cap(num);
484 	else
485 		BUG();
486 }
487 
488 /*
489  * Test for a capability, possibly with a runtime check for non-hyp code.
490  *
491  * For hyp code, this behaves the same as cpus_have_final_cap().
492  *
493  * For non-hyp code:
494  * Before capabilities are finalized, this behaves as cpus_have_cap().
495  * After capabilities are finalized, this is patched to avoid a runtime check.
496  *
497  * @num must be a compile-time constant.
498  */
499 static __always_inline bool cpus_have_const_cap(int num)
500 {
501 	if (is_hyp_code())
502 		return cpus_have_final_cap(num);
503 	else if (system_capabilities_finalized())
504 		return __cpus_have_const_cap(num);
505 	else
506 		return cpus_have_cap(num);
507 }
508 
509 static inline void cpus_set_cap(unsigned int num)
510 {
511 	if (num >= ARM64_NCAPS) {
512 		pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
513 			num, ARM64_NCAPS);
514 	} else {
515 		__set_bit(num, cpu_hwcaps);
516 	}
517 }
518 
519 static inline int __attribute_const__
520 cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
521 {
522 	return (s64)(features << (64 - width - field)) >> (64 - width);
523 }
524 
525 static inline int __attribute_const__
526 cpuid_feature_extract_signed_field(u64 features, int field)
527 {
528 	return cpuid_feature_extract_signed_field_width(features, field, 4);
529 }
530 
531 static __always_inline unsigned int __attribute_const__
532 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
533 {
534 	return (u64)(features << (64 - width - field)) >> (64 - width);
535 }
536 
537 static __always_inline unsigned int __attribute_const__
538 cpuid_feature_extract_unsigned_field(u64 features, int field)
539 {
540 	return cpuid_feature_extract_unsigned_field_width(features, field, 4);
541 }
542 
543 /*
544  * Fields that identify the version of the Performance Monitors Extension do
545  * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825,
546  * "Alternative ID scheme used for the Performance Monitors Extension version".
547  */
548 static inline u64 __attribute_const__
549 cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap)
550 {
551 	u64 val = cpuid_feature_extract_unsigned_field(features, field);
552 	u64 mask = GENMASK_ULL(field + 3, field);
553 
554 	/* Treat IMPLEMENTATION DEFINED functionality as unimplemented */
555 	if (val == ID_AA64DFR0_PMUVER_IMP_DEF)
556 		val = 0;
557 
558 	if (val > cap) {
559 		features &= ~mask;
560 		features |= (cap << field) & mask;
561 	}
562 
563 	return features;
564 }
565 
566 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
567 {
568 	return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
569 }
570 
571 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
572 {
573 	return (reg->user_val | (reg->sys_val & reg->user_mask));
574 }
575 
576 static inline int __attribute_const__
577 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
578 {
579 	return (sign) ?
580 		cpuid_feature_extract_signed_field_width(features, field, width) :
581 		cpuid_feature_extract_unsigned_field_width(features, field, width);
582 }
583 
584 static inline int __attribute_const__
585 cpuid_feature_extract_field(u64 features, int field, bool sign)
586 {
587 	return cpuid_feature_extract_field_width(features, field, 4, sign);
588 }
589 
590 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
591 {
592 	return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
593 }
594 
595 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
596 {
597 	return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
598 		cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
599 }
600 
601 static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
602 {
603 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SHIFT);
604 
605 	return val == ID_AA64PFR0_ELx_32BIT_64BIT;
606 }
607 
608 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
609 {
610 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
611 
612 	return val == ID_AA64PFR0_ELx_32BIT_64BIT;
613 }
614 
615 static inline bool id_aa64pfr0_sve(u64 pfr0)
616 {
617 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT);
618 
619 	return val > 0;
620 }
621 
622 static inline bool id_aa64pfr1_mte(u64 pfr1)
623 {
624 	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_MTE_SHIFT);
625 
626 	return val >= ID_AA64PFR1_MTE;
627 }
628 
629 void __init setup_cpu_features(void);
630 void check_local_cpu_capabilities(void);
631 
632 u64 read_sanitised_ftr_reg(u32 id);
633 u64 __read_sysreg_by_encoding(u32 sys_id);
634 
635 static inline bool cpu_supports_mixed_endian_el0(void)
636 {
637 	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
638 }
639 
640 const struct cpumask *system_32bit_el0_cpumask(void);
641 DECLARE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
642 
643 static inline bool system_supports_32bit_el0(void)
644 {
645 	u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
646 
647 	return static_branch_unlikely(&arm64_mismatched_32bit_el0) ||
648 	       id_aa64pfr0_32bit_el0(pfr0);
649 }
650 
651 static inline bool system_supports_4kb_granule(void)
652 {
653 	u64 mmfr0;
654 	u32 val;
655 
656 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
657 	val = cpuid_feature_extract_unsigned_field(mmfr0,
658 						ID_AA64MMFR0_TGRAN4_SHIFT);
659 
660 	return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) &&
661 	       (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX);
662 }
663 
664 static inline bool system_supports_64kb_granule(void)
665 {
666 	u64 mmfr0;
667 	u32 val;
668 
669 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
670 	val = cpuid_feature_extract_unsigned_field(mmfr0,
671 						ID_AA64MMFR0_TGRAN64_SHIFT);
672 
673 	return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) &&
674 	       (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX);
675 }
676 
677 static inline bool system_supports_16kb_granule(void)
678 {
679 	u64 mmfr0;
680 	u32 val;
681 
682 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
683 	val = cpuid_feature_extract_unsigned_field(mmfr0,
684 						ID_AA64MMFR0_TGRAN16_SHIFT);
685 
686 	return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) &&
687 	       (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX);
688 }
689 
690 static inline bool system_supports_mixed_endian_el0(void)
691 {
692 	return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1));
693 }
694 
695 static inline bool system_supports_mixed_endian(void)
696 {
697 	u64 mmfr0;
698 	u32 val;
699 
700 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
701 	val = cpuid_feature_extract_unsigned_field(mmfr0,
702 						ID_AA64MMFR0_BIGENDEL_SHIFT);
703 
704 	return val == 0x1;
705 }
706 
707 static __always_inline bool system_supports_fpsimd(void)
708 {
709 	return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);
710 }
711 
712 static inline bool system_uses_hw_pan(void)
713 {
714 	return IS_ENABLED(CONFIG_ARM64_PAN) &&
715 		cpus_have_const_cap(ARM64_HAS_PAN);
716 }
717 
718 static inline bool system_uses_ttbr0_pan(void)
719 {
720 	return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
721 		!system_uses_hw_pan();
722 }
723 
724 static __always_inline bool system_supports_sve(void)
725 {
726 	return IS_ENABLED(CONFIG_ARM64_SVE) &&
727 		cpus_have_const_cap(ARM64_SVE);
728 }
729 
730 static __always_inline bool system_supports_cnp(void)
731 {
732 	return IS_ENABLED(CONFIG_ARM64_CNP) &&
733 		cpus_have_const_cap(ARM64_HAS_CNP);
734 }
735 
736 static inline bool system_supports_address_auth(void)
737 {
738 	return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
739 		cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH);
740 }
741 
742 static inline bool system_supports_generic_auth(void)
743 {
744 	return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
745 		cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH);
746 }
747 
748 static inline bool system_has_full_ptr_auth(void)
749 {
750 	return system_supports_address_auth() && system_supports_generic_auth();
751 }
752 
753 static __always_inline bool system_uses_irq_prio_masking(void)
754 {
755 	return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
756 	       cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING);
757 }
758 
759 static inline bool system_supports_mte(void)
760 {
761 	return IS_ENABLED(CONFIG_ARM64_MTE) &&
762 		cpus_have_const_cap(ARM64_MTE);
763 }
764 
765 static inline bool system_has_prio_mask_debugging(void)
766 {
767 	return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
768 	       system_uses_irq_prio_masking();
769 }
770 
771 static inline bool system_supports_bti(void)
772 {
773 	return IS_ENABLED(CONFIG_ARM64_BTI) && cpus_have_const_cap(ARM64_BTI);
774 }
775 
776 static inline bool system_supports_tlb_range(void)
777 {
778 	return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) &&
779 		cpus_have_const_cap(ARM64_HAS_TLB_RANGE);
780 }
781 
782 extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
783 
784 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
785 {
786 	switch (parange) {
787 	case ID_AA64MMFR0_PARANGE_32: return 32;
788 	case ID_AA64MMFR0_PARANGE_36: return 36;
789 	case ID_AA64MMFR0_PARANGE_40: return 40;
790 	case ID_AA64MMFR0_PARANGE_42: return 42;
791 	case ID_AA64MMFR0_PARANGE_44: return 44;
792 	case ID_AA64MMFR0_PARANGE_48: return 48;
793 	case ID_AA64MMFR0_PARANGE_52: return 52;
794 	/*
795 	 * A future PE could use a value unknown to the kernel.
796 	 * However, by the "D10.1.4 Principles of the ID scheme
797 	 * for fields in ID registers", ARM DDI 0487C.a, any new
798 	 * value is guaranteed to be higher than what we know already.
799 	 * As a safe limit, we return the limit supported by the kernel.
800 	 */
801 	default: return CONFIG_ARM64_PA_BITS;
802 	}
803 }
804 
805 /* Check whether hardware update of the Access flag is supported */
806 static inline bool cpu_has_hw_af(void)
807 {
808 	u64 mmfr1;
809 
810 	if (!IS_ENABLED(CONFIG_ARM64_HW_AFDBM))
811 		return false;
812 
813 	mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
814 	return cpuid_feature_extract_unsigned_field(mmfr1,
815 						ID_AA64MMFR1_HADBS_SHIFT);
816 }
817 
818 static inline bool cpu_has_pan(void)
819 {
820 	u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
821 	return cpuid_feature_extract_unsigned_field(mmfr1,
822 						    ID_AA64MMFR1_PAN_SHIFT);
823 }
824 
825 #ifdef CONFIG_ARM64_AMU_EXTN
826 /* Check whether the cpu supports the Activity Monitors Unit (AMU) */
827 extern bool cpu_has_amu_feat(int cpu);
828 #else
829 static inline bool cpu_has_amu_feat(int cpu)
830 {
831 	return false;
832 }
833 #endif
834 
835 /* Get a cpu that supports the Activity Monitors Unit (AMU) */
836 extern int get_cpu_with_amu_feat(void);
837 
838 static inline unsigned int get_vmid_bits(u64 mmfr1)
839 {
840 	int vmid_bits;
841 
842 	vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,
843 						ID_AA64MMFR1_VMIDBITS_SHIFT);
844 	if (vmid_bits == ID_AA64MMFR1_VMIDBITS_16)
845 		return 16;
846 
847 	/*
848 	 * Return the default here even if any reserved
849 	 * value is fetched from the system register.
850 	 */
851 	return 8;
852 }
853 
854 extern struct arm64_ftr_override id_aa64mmfr1_override;
855 extern struct arm64_ftr_override id_aa64pfr1_override;
856 extern struct arm64_ftr_override id_aa64isar1_override;
857 
858 u32 get_kvm_ipa_limit(void);
859 void dump_cpu_features(void);
860 
861 #endif /* __ASSEMBLY__ */
862 
863 #endif
864