1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
4  */
5 
6 #ifndef __ASM_CPUFEATURE_H
7 #define __ASM_CPUFEATURE_H
8 
9 #include <asm/alternative-macros.h>
10 #include <asm/cpucaps.h>
11 #include <asm/cputype.h>
12 #include <asm/hwcap.h>
13 #include <asm/sysreg.h>
14 
15 #define MAX_CPU_FEATURES	128
16 #define cpu_feature(x)		KERNEL_HWCAP_ ## x
17 
18 #ifndef __ASSEMBLY__
19 
20 #include <linux/bug.h>
21 #include <linux/jump_label.h>
22 #include <linux/kernel.h>
23 
24 /*
25  * CPU feature register tracking
26  *
27  * The safe value of a CPUID feature field is dependent on the implications
28  * of the values assigned to it by the architecture. Based on the relationship
29  * between the values, the features are classified into 3 types - LOWER_SAFE,
30  * HIGHER_SAFE and EXACT.
31  *
32  * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
33  * for HIGHER_SAFE. It is expected that all CPUs have the same value for
34  * a field when EXACT is specified, failing which, the safe value specified
35  * in the table is chosen.
36  */
37 
38 enum ftr_type {
39 	FTR_EXACT,			/* Use a predefined safe value */
40 	FTR_LOWER_SAFE,			/* Smaller value is safe */
41 	FTR_HIGHER_SAFE,		/* Bigger value is safe */
42 	FTR_HIGHER_OR_ZERO_SAFE,	/* Bigger value is safe, but 0 is biggest */
43 };
44 
45 #define FTR_STRICT	true	/* SANITY check strict matching required */
46 #define FTR_NONSTRICT	false	/* SANITY check ignored */
47 
48 #define FTR_SIGNED	true	/* Value should be treated as signed */
49 #define FTR_UNSIGNED	false	/* Value should be treated as unsigned */
50 
51 #define FTR_VISIBLE	true	/* Feature visible to the user space */
52 #define FTR_HIDDEN	false	/* Feature is hidden from the user */
53 
54 #define FTR_VISIBLE_IF_IS_ENABLED(config)		\
55 	(IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
56 
57 struct arm64_ftr_bits {
58 	bool		sign;	/* Value is signed ? */
59 	bool		visible;
60 	bool		strict;	/* CPU Sanity check: strict matching required ? */
61 	enum ftr_type	type;
62 	u8		shift;
63 	u8		width;
64 	s64		safe_val; /* safe value for FTR_EXACT features */
65 };
66 
67 /*
68  * Describe the early feature override to the core override code:
69  *
70  * @val			Values that are to be merged into the final
71  *			sanitised value of the register. Only the bitfields
72  *			set to 1 in @mask are valid
73  * @mask		Mask of the features that are overridden by @val
74  *
75  * A @mask field set to full-1 indicates that the corresponding field
76  * in @val is a valid override.
77  *
78  * A @mask field set to full-0 with the corresponding @val field set
79  * to full-0 denotes that this field has no override
80  *
81  * A @mask field set to full-0 with the corresponding @val field set
82  * to full-1 denotes thath this field has an invalid override.
83  */
84 struct arm64_ftr_override {
85 	u64		val;
86 	u64		mask;
87 };
88 
89 /*
90  * @arm64_ftr_reg - Feature register
91  * @strict_mask		Bits which should match across all CPUs for sanity.
92  * @sys_val		Safe value across the CPUs (system view)
93  */
94 struct arm64_ftr_reg {
95 	const char			*name;
96 	u64				strict_mask;
97 	u64				user_mask;
98 	u64				sys_val;
99 	u64				user_val;
100 	struct arm64_ftr_override	*override;
101 	const struct arm64_ftr_bits	*ftr_bits;
102 };
103 
104 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
105 
106 /*
107  * CPU capabilities:
108  *
109  * We use arm64_cpu_capabilities to represent system features, errata work
110  * arounds (both used internally by kernel and tracked in cpu_hwcaps) and
111  * ELF HWCAPs (which are exposed to user).
112  *
113  * To support systems with heterogeneous CPUs, we need to make sure that we
114  * detect the capabilities correctly on the system and take appropriate
115  * measures to ensure there are no incompatibilities.
116  *
117  * This comment tries to explain how we treat the capabilities.
118  * Each capability has the following list of attributes :
119  *
120  * 1) Scope of Detection : The system detects a given capability by
121  *    performing some checks at runtime. This could be, e.g, checking the
122  *    value of a field in CPU ID feature register or checking the cpu
123  *    model. The capability provides a call back ( @matches() ) to
124  *    perform the check. Scope defines how the checks should be performed.
125  *    There are three cases:
126  *
127  *     a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
128  *        matches. This implies, we have to run the check on all the
129  *        booting CPUs, until the system decides that state of the
130  *        capability is finalised. (See section 2 below)
131  *		Or
132  *     b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
133  *        matches. This implies, we run the check only once, when the
134  *        system decides to finalise the state of the capability. If the
135  *        capability relies on a field in one of the CPU ID feature
136  *        registers, we use the sanitised value of the register from the
137  *        CPU feature infrastructure to make the decision.
138  *		Or
139  *     c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
140  *        feature. This category is for features that are "finalised"
141  *        (or used) by the kernel very early even before the SMP cpus
142  *        are brought up.
143  *
144  *    The process of detection is usually denoted by "update" capability
145  *    state in the code.
146  *
147  * 2) Finalise the state : The kernel should finalise the state of a
148  *    capability at some point during its execution and take necessary
149  *    actions if any. Usually, this is done, after all the boot-time
150  *    enabled CPUs are brought up by the kernel, so that it can make
151  *    better decision based on the available set of CPUs. However, there
152  *    are some special cases, where the action is taken during the early
153  *    boot by the primary boot CPU. (e.g, running the kernel at EL2 with
154  *    Virtualisation Host Extensions). The kernel usually disallows any
155  *    changes to the state of a capability once it finalises the capability
156  *    and takes any action, as it may be impossible to execute the actions
157  *    safely. A CPU brought up after a capability is "finalised" is
158  *    referred to as "Late CPU" w.r.t the capability. e.g, all secondary
159  *    CPUs are treated "late CPUs" for capabilities determined by the boot
160  *    CPU.
161  *
162  *    At the moment there are two passes of finalising the capabilities.
163  *      a) Boot CPU scope capabilities - Finalised by primary boot CPU via
164  *         setup_boot_cpu_capabilities().
165  *      b) Everything except (a) - Run via setup_system_capabilities().
166  *
167  * 3) Verification: When a CPU is brought online (e.g, by user or by the
168  *    kernel), the kernel should make sure that it is safe to use the CPU,
169  *    by verifying that the CPU is compliant with the state of the
170  *    capabilities finalised already. This happens via :
171  *
172  *	secondary_start_kernel()-> check_local_cpu_capabilities()
173  *
174  *    As explained in (2) above, capabilities could be finalised at
175  *    different points in the execution. Each newly booted CPU is verified
176  *    against the capabilities that have been finalised by the time it
177  *    boots.
178  *
179  *	a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
180  *	except for the primary boot CPU.
181  *
182  *	b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
183  *	user after the kernel boot are verified against the capability.
184  *
185  *    If there is a conflict, the kernel takes an action, based on the
186  *    severity (e.g, a CPU could be prevented from booting or cause a
187  *    kernel panic). The CPU is allowed to "affect" the state of the
188  *    capability, if it has not been finalised already. See section 5
189  *    for more details on conflicts.
190  *
191  * 4) Action: As mentioned in (2), the kernel can take an action for each
192  *    detected capability, on all CPUs on the system. Appropriate actions
193  *    include, turning on an architectural feature, modifying the control
194  *    registers (e.g, SCTLR, TCR etc.) or patching the kernel via
195  *    alternatives. The kernel patching is batched and performed at later
196  *    point. The actions are always initiated only after the capability
197  *    is finalised. This is usally denoted by "enabling" the capability.
198  *    The actions are initiated as follows :
199  *	a) Action is triggered on all online CPUs, after the capability is
200  *	finalised, invoked within the stop_machine() context from
201  *	enable_cpu_capabilitie().
202  *
203  *	b) Any late CPU, brought up after (1), the action is triggered via:
204  *
205  *	  check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
206  *
207  * 5) Conflicts: Based on the state of the capability on a late CPU vs.
208  *    the system state, we could have the following combinations :
209  *
210  *		x-----------------------------x
211  *		| Type  | System   | Late CPU |
212  *		|-----------------------------|
213  *		|  a    |   y      |    n     |
214  *		|-----------------------------|
215  *		|  b    |   n      |    y     |
216  *		x-----------------------------x
217  *
218  *     Two separate flag bits are defined to indicate whether each kind of
219  *     conflict can be allowed:
220  *		ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
221  *		ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
222  *
223  *     Case (a) is not permitted for a capability that the system requires
224  *     all CPUs to have in order for the capability to be enabled. This is
225  *     typical for capabilities that represent enhanced functionality.
226  *
227  *     Case (b) is not permitted for a capability that must be enabled
228  *     during boot if any CPU in the system requires it in order to run
229  *     safely. This is typical for erratum work arounds that cannot be
230  *     enabled after the corresponding capability is finalised.
231  *
232  *     In some non-typical cases either both (a) and (b), or neither,
233  *     should be permitted. This can be described by including neither
234  *     or both flags in the capability's type field.
235  *
236  *     In case of a conflict, the CPU is prevented from booting. If the
237  *     ARM64_CPUCAP_PANIC_ON_CONFLICT flag is specified for the capability,
238  *     then a kernel panic is triggered.
239  */
240 
241 
242 /*
243  * Decide how the capability is detected.
244  * On any local CPU vs System wide vs the primary boot CPU
245  */
246 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU		((u16)BIT(0))
247 #define ARM64_CPUCAP_SCOPE_SYSTEM		((u16)BIT(1))
248 /*
249  * The capabilitiy is detected on the Boot CPU and is used by kernel
250  * during early boot. i.e, the capability should be "detected" and
251  * "enabled" as early as possibly on all booting CPUs.
252  */
253 #define ARM64_CPUCAP_SCOPE_BOOT_CPU		((u16)BIT(2))
254 #define ARM64_CPUCAP_SCOPE_MASK			\
255 	(ARM64_CPUCAP_SCOPE_SYSTEM	|	\
256 	 ARM64_CPUCAP_SCOPE_LOCAL_CPU	|	\
257 	 ARM64_CPUCAP_SCOPE_BOOT_CPU)
258 
259 #define SCOPE_SYSTEM				ARM64_CPUCAP_SCOPE_SYSTEM
260 #define SCOPE_LOCAL_CPU				ARM64_CPUCAP_SCOPE_LOCAL_CPU
261 #define SCOPE_BOOT_CPU				ARM64_CPUCAP_SCOPE_BOOT_CPU
262 #define SCOPE_ALL				ARM64_CPUCAP_SCOPE_MASK
263 
264 /*
265  * Is it permitted for a late CPU to have this capability when system
266  * hasn't already enabled it ?
267  */
268 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU	((u16)BIT(4))
269 /* Is it safe for a late CPU to miss this capability when system has it */
270 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU	((u16)BIT(5))
271 /* Panic when a conflict is detected */
272 #define ARM64_CPUCAP_PANIC_ON_CONFLICT		((u16)BIT(6))
273 
274 /*
275  * CPU errata workarounds that need to be enabled at boot time if one or
276  * more CPUs in the system requires it. When one of these capabilities
277  * has been enabled, it is safe to allow any CPU to boot that doesn't
278  * require the workaround. However, it is not safe if a "late" CPU
279  * requires a workaround and the system hasn't enabled it already.
280  */
281 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM		\
282 	(ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
283 /*
284  * CPU feature detected at boot time based on system-wide value of a
285  * feature. It is safe for a late CPU to have this feature even though
286  * the system hasn't enabled it, although the feature will not be used
287  * by Linux in this case. If the system has enabled this feature already,
288  * then every late CPU must have it.
289  */
290 #define ARM64_CPUCAP_SYSTEM_FEATURE	\
291 	(ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
292 /*
293  * CPU feature detected at boot time based on feature of one or more CPUs.
294  * All possible conflicts for a late CPU are ignored.
295  * NOTE: this means that a late CPU with the feature will *not* cause the
296  * capability to be advertised by cpus_have_*cap()!
297  */
298 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE		\
299 	(ARM64_CPUCAP_SCOPE_LOCAL_CPU		|	\
300 	 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU	|	\
301 	 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
302 
303 /*
304  * CPU feature detected at boot time, on one or more CPUs. A late CPU
305  * is not allowed to have the capability when the system doesn't have it.
306  * It is Ok for a late CPU to miss the feature.
307  */
308 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE	\
309 	(ARM64_CPUCAP_SCOPE_LOCAL_CPU		|	\
310 	 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
311 
312 /*
313  * CPU feature used early in the boot based on the boot CPU. All secondary
314  * CPUs must match the state of the capability as detected by the boot CPU. In
315  * case of a conflict, a kernel panic is triggered.
316  */
317 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE		\
318 	(ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT)
319 
320 /*
321  * CPU feature used early in the boot based on the boot CPU. It is safe for a
322  * late CPU to have this feature even though the boot CPU hasn't enabled it,
323  * although the feature will not be used by Linux in this case. If the boot CPU
324  * has enabled this feature already, then every late CPU must have it.
325  */
326 #define ARM64_CPUCAP_BOOT_CPU_FEATURE                  \
327 	(ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
328 
329 struct arm64_cpu_capabilities {
330 	const char *desc;
331 	u16 capability;
332 	u16 type;
333 	bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
334 	/*
335 	 * Take the appropriate actions to configure this capability
336 	 * for this CPU. If the capability is detected by the kernel
337 	 * this will be called on all the CPUs in the system,
338 	 * including the hotplugged CPUs, regardless of whether the
339 	 * capability is available on that specific CPU. This is
340 	 * useful for some capabilities (e.g, working around CPU
341 	 * errata), where all the CPUs must take some action (e.g,
342 	 * changing system control/configuration). Thus, if an action
343 	 * is required only if the CPU has the capability, then the
344 	 * routine must check it before taking any action.
345 	 */
346 	void (*cpu_enable)(const struct arm64_cpu_capabilities *cap);
347 	union {
348 		struct {	/* To be used for erratum handling only */
349 			struct midr_range midr_range;
350 			const struct arm64_midr_revidr {
351 				u32 midr_rv;		/* revision/variant */
352 				u32 revidr_mask;
353 			} * const fixed_revs;
354 		};
355 
356 		const struct midr_range *midr_range_list;
357 		struct {	/* Feature register checking */
358 			u32 sys_reg;
359 			u8 field_pos;
360 			u8 field_width;
361 			u8 min_field_value;
362 			u8 hwcap_type;
363 			bool sign;
364 			unsigned long hwcap;
365 		};
366 	};
367 
368 	/*
369 	 * An optional list of "matches/cpu_enable" pair for the same
370 	 * "capability" of the same "type" as described by the parent.
371 	 * Only matches(), cpu_enable() and fields relevant to these
372 	 * methods are significant in the list. The cpu_enable is
373 	 * invoked only if the corresponding entry "matches()".
374 	 * However, if a cpu_enable() method is associated
375 	 * with multiple matches(), care should be taken that either
376 	 * the match criteria are mutually exclusive, or that the
377 	 * method is robust against being called multiple times.
378 	 */
379 	const struct arm64_cpu_capabilities *match_list;
380 };
381 
382 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
383 {
384 	return cap->type & ARM64_CPUCAP_SCOPE_MASK;
385 }
386 
387 /*
388  * Generic helper for handling capabilities with multiple (match,enable) pairs
389  * of call backs, sharing the same capability bit.
390  * Iterate over each entry to see if at least one matches.
391  */
392 static inline bool
393 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
394 			       int scope)
395 {
396 	const struct arm64_cpu_capabilities *caps;
397 
398 	for (caps = entry->match_list; caps->matches; caps++)
399 		if (caps->matches(caps, scope))
400 			return true;
401 
402 	return false;
403 }
404 
405 static __always_inline bool is_vhe_hyp_code(void)
406 {
407 	/* Only defined for code run in VHE hyp context */
408 	return __is_defined(__KVM_VHE_HYPERVISOR__);
409 }
410 
411 static __always_inline bool is_nvhe_hyp_code(void)
412 {
413 	/* Only defined for code run in NVHE hyp context */
414 	return __is_defined(__KVM_NVHE_HYPERVISOR__);
415 }
416 
417 static __always_inline bool is_hyp_code(void)
418 {
419 	return is_vhe_hyp_code() || is_nvhe_hyp_code();
420 }
421 
422 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
423 
424 extern DECLARE_BITMAP(boot_capabilities, ARM64_NCAPS);
425 
426 #define for_each_available_cap(cap)		\
427 	for_each_set_bit(cap, cpu_hwcaps, ARM64_NCAPS)
428 
429 bool this_cpu_has_cap(unsigned int cap);
430 void cpu_set_feature(unsigned int num);
431 bool cpu_have_feature(unsigned int num);
432 unsigned long cpu_get_elf_hwcap(void);
433 unsigned long cpu_get_elf_hwcap2(void);
434 
435 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name))
436 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name))
437 
438 static __always_inline bool system_capabilities_finalized(void)
439 {
440 	return alternative_has_feature_likely(ARM64_ALWAYS_SYSTEM);
441 }
442 
443 /*
444  * Test for a capability with a runtime check.
445  *
446  * Before the capability is detected, this returns false.
447  */
448 static __always_inline bool cpus_have_cap(unsigned int num)
449 {
450 	if (num >= ARM64_NCAPS)
451 		return false;
452 	return arch_test_bit(num, cpu_hwcaps);
453 }
454 
455 /*
456  * Test for a capability without a runtime check.
457  *
458  * Before capabilities are finalized, this returns false.
459  * After capabilities are finalized, this is patched to avoid a runtime check.
460  *
461  * @num must be a compile-time constant.
462  */
463 static __always_inline bool __cpus_have_const_cap(int num)
464 {
465 	if (num >= ARM64_NCAPS)
466 		return false;
467 	return alternative_has_feature_unlikely(num);
468 }
469 
470 /*
471  * Test for a capability without a runtime check.
472  *
473  * Before capabilities are finalized, this will BUG().
474  * After capabilities are finalized, this is patched to avoid a runtime check.
475  *
476  * @num must be a compile-time constant.
477  */
478 static __always_inline bool cpus_have_final_cap(int num)
479 {
480 	if (system_capabilities_finalized())
481 		return __cpus_have_const_cap(num);
482 	else
483 		BUG();
484 }
485 
486 /*
487  * Test for a capability, possibly with a runtime check for non-hyp code.
488  *
489  * For hyp code, this behaves the same as cpus_have_final_cap().
490  *
491  * For non-hyp code:
492  * Before capabilities are finalized, this behaves as cpus_have_cap().
493  * After capabilities are finalized, this is patched to avoid a runtime check.
494  *
495  * @num must be a compile-time constant.
496  */
497 static __always_inline bool cpus_have_const_cap(int num)
498 {
499 	if (is_hyp_code())
500 		return cpus_have_final_cap(num);
501 	else if (system_capabilities_finalized())
502 		return __cpus_have_const_cap(num);
503 	else
504 		return cpus_have_cap(num);
505 }
506 
507 static inline void cpus_set_cap(unsigned int num)
508 {
509 	if (num >= ARM64_NCAPS) {
510 		pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
511 			num, ARM64_NCAPS);
512 	} else {
513 		__set_bit(num, cpu_hwcaps);
514 	}
515 }
516 
517 static inline int __attribute_const__
518 cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
519 {
520 	return (s64)(features << (64 - width - field)) >> (64 - width);
521 }
522 
523 static inline int __attribute_const__
524 cpuid_feature_extract_signed_field(u64 features, int field)
525 {
526 	return cpuid_feature_extract_signed_field_width(features, field, 4);
527 }
528 
529 static __always_inline unsigned int __attribute_const__
530 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
531 {
532 	return (u64)(features << (64 - width - field)) >> (64 - width);
533 }
534 
535 static __always_inline unsigned int __attribute_const__
536 cpuid_feature_extract_unsigned_field(u64 features, int field)
537 {
538 	return cpuid_feature_extract_unsigned_field_width(features, field, 4);
539 }
540 
541 /*
542  * Fields that identify the version of the Performance Monitors Extension do
543  * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825,
544  * "Alternative ID scheme used for the Performance Monitors Extension version".
545  */
546 static inline u64 __attribute_const__
547 cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap)
548 {
549 	u64 val = cpuid_feature_extract_unsigned_field(features, field);
550 	u64 mask = GENMASK_ULL(field + 3, field);
551 
552 	/* Treat IMPLEMENTATION DEFINED functionality as unimplemented */
553 	if (val == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
554 		val = 0;
555 
556 	if (val > cap) {
557 		features &= ~mask;
558 		features |= (cap << field) & mask;
559 	}
560 
561 	return features;
562 }
563 
564 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
565 {
566 	return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
567 }
568 
569 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
570 {
571 	return (reg->user_val | (reg->sys_val & reg->user_mask));
572 }
573 
574 static inline int __attribute_const__
575 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
576 {
577 	if (WARN_ON_ONCE(!width))
578 		width = 4;
579 	return (sign) ?
580 		cpuid_feature_extract_signed_field_width(features, field, width) :
581 		cpuid_feature_extract_unsigned_field_width(features, field, width);
582 }
583 
584 static inline int __attribute_const__
585 cpuid_feature_extract_field(u64 features, int field, bool sign)
586 {
587 	return cpuid_feature_extract_field_width(features, field, 4, sign);
588 }
589 
590 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
591 {
592 	return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
593 }
594 
595 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
596 {
597 	return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGEND_SHIFT) == 0x1 ||
598 		cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT) == 0x1;
599 }
600 
601 static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
602 {
603 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL1_SHIFT);
604 
605 	return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
606 }
607 
608 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
609 {
610 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL0_SHIFT);
611 
612 	return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT;
613 }
614 
615 static inline bool id_aa64pfr0_sve(u64 pfr0)
616 {
617 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SVE_SHIFT);
618 
619 	return val > 0;
620 }
621 
622 static inline bool id_aa64pfr1_sme(u64 pfr1)
623 {
624 	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_SME_SHIFT);
625 
626 	return val > 0;
627 }
628 
629 static inline bool id_aa64pfr1_mte(u64 pfr1)
630 {
631 	u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT);
632 
633 	return val >= ID_AA64PFR1_EL1_MTE_MTE2;
634 }
635 
636 void __init setup_cpu_features(void);
637 void check_local_cpu_capabilities(void);
638 
639 u64 read_sanitised_ftr_reg(u32 id);
640 u64 __read_sysreg_by_encoding(u32 sys_id);
641 
642 static inline bool cpu_supports_mixed_endian_el0(void)
643 {
644 	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
645 }
646 
647 
648 static inline bool supports_csv2p3(int scope)
649 {
650 	u64 pfr0;
651 	u8 csv2_val;
652 
653 	if (scope == SCOPE_LOCAL_CPU)
654 		pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
655 	else
656 		pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
657 
658 	csv2_val = cpuid_feature_extract_unsigned_field(pfr0,
659 							ID_AA64PFR0_EL1_CSV2_SHIFT);
660 	return csv2_val == 3;
661 }
662 
663 static inline bool supports_clearbhb(int scope)
664 {
665 	u64 isar2;
666 
667 	if (scope == SCOPE_LOCAL_CPU)
668 		isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1);
669 	else
670 		isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
671 
672 	return cpuid_feature_extract_unsigned_field(isar2,
673 						    ID_AA64ISAR2_EL1_BC_SHIFT);
674 }
675 
676 const struct cpumask *system_32bit_el0_cpumask(void);
677 DECLARE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0);
678 
679 static inline bool system_supports_32bit_el0(void)
680 {
681 	u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
682 
683 	return static_branch_unlikely(&arm64_mismatched_32bit_el0) ||
684 	       id_aa64pfr0_32bit_el0(pfr0);
685 }
686 
687 static inline bool system_supports_4kb_granule(void)
688 {
689 	u64 mmfr0;
690 	u32 val;
691 
692 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
693 	val = cpuid_feature_extract_unsigned_field(mmfr0,
694 						ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
695 
696 	return (val >= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN) &&
697 	       (val <= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX);
698 }
699 
700 static inline bool system_supports_64kb_granule(void)
701 {
702 	u64 mmfr0;
703 	u32 val;
704 
705 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
706 	val = cpuid_feature_extract_unsigned_field(mmfr0,
707 						ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
708 
709 	return (val >= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN) &&
710 	       (val <= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX);
711 }
712 
713 static inline bool system_supports_16kb_granule(void)
714 {
715 	u64 mmfr0;
716 	u32 val;
717 
718 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
719 	val = cpuid_feature_extract_unsigned_field(mmfr0,
720 						ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
721 
722 	return (val >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN) &&
723 	       (val <= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX);
724 }
725 
726 static inline bool system_supports_mixed_endian_el0(void)
727 {
728 	return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1));
729 }
730 
731 static inline bool system_supports_mixed_endian(void)
732 {
733 	u64 mmfr0;
734 	u32 val;
735 
736 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
737 	val = cpuid_feature_extract_unsigned_field(mmfr0,
738 						ID_AA64MMFR0_EL1_BIGEND_SHIFT);
739 
740 	return val == 0x1;
741 }
742 
743 static __always_inline bool system_supports_fpsimd(void)
744 {
745 	return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);
746 }
747 
748 static inline bool system_uses_hw_pan(void)
749 {
750 	return IS_ENABLED(CONFIG_ARM64_PAN) &&
751 		cpus_have_const_cap(ARM64_HAS_PAN);
752 }
753 
754 static inline bool system_uses_ttbr0_pan(void)
755 {
756 	return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
757 		!system_uses_hw_pan();
758 }
759 
760 static __always_inline bool system_supports_sve(void)
761 {
762 	return IS_ENABLED(CONFIG_ARM64_SVE) &&
763 		cpus_have_const_cap(ARM64_SVE);
764 }
765 
766 static __always_inline bool system_supports_sme(void)
767 {
768 	return IS_ENABLED(CONFIG_ARM64_SME) &&
769 		cpus_have_const_cap(ARM64_SME);
770 }
771 
772 static __always_inline bool system_supports_sme2(void)
773 {
774 	return IS_ENABLED(CONFIG_ARM64_SME) &&
775 		cpus_have_const_cap(ARM64_SME2);
776 }
777 
778 static __always_inline bool system_supports_fa64(void)
779 {
780 	return IS_ENABLED(CONFIG_ARM64_SME) &&
781 		cpus_have_const_cap(ARM64_SME_FA64);
782 }
783 
784 static __always_inline bool system_supports_tpidr2(void)
785 {
786 	return system_supports_sme();
787 }
788 
789 static __always_inline bool system_supports_cnp(void)
790 {
791 	return IS_ENABLED(CONFIG_ARM64_CNP) &&
792 		cpus_have_const_cap(ARM64_HAS_CNP);
793 }
794 
795 static inline bool system_supports_address_auth(void)
796 {
797 	return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
798 		cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH);
799 }
800 
801 static inline bool system_supports_generic_auth(void)
802 {
803 	return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
804 		cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH);
805 }
806 
807 static inline bool system_has_full_ptr_auth(void)
808 {
809 	return system_supports_address_auth() && system_supports_generic_auth();
810 }
811 
812 static __always_inline bool system_uses_irq_prio_masking(void)
813 {
814 	return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
815 	       cpus_have_const_cap(ARM64_HAS_GIC_PRIO_MASKING);
816 }
817 
818 static inline bool system_supports_mte(void)
819 {
820 	return IS_ENABLED(CONFIG_ARM64_MTE) &&
821 		cpus_have_const_cap(ARM64_MTE);
822 }
823 
824 static inline bool system_has_prio_mask_debugging(void)
825 {
826 	return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
827 	       system_uses_irq_prio_masking();
828 }
829 
830 static inline bool system_supports_bti(void)
831 {
832 	return IS_ENABLED(CONFIG_ARM64_BTI) && cpus_have_const_cap(ARM64_BTI);
833 }
834 
835 static inline bool system_supports_tlb_range(void)
836 {
837 	return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) &&
838 		cpus_have_const_cap(ARM64_HAS_TLB_RANGE);
839 }
840 
841 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
842 bool try_emulate_mrs(struct pt_regs *regs, u32 isn);
843 
844 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
845 {
846 	switch (parange) {
847 	case ID_AA64MMFR0_EL1_PARANGE_32: return 32;
848 	case ID_AA64MMFR0_EL1_PARANGE_36: return 36;
849 	case ID_AA64MMFR0_EL1_PARANGE_40: return 40;
850 	case ID_AA64MMFR0_EL1_PARANGE_42: return 42;
851 	case ID_AA64MMFR0_EL1_PARANGE_44: return 44;
852 	case ID_AA64MMFR0_EL1_PARANGE_48: return 48;
853 	case ID_AA64MMFR0_EL1_PARANGE_52: return 52;
854 	/*
855 	 * A future PE could use a value unknown to the kernel.
856 	 * However, by the "D10.1.4 Principles of the ID scheme
857 	 * for fields in ID registers", ARM DDI 0487C.a, any new
858 	 * value is guaranteed to be higher than what we know already.
859 	 * As a safe limit, we return the limit supported by the kernel.
860 	 */
861 	default: return CONFIG_ARM64_PA_BITS;
862 	}
863 }
864 
865 /* Check whether hardware update of the Access flag is supported */
866 static inline bool cpu_has_hw_af(void)
867 {
868 	u64 mmfr1;
869 
870 	if (!IS_ENABLED(CONFIG_ARM64_HW_AFDBM))
871 		return false;
872 
873 	/*
874 	 * Use cached version to avoid emulated msr operation on KVM
875 	 * guests.
876 	 */
877 	mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
878 	return cpuid_feature_extract_unsigned_field(mmfr1,
879 						ID_AA64MMFR1_EL1_HAFDBS_SHIFT);
880 }
881 
882 static inline bool cpu_has_pan(void)
883 {
884 	u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
885 	return cpuid_feature_extract_unsigned_field(mmfr1,
886 						    ID_AA64MMFR1_EL1_PAN_SHIFT);
887 }
888 
889 #ifdef CONFIG_ARM64_AMU_EXTN
890 /* Check whether the cpu supports the Activity Monitors Unit (AMU) */
891 extern bool cpu_has_amu_feat(int cpu);
892 #else
893 static inline bool cpu_has_amu_feat(int cpu)
894 {
895 	return false;
896 }
897 #endif
898 
899 /* Get a cpu that supports the Activity Monitors Unit (AMU) */
900 extern int get_cpu_with_amu_feat(void);
901 
902 static inline unsigned int get_vmid_bits(u64 mmfr1)
903 {
904 	int vmid_bits;
905 
906 	vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1,
907 						ID_AA64MMFR1_EL1_VMIDBits_SHIFT);
908 	if (vmid_bits == ID_AA64MMFR1_EL1_VMIDBits_16)
909 		return 16;
910 
911 	/*
912 	 * Return the default here even if any reserved
913 	 * value is fetched from the system register.
914 	 */
915 	return 8;
916 }
917 
918 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id);
919 
920 extern struct arm64_ftr_override id_aa64mmfr1_override;
921 extern struct arm64_ftr_override id_aa64pfr0_override;
922 extern struct arm64_ftr_override id_aa64pfr1_override;
923 extern struct arm64_ftr_override id_aa64zfr0_override;
924 extern struct arm64_ftr_override id_aa64smfr0_override;
925 extern struct arm64_ftr_override id_aa64isar1_override;
926 extern struct arm64_ftr_override id_aa64isar2_override;
927 
928 u32 get_kvm_ipa_limit(void);
929 void dump_cpu_features(void);
930 
931 #endif /* __ASSEMBLY__ */
932 
933 #endif
934