1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org> 4 */ 5 6 #ifndef __ASM_CPUFEATURE_H 7 #define __ASM_CPUFEATURE_H 8 9 #include <asm/alternative-macros.h> 10 #include <asm/cpucaps.h> 11 #include <asm/cputype.h> 12 #include <asm/hwcap.h> 13 #include <asm/sysreg.h> 14 15 #define MAX_CPU_FEATURES 128 16 #define cpu_feature(x) KERNEL_HWCAP_ ## x 17 18 #ifndef __ASSEMBLY__ 19 20 #include <linux/bug.h> 21 #include <linux/jump_label.h> 22 #include <linux/kernel.h> 23 24 /* 25 * CPU feature register tracking 26 * 27 * The safe value of a CPUID feature field is dependent on the implications 28 * of the values assigned to it by the architecture. Based on the relationship 29 * between the values, the features are classified into 3 types - LOWER_SAFE, 30 * HIGHER_SAFE and EXACT. 31 * 32 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest 33 * for HIGHER_SAFE. It is expected that all CPUs have the same value for 34 * a field when EXACT is specified, failing which, the safe value specified 35 * in the table is chosen. 36 */ 37 38 enum ftr_type { 39 FTR_EXACT, /* Use a predefined safe value */ 40 FTR_LOWER_SAFE, /* Smaller value is safe */ 41 FTR_HIGHER_SAFE, /* Bigger value is safe */ 42 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ 43 }; 44 45 #define FTR_STRICT true /* SANITY check strict matching required */ 46 #define FTR_NONSTRICT false /* SANITY check ignored */ 47 48 #define FTR_SIGNED true /* Value should be treated as signed */ 49 #define FTR_UNSIGNED false /* Value should be treated as unsigned */ 50 51 #define FTR_VISIBLE true /* Feature visible to the user space */ 52 #define FTR_HIDDEN false /* Feature is hidden from the user */ 53 54 #define FTR_VISIBLE_IF_IS_ENABLED(config) \ 55 (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN) 56 57 struct arm64_ftr_bits { 58 bool sign; /* Value is signed ? */ 59 bool visible; 60 bool strict; /* CPU Sanity check: strict matching required ? */ 61 enum ftr_type type; 62 u8 shift; 63 u8 width; 64 s64 safe_val; /* safe value for FTR_EXACT features */ 65 }; 66 67 /* 68 * Describe the early feature override to the core override code: 69 * 70 * @val Values that are to be merged into the final 71 * sanitised value of the register. Only the bitfields 72 * set to 1 in @mask are valid 73 * @mask Mask of the features that are overridden by @val 74 * 75 * A @mask field set to full-1 indicates that the corresponding field 76 * in @val is a valid override. 77 * 78 * A @mask field set to full-0 with the corresponding @val field set 79 * to full-0 denotes that this field has no override 80 * 81 * A @mask field set to full-0 with the corresponding @val field set 82 * to full-1 denotes thath this field has an invalid override. 83 */ 84 struct arm64_ftr_override { 85 u64 val; 86 u64 mask; 87 }; 88 89 /* 90 * @arm64_ftr_reg - Feature register 91 * @strict_mask Bits which should match across all CPUs for sanity. 92 * @sys_val Safe value across the CPUs (system view) 93 */ 94 struct arm64_ftr_reg { 95 const char *name; 96 u64 strict_mask; 97 u64 user_mask; 98 u64 sys_val; 99 u64 user_val; 100 struct arm64_ftr_override *override; 101 const struct arm64_ftr_bits *ftr_bits; 102 }; 103 104 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; 105 106 /* 107 * CPU capabilities: 108 * 109 * We use arm64_cpu_capabilities to represent system features, errata work 110 * arounds (both used internally by kernel and tracked in system_cpucaps) and 111 * ELF HWCAPs (which are exposed to user). 112 * 113 * To support systems with heterogeneous CPUs, we need to make sure that we 114 * detect the capabilities correctly on the system and take appropriate 115 * measures to ensure there are no incompatibilities. 116 * 117 * This comment tries to explain how we treat the capabilities. 118 * Each capability has the following list of attributes : 119 * 120 * 1) Scope of Detection : The system detects a given capability by 121 * performing some checks at runtime. This could be, e.g, checking the 122 * value of a field in CPU ID feature register or checking the cpu 123 * model. The capability provides a call back ( @matches() ) to 124 * perform the check. Scope defines how the checks should be performed. 125 * There are three cases: 126 * 127 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one 128 * matches. This implies, we have to run the check on all the 129 * booting CPUs, until the system decides that state of the 130 * capability is finalised. (See section 2 below) 131 * Or 132 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs 133 * matches. This implies, we run the check only once, when the 134 * system decides to finalise the state of the capability. If the 135 * capability relies on a field in one of the CPU ID feature 136 * registers, we use the sanitised value of the register from the 137 * CPU feature infrastructure to make the decision. 138 * Or 139 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the 140 * feature. This category is for features that are "finalised" 141 * (or used) by the kernel very early even before the SMP cpus 142 * are brought up. 143 * 144 * The process of detection is usually denoted by "update" capability 145 * state in the code. 146 * 147 * 2) Finalise the state : The kernel should finalise the state of a 148 * capability at some point during its execution and take necessary 149 * actions if any. Usually, this is done, after all the boot-time 150 * enabled CPUs are brought up by the kernel, so that it can make 151 * better decision based on the available set of CPUs. However, there 152 * are some special cases, where the action is taken during the early 153 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with 154 * Virtualisation Host Extensions). The kernel usually disallows any 155 * changes to the state of a capability once it finalises the capability 156 * and takes any action, as it may be impossible to execute the actions 157 * safely. A CPU brought up after a capability is "finalised" is 158 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary 159 * CPUs are treated "late CPUs" for capabilities determined by the boot 160 * CPU. 161 * 162 * At the moment there are two passes of finalising the capabilities. 163 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via 164 * setup_boot_cpu_capabilities(). 165 * b) Everything except (a) - Run via setup_system_capabilities(). 166 * 167 * 3) Verification: When a CPU is brought online (e.g, by user or by the 168 * kernel), the kernel should make sure that it is safe to use the CPU, 169 * by verifying that the CPU is compliant with the state of the 170 * capabilities finalised already. This happens via : 171 * 172 * secondary_start_kernel()-> check_local_cpu_capabilities() 173 * 174 * As explained in (2) above, capabilities could be finalised at 175 * different points in the execution. Each newly booted CPU is verified 176 * against the capabilities that have been finalised by the time it 177 * boots. 178 * 179 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability 180 * except for the primary boot CPU. 181 * 182 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the 183 * user after the kernel boot are verified against the capability. 184 * 185 * If there is a conflict, the kernel takes an action, based on the 186 * severity (e.g, a CPU could be prevented from booting or cause a 187 * kernel panic). The CPU is allowed to "affect" the state of the 188 * capability, if it has not been finalised already. See section 5 189 * for more details on conflicts. 190 * 191 * 4) Action: As mentioned in (2), the kernel can take an action for each 192 * detected capability, on all CPUs on the system. Appropriate actions 193 * include, turning on an architectural feature, modifying the control 194 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via 195 * alternatives. The kernel patching is batched and performed at later 196 * point. The actions are always initiated only after the capability 197 * is finalised. This is usally denoted by "enabling" the capability. 198 * The actions are initiated as follows : 199 * a) Action is triggered on all online CPUs, after the capability is 200 * finalised, invoked within the stop_machine() context from 201 * enable_cpu_capabilitie(). 202 * 203 * b) Any late CPU, brought up after (1), the action is triggered via: 204 * 205 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities() 206 * 207 * 5) Conflicts: Based on the state of the capability on a late CPU vs. 208 * the system state, we could have the following combinations : 209 * 210 * x-----------------------------x 211 * | Type | System | Late CPU | 212 * |-----------------------------| 213 * | a | y | n | 214 * |-----------------------------| 215 * | b | n | y | 216 * x-----------------------------x 217 * 218 * Two separate flag bits are defined to indicate whether each kind of 219 * conflict can be allowed: 220 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed 221 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed 222 * 223 * Case (a) is not permitted for a capability that the system requires 224 * all CPUs to have in order for the capability to be enabled. This is 225 * typical for capabilities that represent enhanced functionality. 226 * 227 * Case (b) is not permitted for a capability that must be enabled 228 * during boot if any CPU in the system requires it in order to run 229 * safely. This is typical for erratum work arounds that cannot be 230 * enabled after the corresponding capability is finalised. 231 * 232 * In some non-typical cases either both (a) and (b), or neither, 233 * should be permitted. This can be described by including neither 234 * or both flags in the capability's type field. 235 * 236 * In case of a conflict, the CPU is prevented from booting. If the 237 * ARM64_CPUCAP_PANIC_ON_CONFLICT flag is specified for the capability, 238 * then a kernel panic is triggered. 239 */ 240 241 242 /* 243 * Decide how the capability is detected. 244 * On any local CPU vs System wide vs the primary boot CPU 245 */ 246 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0)) 247 #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1)) 248 /* 249 * The capabilitiy is detected on the Boot CPU and is used by kernel 250 * during early boot. i.e, the capability should be "detected" and 251 * "enabled" as early as possibly on all booting CPUs. 252 */ 253 #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2)) 254 #define ARM64_CPUCAP_SCOPE_MASK \ 255 (ARM64_CPUCAP_SCOPE_SYSTEM | \ 256 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 257 ARM64_CPUCAP_SCOPE_BOOT_CPU) 258 259 #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM 260 #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU 261 #define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU 262 #define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK 263 264 /* 265 * Is it permitted for a late CPU to have this capability when system 266 * hasn't already enabled it ? 267 */ 268 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4)) 269 /* Is it safe for a late CPU to miss this capability when system has it */ 270 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5)) 271 /* Panic when a conflict is detected */ 272 #define ARM64_CPUCAP_PANIC_ON_CONFLICT ((u16)BIT(6)) 273 274 /* 275 * CPU errata workarounds that need to be enabled at boot time if one or 276 * more CPUs in the system requires it. When one of these capabilities 277 * has been enabled, it is safe to allow any CPU to boot that doesn't 278 * require the workaround. However, it is not safe if a "late" CPU 279 * requires a workaround and the system hasn't enabled it already. 280 */ 281 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \ 282 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU) 283 /* 284 * CPU feature detected at boot time based on system-wide value of a 285 * feature. It is safe for a late CPU to have this feature even though 286 * the system hasn't enabled it, although the feature will not be used 287 * by Linux in this case. If the system has enabled this feature already, 288 * then every late CPU must have it. 289 */ 290 #define ARM64_CPUCAP_SYSTEM_FEATURE \ 291 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 292 /* 293 * CPU feature detected at boot time based on feature of one or more CPUs. 294 * All possible conflicts for a late CPU are ignored. 295 * NOTE: this means that a late CPU with the feature will *not* cause the 296 * capability to be advertised by cpus_have_*cap()! 297 */ 298 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \ 299 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 300 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \ 301 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 302 303 /* 304 * CPU feature detected at boot time, on one or more CPUs. A late CPU 305 * is not allowed to have the capability when the system doesn't have it. 306 * It is Ok for a late CPU to miss the feature. 307 */ 308 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \ 309 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 310 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU) 311 312 /* 313 * CPU feature used early in the boot based on the boot CPU. All secondary 314 * CPUs must match the state of the capability as detected by the boot CPU. In 315 * case of a conflict, a kernel panic is triggered. 316 */ 317 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE \ 318 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT) 319 320 /* 321 * CPU feature used early in the boot based on the boot CPU. It is safe for a 322 * late CPU to have this feature even though the boot CPU hasn't enabled it, 323 * although the feature will not be used by Linux in this case. If the boot CPU 324 * has enabled this feature already, then every late CPU must have it. 325 */ 326 #define ARM64_CPUCAP_BOOT_CPU_FEATURE \ 327 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 328 329 struct arm64_cpu_capabilities { 330 const char *desc; 331 u16 capability; 332 u16 type; 333 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); 334 /* 335 * Take the appropriate actions to configure this capability 336 * for this CPU. If the capability is detected by the kernel 337 * this will be called on all the CPUs in the system, 338 * including the hotplugged CPUs, regardless of whether the 339 * capability is available on that specific CPU. This is 340 * useful for some capabilities (e.g, working around CPU 341 * errata), where all the CPUs must take some action (e.g, 342 * changing system control/configuration). Thus, if an action 343 * is required only if the CPU has the capability, then the 344 * routine must check it before taking any action. 345 */ 346 void (*cpu_enable)(const struct arm64_cpu_capabilities *cap); 347 union { 348 struct { /* To be used for erratum handling only */ 349 struct midr_range midr_range; 350 const struct arm64_midr_revidr { 351 u32 midr_rv; /* revision/variant */ 352 u32 revidr_mask; 353 } * const fixed_revs; 354 }; 355 356 const struct midr_range *midr_range_list; 357 struct { /* Feature register checking */ 358 u32 sys_reg; 359 u8 field_pos; 360 u8 field_width; 361 u8 min_field_value; 362 u8 hwcap_type; 363 bool sign; 364 unsigned long hwcap; 365 }; 366 }; 367 368 /* 369 * An optional list of "matches/cpu_enable" pair for the same 370 * "capability" of the same "type" as described by the parent. 371 * Only matches(), cpu_enable() and fields relevant to these 372 * methods are significant in the list. The cpu_enable is 373 * invoked only if the corresponding entry "matches()". 374 * However, if a cpu_enable() method is associated 375 * with multiple matches(), care should be taken that either 376 * the match criteria are mutually exclusive, or that the 377 * method is robust against being called multiple times. 378 */ 379 const struct arm64_cpu_capabilities *match_list; 380 }; 381 382 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap) 383 { 384 return cap->type & ARM64_CPUCAP_SCOPE_MASK; 385 } 386 387 /* 388 * Generic helper for handling capabilities with multiple (match,enable) pairs 389 * of call backs, sharing the same capability bit. 390 * Iterate over each entry to see if at least one matches. 391 */ 392 static inline bool 393 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, 394 int scope) 395 { 396 const struct arm64_cpu_capabilities *caps; 397 398 for (caps = entry->match_list; caps->matches; caps++) 399 if (caps->matches(caps, scope)) 400 return true; 401 402 return false; 403 } 404 405 static __always_inline bool is_vhe_hyp_code(void) 406 { 407 /* Only defined for code run in VHE hyp context */ 408 return __is_defined(__KVM_VHE_HYPERVISOR__); 409 } 410 411 static __always_inline bool is_nvhe_hyp_code(void) 412 { 413 /* Only defined for code run in NVHE hyp context */ 414 return __is_defined(__KVM_NVHE_HYPERVISOR__); 415 } 416 417 static __always_inline bool is_hyp_code(void) 418 { 419 return is_vhe_hyp_code() || is_nvhe_hyp_code(); 420 } 421 422 extern DECLARE_BITMAP(system_cpucaps, ARM64_NCAPS); 423 424 extern DECLARE_BITMAP(boot_cpucaps, ARM64_NCAPS); 425 426 #define for_each_available_cap(cap) \ 427 for_each_set_bit(cap, system_cpucaps, ARM64_NCAPS) 428 429 bool this_cpu_has_cap(unsigned int cap); 430 void cpu_set_feature(unsigned int num); 431 bool cpu_have_feature(unsigned int num); 432 unsigned long cpu_get_elf_hwcap(void); 433 unsigned long cpu_get_elf_hwcap2(void); 434 435 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name)) 436 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name)) 437 438 static __always_inline bool system_capabilities_finalized(void) 439 { 440 return alternative_has_cap_likely(ARM64_ALWAYS_SYSTEM); 441 } 442 443 /* 444 * Test for a capability with a runtime check. 445 * 446 * Before the capability is detected, this returns false. 447 */ 448 static __always_inline bool cpus_have_cap(unsigned int num) 449 { 450 if (num >= ARM64_NCAPS) 451 return false; 452 return arch_test_bit(num, system_cpucaps); 453 } 454 455 /* 456 * Test for a capability without a runtime check. 457 * 458 * Before capabilities are finalized, this returns false. 459 * After capabilities are finalized, this is patched to avoid a runtime check. 460 * 461 * @num must be a compile-time constant. 462 */ 463 static __always_inline bool __cpus_have_const_cap(int num) 464 { 465 if (num >= ARM64_NCAPS) 466 return false; 467 return alternative_has_cap_unlikely(num); 468 } 469 470 /* 471 * Test for a capability without a runtime check. 472 * 473 * Before capabilities are finalized, this will BUG(). 474 * After capabilities are finalized, this is patched to avoid a runtime check. 475 * 476 * @num must be a compile-time constant. 477 */ 478 static __always_inline bool cpus_have_final_cap(int num) 479 { 480 if (system_capabilities_finalized()) 481 return __cpus_have_const_cap(num); 482 else 483 BUG(); 484 } 485 486 /* 487 * Test for a capability, possibly with a runtime check for non-hyp code. 488 * 489 * For hyp code, this behaves the same as cpus_have_final_cap(). 490 * 491 * For non-hyp code: 492 * Before capabilities are finalized, this behaves as cpus_have_cap(). 493 * After capabilities are finalized, this is patched to avoid a runtime check. 494 * 495 * @num must be a compile-time constant. 496 */ 497 static __always_inline bool cpus_have_const_cap(int num) 498 { 499 if (is_hyp_code()) 500 return cpus_have_final_cap(num); 501 else if (system_capabilities_finalized()) 502 return __cpus_have_const_cap(num); 503 else 504 return cpus_have_cap(num); 505 } 506 507 static inline int __attribute_const__ 508 cpuid_feature_extract_signed_field_width(u64 features, int field, int width) 509 { 510 return (s64)(features << (64 - width - field)) >> (64 - width); 511 } 512 513 static inline int __attribute_const__ 514 cpuid_feature_extract_signed_field(u64 features, int field) 515 { 516 return cpuid_feature_extract_signed_field_width(features, field, 4); 517 } 518 519 static __always_inline unsigned int __attribute_const__ 520 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width) 521 { 522 return (u64)(features << (64 - width - field)) >> (64 - width); 523 } 524 525 static __always_inline unsigned int __attribute_const__ 526 cpuid_feature_extract_unsigned_field(u64 features, int field) 527 { 528 return cpuid_feature_extract_unsigned_field_width(features, field, 4); 529 } 530 531 /* 532 * Fields that identify the version of the Performance Monitors Extension do 533 * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825, 534 * "Alternative ID scheme used for the Performance Monitors Extension version". 535 */ 536 static inline u64 __attribute_const__ 537 cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap) 538 { 539 u64 val = cpuid_feature_extract_unsigned_field(features, field); 540 u64 mask = GENMASK_ULL(field + 3, field); 541 542 /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */ 543 if (val == ID_AA64DFR0_EL1_PMUVer_IMP_DEF) 544 val = 0; 545 546 if (val > cap) { 547 features &= ~mask; 548 features |= (cap << field) & mask; 549 } 550 551 return features; 552 } 553 554 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp) 555 { 556 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift); 557 } 558 559 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg) 560 { 561 return (reg->user_val | (reg->sys_val & reg->user_mask)); 562 } 563 564 static inline int __attribute_const__ 565 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign) 566 { 567 if (WARN_ON_ONCE(!width)) 568 width = 4; 569 return (sign) ? 570 cpuid_feature_extract_signed_field_width(features, field, width) : 571 cpuid_feature_extract_unsigned_field_width(features, field, width); 572 } 573 574 static inline int __attribute_const__ 575 cpuid_feature_extract_field(u64 features, int field, bool sign) 576 { 577 return cpuid_feature_extract_field_width(features, field, 4, sign); 578 } 579 580 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val) 581 { 582 return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign); 583 } 584 585 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0) 586 { 587 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGEND_SHIFT) == 0x1 || 588 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT) == 0x1; 589 } 590 591 static inline bool id_aa64pfr0_32bit_el1(u64 pfr0) 592 { 593 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL1_SHIFT); 594 595 return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT; 596 } 597 598 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0) 599 { 600 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_EL0_SHIFT); 601 602 return val == ID_AA64PFR0_EL1_ELx_32BIT_64BIT; 603 } 604 605 static inline bool id_aa64pfr0_sve(u64 pfr0) 606 { 607 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SVE_SHIFT); 608 609 return val > 0; 610 } 611 612 static inline bool id_aa64pfr1_sme(u64 pfr1) 613 { 614 u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_SME_SHIFT); 615 616 return val > 0; 617 } 618 619 static inline bool id_aa64pfr1_mte(u64 pfr1) 620 { 621 u32 val = cpuid_feature_extract_unsigned_field(pfr1, ID_AA64PFR1_EL1_MTE_SHIFT); 622 623 return val >= ID_AA64PFR1_EL1_MTE_MTE2; 624 } 625 626 void __init setup_cpu_features(void); 627 void check_local_cpu_capabilities(void); 628 629 u64 read_sanitised_ftr_reg(u32 id); 630 u64 __read_sysreg_by_encoding(u32 sys_id); 631 632 static inline bool cpu_supports_mixed_endian_el0(void) 633 { 634 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); 635 } 636 637 638 static inline bool supports_csv2p3(int scope) 639 { 640 u64 pfr0; 641 u8 csv2_val; 642 643 if (scope == SCOPE_LOCAL_CPU) 644 pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1); 645 else 646 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 647 648 csv2_val = cpuid_feature_extract_unsigned_field(pfr0, 649 ID_AA64PFR0_EL1_CSV2_SHIFT); 650 return csv2_val == 3; 651 } 652 653 static inline bool supports_clearbhb(int scope) 654 { 655 u64 isar2; 656 657 if (scope == SCOPE_LOCAL_CPU) 658 isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1); 659 else 660 isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1); 661 662 return cpuid_feature_extract_unsigned_field(isar2, 663 ID_AA64ISAR2_EL1_BC_SHIFT); 664 } 665 666 const struct cpumask *system_32bit_el0_cpumask(void); 667 DECLARE_STATIC_KEY_FALSE(arm64_mismatched_32bit_el0); 668 669 static inline bool system_supports_32bit_el0(void) 670 { 671 u64 pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1); 672 673 return static_branch_unlikely(&arm64_mismatched_32bit_el0) || 674 id_aa64pfr0_32bit_el0(pfr0); 675 } 676 677 static inline bool system_supports_4kb_granule(void) 678 { 679 u64 mmfr0; 680 u32 val; 681 682 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 683 val = cpuid_feature_extract_unsigned_field(mmfr0, 684 ID_AA64MMFR0_EL1_TGRAN4_SHIFT); 685 686 return (val >= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN) && 687 (val <= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX); 688 } 689 690 static inline bool system_supports_64kb_granule(void) 691 { 692 u64 mmfr0; 693 u32 val; 694 695 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 696 val = cpuid_feature_extract_unsigned_field(mmfr0, 697 ID_AA64MMFR0_EL1_TGRAN64_SHIFT); 698 699 return (val >= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN) && 700 (val <= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX); 701 } 702 703 static inline bool system_supports_16kb_granule(void) 704 { 705 u64 mmfr0; 706 u32 val; 707 708 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 709 val = cpuid_feature_extract_unsigned_field(mmfr0, 710 ID_AA64MMFR0_EL1_TGRAN16_SHIFT); 711 712 return (val >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN) && 713 (val <= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX); 714 } 715 716 static inline bool system_supports_mixed_endian_el0(void) 717 { 718 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1)); 719 } 720 721 static inline bool system_supports_mixed_endian(void) 722 { 723 u64 mmfr0; 724 u32 val; 725 726 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 727 val = cpuid_feature_extract_unsigned_field(mmfr0, 728 ID_AA64MMFR0_EL1_BIGEND_SHIFT); 729 730 return val == 0x1; 731 } 732 733 static __always_inline bool system_supports_fpsimd(void) 734 { 735 return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD); 736 } 737 738 static inline bool system_uses_hw_pan(void) 739 { 740 return IS_ENABLED(CONFIG_ARM64_PAN) && 741 cpus_have_const_cap(ARM64_HAS_PAN); 742 } 743 744 static inline bool system_uses_ttbr0_pan(void) 745 { 746 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) && 747 !system_uses_hw_pan(); 748 } 749 750 static __always_inline bool system_supports_sve(void) 751 { 752 return IS_ENABLED(CONFIG_ARM64_SVE) && 753 cpus_have_const_cap(ARM64_SVE); 754 } 755 756 static __always_inline bool system_supports_sme(void) 757 { 758 return IS_ENABLED(CONFIG_ARM64_SME) && 759 cpus_have_const_cap(ARM64_SME); 760 } 761 762 static __always_inline bool system_supports_sme2(void) 763 { 764 return IS_ENABLED(CONFIG_ARM64_SME) && 765 cpus_have_const_cap(ARM64_SME2); 766 } 767 768 static __always_inline bool system_supports_fa64(void) 769 { 770 return IS_ENABLED(CONFIG_ARM64_SME) && 771 cpus_have_const_cap(ARM64_SME_FA64); 772 } 773 774 static __always_inline bool system_supports_tpidr2(void) 775 { 776 return system_supports_sme(); 777 } 778 779 static __always_inline bool system_supports_cnp(void) 780 { 781 return IS_ENABLED(CONFIG_ARM64_CNP) && 782 cpus_have_const_cap(ARM64_HAS_CNP); 783 } 784 785 static inline bool system_supports_address_auth(void) 786 { 787 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) && 788 cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH); 789 } 790 791 static inline bool system_supports_generic_auth(void) 792 { 793 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) && 794 cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH); 795 } 796 797 static inline bool system_has_full_ptr_auth(void) 798 { 799 return system_supports_address_auth() && system_supports_generic_auth(); 800 } 801 802 static __always_inline bool system_uses_irq_prio_masking(void) 803 { 804 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 805 cpus_have_const_cap(ARM64_HAS_GIC_PRIO_MASKING); 806 } 807 808 static inline bool system_supports_mte(void) 809 { 810 return IS_ENABLED(CONFIG_ARM64_MTE) && 811 cpus_have_const_cap(ARM64_MTE); 812 } 813 814 static inline bool system_has_prio_mask_debugging(void) 815 { 816 return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) && 817 system_uses_irq_prio_masking(); 818 } 819 820 static inline bool system_supports_bti(void) 821 { 822 return IS_ENABLED(CONFIG_ARM64_BTI) && cpus_have_const_cap(ARM64_BTI); 823 } 824 825 static inline bool system_supports_tlb_range(void) 826 { 827 return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) && 828 cpus_have_const_cap(ARM64_HAS_TLB_RANGE); 829 } 830 831 int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); 832 bool try_emulate_mrs(struct pt_regs *regs, u32 isn); 833 834 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) 835 { 836 switch (parange) { 837 case ID_AA64MMFR0_EL1_PARANGE_32: return 32; 838 case ID_AA64MMFR0_EL1_PARANGE_36: return 36; 839 case ID_AA64MMFR0_EL1_PARANGE_40: return 40; 840 case ID_AA64MMFR0_EL1_PARANGE_42: return 42; 841 case ID_AA64MMFR0_EL1_PARANGE_44: return 44; 842 case ID_AA64MMFR0_EL1_PARANGE_48: return 48; 843 case ID_AA64MMFR0_EL1_PARANGE_52: return 52; 844 /* 845 * A future PE could use a value unknown to the kernel. 846 * However, by the "D10.1.4 Principles of the ID scheme 847 * for fields in ID registers", ARM DDI 0487C.a, any new 848 * value is guaranteed to be higher than what we know already. 849 * As a safe limit, we return the limit supported by the kernel. 850 */ 851 default: return CONFIG_ARM64_PA_BITS; 852 } 853 } 854 855 /* Check whether hardware update of the Access flag is supported */ 856 static inline bool cpu_has_hw_af(void) 857 { 858 u64 mmfr1; 859 860 if (!IS_ENABLED(CONFIG_ARM64_HW_AFDBM)) 861 return false; 862 863 /* 864 * Use cached version to avoid emulated msr operation on KVM 865 * guests. 866 */ 867 mmfr1 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1); 868 return cpuid_feature_extract_unsigned_field(mmfr1, 869 ID_AA64MMFR1_EL1_HAFDBS_SHIFT); 870 } 871 872 static inline bool cpu_has_pan(void) 873 { 874 u64 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 875 return cpuid_feature_extract_unsigned_field(mmfr1, 876 ID_AA64MMFR1_EL1_PAN_SHIFT); 877 } 878 879 #ifdef CONFIG_ARM64_AMU_EXTN 880 /* Check whether the cpu supports the Activity Monitors Unit (AMU) */ 881 extern bool cpu_has_amu_feat(int cpu); 882 #else 883 static inline bool cpu_has_amu_feat(int cpu) 884 { 885 return false; 886 } 887 #endif 888 889 /* Get a cpu that supports the Activity Monitors Unit (AMU) */ 890 extern int get_cpu_with_amu_feat(void); 891 892 static inline unsigned int get_vmid_bits(u64 mmfr1) 893 { 894 int vmid_bits; 895 896 vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1, 897 ID_AA64MMFR1_EL1_VMIDBits_SHIFT); 898 if (vmid_bits == ID_AA64MMFR1_EL1_VMIDBits_16) 899 return 16; 900 901 /* 902 * Return the default here even if any reserved 903 * value is fetched from the system register. 904 */ 905 return 8; 906 } 907 908 struct arm64_ftr_reg *get_arm64_ftr_reg(u32 sys_id); 909 910 extern struct arm64_ftr_override id_aa64mmfr1_override; 911 extern struct arm64_ftr_override id_aa64pfr0_override; 912 extern struct arm64_ftr_override id_aa64pfr1_override; 913 extern struct arm64_ftr_override id_aa64zfr0_override; 914 extern struct arm64_ftr_override id_aa64smfr0_override; 915 extern struct arm64_ftr_override id_aa64isar1_override; 916 extern struct arm64_ftr_override id_aa64isar2_override; 917 918 u32 get_kvm_ipa_limit(void); 919 void dump_cpu_features(void); 920 921 #endif /* __ASSEMBLY__ */ 922 923 #endif 924