1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org> 4 */ 5 6 #ifndef __ASM_CPUFEATURE_H 7 #define __ASM_CPUFEATURE_H 8 9 #include <asm/cpucaps.h> 10 #include <asm/cputype.h> 11 #include <asm/hwcap.h> 12 #include <asm/sysreg.h> 13 14 #define MAX_CPU_FEATURES 64 15 #define cpu_feature(x) KERNEL_HWCAP_ ## x 16 17 #ifndef __ASSEMBLY__ 18 19 #include <linux/bug.h> 20 #include <linux/jump_label.h> 21 #include <linux/kernel.h> 22 23 /* 24 * CPU feature register tracking 25 * 26 * The safe value of a CPUID feature field is dependent on the implications 27 * of the values assigned to it by the architecture. Based on the relationship 28 * between the values, the features are classified into 3 types - LOWER_SAFE, 29 * HIGHER_SAFE and EXACT. 30 * 31 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest 32 * for HIGHER_SAFE. It is expected that all CPUs have the same value for 33 * a field when EXACT is specified, failing which, the safe value specified 34 * in the table is chosen. 35 */ 36 37 enum ftr_type { 38 FTR_EXACT, /* Use a predefined safe value */ 39 FTR_LOWER_SAFE, /* Smaller value is safe */ 40 FTR_HIGHER_SAFE, /* Bigger value is safe */ 41 FTR_HIGHER_OR_ZERO_SAFE, /* Bigger value is safe, but 0 is biggest */ 42 }; 43 44 #define FTR_STRICT true /* SANITY check strict matching required */ 45 #define FTR_NONSTRICT false /* SANITY check ignored */ 46 47 #define FTR_SIGNED true /* Value should be treated as signed */ 48 #define FTR_UNSIGNED false /* Value should be treated as unsigned */ 49 50 #define FTR_VISIBLE true /* Feature visible to the user space */ 51 #define FTR_HIDDEN false /* Feature is hidden from the user */ 52 53 #define FTR_VISIBLE_IF_IS_ENABLED(config) \ 54 (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN) 55 56 struct arm64_ftr_bits { 57 bool sign; /* Value is signed ? */ 58 bool visible; 59 bool strict; /* CPU Sanity check: strict matching required ? */ 60 enum ftr_type type; 61 u8 shift; 62 u8 width; 63 s64 safe_val; /* safe value for FTR_EXACT features */ 64 }; 65 66 /* 67 * @arm64_ftr_reg - Feature register 68 * @strict_mask Bits which should match across all CPUs for sanity. 69 * @sys_val Safe value across the CPUs (system view) 70 */ 71 struct arm64_ftr_reg { 72 const char *name; 73 u64 strict_mask; 74 u64 user_mask; 75 u64 sys_val; 76 u64 user_val; 77 const struct arm64_ftr_bits *ftr_bits; 78 }; 79 80 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; 81 82 /* 83 * CPU capabilities: 84 * 85 * We use arm64_cpu_capabilities to represent system features, errata work 86 * arounds (both used internally by kernel and tracked in cpu_hwcaps) and 87 * ELF HWCAPs (which are exposed to user). 88 * 89 * To support systems with heterogeneous CPUs, we need to make sure that we 90 * detect the capabilities correctly on the system and take appropriate 91 * measures to ensure there are no incompatibilities. 92 * 93 * This comment tries to explain how we treat the capabilities. 94 * Each capability has the following list of attributes : 95 * 96 * 1) Scope of Detection : The system detects a given capability by 97 * performing some checks at runtime. This could be, e.g, checking the 98 * value of a field in CPU ID feature register or checking the cpu 99 * model. The capability provides a call back ( @matches() ) to 100 * perform the check. Scope defines how the checks should be performed. 101 * There are three cases: 102 * 103 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one 104 * matches. This implies, we have to run the check on all the 105 * booting CPUs, until the system decides that state of the 106 * capability is finalised. (See section 2 below) 107 * Or 108 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs 109 * matches. This implies, we run the check only once, when the 110 * system decides to finalise the state of the capability. If the 111 * capability relies on a field in one of the CPU ID feature 112 * registers, we use the sanitised value of the register from the 113 * CPU feature infrastructure to make the decision. 114 * Or 115 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the 116 * feature. This category is for features that are "finalised" 117 * (or used) by the kernel very early even before the SMP cpus 118 * are brought up. 119 * 120 * The process of detection is usually denoted by "update" capability 121 * state in the code. 122 * 123 * 2) Finalise the state : The kernel should finalise the state of a 124 * capability at some point during its execution and take necessary 125 * actions if any. Usually, this is done, after all the boot-time 126 * enabled CPUs are brought up by the kernel, so that it can make 127 * better decision based on the available set of CPUs. However, there 128 * are some special cases, where the action is taken during the early 129 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with 130 * Virtualisation Host Extensions). The kernel usually disallows any 131 * changes to the state of a capability once it finalises the capability 132 * and takes any action, as it may be impossible to execute the actions 133 * safely. A CPU brought up after a capability is "finalised" is 134 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary 135 * CPUs are treated "late CPUs" for capabilities determined by the boot 136 * CPU. 137 * 138 * At the moment there are two passes of finalising the capabilities. 139 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via 140 * setup_boot_cpu_capabilities(). 141 * b) Everything except (a) - Run via setup_system_capabilities(). 142 * 143 * 3) Verification: When a CPU is brought online (e.g, by user or by the 144 * kernel), the kernel should make sure that it is safe to use the CPU, 145 * by verifying that the CPU is compliant with the state of the 146 * capabilities finalised already. This happens via : 147 * 148 * secondary_start_kernel()-> check_local_cpu_capabilities() 149 * 150 * As explained in (2) above, capabilities could be finalised at 151 * different points in the execution. Each newly booted CPU is verified 152 * against the capabilities that have been finalised by the time it 153 * boots. 154 * 155 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability 156 * except for the primary boot CPU. 157 * 158 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the 159 * user after the kernel boot are verified against the capability. 160 * 161 * If there is a conflict, the kernel takes an action, based on the 162 * severity (e.g, a CPU could be prevented from booting or cause a 163 * kernel panic). The CPU is allowed to "affect" the state of the 164 * capability, if it has not been finalised already. See section 5 165 * for more details on conflicts. 166 * 167 * 4) Action: As mentioned in (2), the kernel can take an action for each 168 * detected capability, on all CPUs on the system. Appropriate actions 169 * include, turning on an architectural feature, modifying the control 170 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via 171 * alternatives. The kernel patching is batched and performed at later 172 * point. The actions are always initiated only after the capability 173 * is finalised. This is usally denoted by "enabling" the capability. 174 * The actions are initiated as follows : 175 * a) Action is triggered on all online CPUs, after the capability is 176 * finalised, invoked within the stop_machine() context from 177 * enable_cpu_capabilitie(). 178 * 179 * b) Any late CPU, brought up after (1), the action is triggered via: 180 * 181 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities() 182 * 183 * 5) Conflicts: Based on the state of the capability on a late CPU vs. 184 * the system state, we could have the following combinations : 185 * 186 * x-----------------------------x 187 * | Type | System | Late CPU | 188 * |-----------------------------| 189 * | a | y | n | 190 * |-----------------------------| 191 * | b | n | y | 192 * x-----------------------------x 193 * 194 * Two separate flag bits are defined to indicate whether each kind of 195 * conflict can be allowed: 196 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed 197 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed 198 * 199 * Case (a) is not permitted for a capability that the system requires 200 * all CPUs to have in order for the capability to be enabled. This is 201 * typical for capabilities that represent enhanced functionality. 202 * 203 * Case (b) is not permitted for a capability that must be enabled 204 * during boot if any CPU in the system requires it in order to run 205 * safely. This is typical for erratum work arounds that cannot be 206 * enabled after the corresponding capability is finalised. 207 * 208 * In some non-typical cases either both (a) and (b), or neither, 209 * should be permitted. This can be described by including neither 210 * or both flags in the capability's type field. 211 * 212 * In case of a conflict, the CPU is prevented from booting. If the 213 * ARM64_CPUCAP_PANIC_ON_CONFLICT flag is specified for the capability, 214 * then a kernel panic is triggered. 215 */ 216 217 218 /* 219 * Decide how the capability is detected. 220 * On any local CPU vs System wide vs the primary boot CPU 221 */ 222 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0)) 223 #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1)) 224 /* 225 * The capabilitiy is detected on the Boot CPU and is used by kernel 226 * during early boot. i.e, the capability should be "detected" and 227 * "enabled" as early as possibly on all booting CPUs. 228 */ 229 #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2)) 230 #define ARM64_CPUCAP_SCOPE_MASK \ 231 (ARM64_CPUCAP_SCOPE_SYSTEM | \ 232 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 233 ARM64_CPUCAP_SCOPE_BOOT_CPU) 234 235 #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM 236 #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU 237 #define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU 238 #define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK 239 240 /* 241 * Is it permitted for a late CPU to have this capability when system 242 * hasn't already enabled it ? 243 */ 244 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4)) 245 /* Is it safe for a late CPU to miss this capability when system has it */ 246 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5)) 247 /* Panic when a conflict is detected */ 248 #define ARM64_CPUCAP_PANIC_ON_CONFLICT ((u16)BIT(6)) 249 250 /* 251 * CPU errata workarounds that need to be enabled at boot time if one or 252 * more CPUs in the system requires it. When one of these capabilities 253 * has been enabled, it is safe to allow any CPU to boot that doesn't 254 * require the workaround. However, it is not safe if a "late" CPU 255 * requires a workaround and the system hasn't enabled it already. 256 */ 257 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \ 258 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU) 259 /* 260 * CPU feature detected at boot time based on system-wide value of a 261 * feature. It is safe for a late CPU to have this feature even though 262 * the system hasn't enabled it, although the feature will not be used 263 * by Linux in this case. If the system has enabled this feature already, 264 * then every late CPU must have it. 265 */ 266 #define ARM64_CPUCAP_SYSTEM_FEATURE \ 267 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 268 /* 269 * CPU feature detected at boot time based on feature of one or more CPUs. 270 * All possible conflicts for a late CPU are ignored. 271 */ 272 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \ 273 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 274 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \ 275 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 276 277 /* 278 * CPU feature detected at boot time, on one or more CPUs. A late CPU 279 * is not allowed to have the capability when the system doesn't have it. 280 * It is Ok for a late CPU to miss the feature. 281 */ 282 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \ 283 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 284 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU) 285 286 /* 287 * CPU feature used early in the boot based on the boot CPU. All secondary 288 * CPUs must match the state of the capability as detected by the boot CPU. In 289 * case of a conflict, a kernel panic is triggered. 290 */ 291 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE \ 292 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PANIC_ON_CONFLICT) 293 294 /* 295 * CPU feature used early in the boot based on the boot CPU. It is safe for a 296 * late CPU to have this feature even though the boot CPU hasn't enabled it, 297 * although the feature will not be used by Linux in this case. If the boot CPU 298 * has enabled this feature already, then every late CPU must have it. 299 */ 300 #define ARM64_CPUCAP_BOOT_CPU_FEATURE \ 301 (ARM64_CPUCAP_SCOPE_BOOT_CPU | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 302 303 struct arm64_cpu_capabilities { 304 const char *desc; 305 u16 capability; 306 u16 type; 307 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); 308 /* 309 * Take the appropriate actions to configure this capability 310 * for this CPU. If the capability is detected by the kernel 311 * this will be called on all the CPUs in the system, 312 * including the hotplugged CPUs, regardless of whether the 313 * capability is available on that specific CPU. This is 314 * useful for some capabilities (e.g, working around CPU 315 * errata), where all the CPUs must take some action (e.g, 316 * changing system control/configuration). Thus, if an action 317 * is required only if the CPU has the capability, then the 318 * routine must check it before taking any action. 319 */ 320 void (*cpu_enable)(const struct arm64_cpu_capabilities *cap); 321 union { 322 struct { /* To be used for erratum handling only */ 323 struct midr_range midr_range; 324 const struct arm64_midr_revidr { 325 u32 midr_rv; /* revision/variant */ 326 u32 revidr_mask; 327 } * const fixed_revs; 328 }; 329 330 const struct midr_range *midr_range_list; 331 struct { /* Feature register checking */ 332 u32 sys_reg; 333 u8 field_pos; 334 u8 min_field_value; 335 u8 hwcap_type; 336 bool sign; 337 unsigned long hwcap; 338 }; 339 }; 340 341 /* 342 * An optional list of "matches/cpu_enable" pair for the same 343 * "capability" of the same "type" as described by the parent. 344 * Only matches(), cpu_enable() and fields relevant to these 345 * methods are significant in the list. The cpu_enable is 346 * invoked only if the corresponding entry "matches()". 347 * However, if a cpu_enable() method is associated 348 * with multiple matches(), care should be taken that either 349 * the match criteria are mutually exclusive, or that the 350 * method is robust against being called multiple times. 351 */ 352 const struct arm64_cpu_capabilities *match_list; 353 }; 354 355 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap) 356 { 357 return cap->type & ARM64_CPUCAP_SCOPE_MASK; 358 } 359 360 /* 361 * Generic helper for handling capabilties with multiple (match,enable) pairs 362 * of call backs, sharing the same capability bit. 363 * Iterate over each entry to see if at least one matches. 364 */ 365 static inline bool 366 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, 367 int scope) 368 { 369 const struct arm64_cpu_capabilities *caps; 370 371 for (caps = entry->match_list; caps->matches; caps++) 372 if (caps->matches(caps, scope)) 373 return true; 374 375 return false; 376 } 377 378 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 379 extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS]; 380 extern struct static_key_false arm64_const_caps_ready; 381 382 /* ARM64 CAPS + alternative_cb */ 383 #define ARM64_NPATCHABLE (ARM64_NCAPS + 1) 384 extern DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 385 386 #define for_each_available_cap(cap) \ 387 for_each_set_bit(cap, cpu_hwcaps, ARM64_NCAPS) 388 389 bool this_cpu_has_cap(unsigned int cap); 390 void cpu_set_feature(unsigned int num); 391 bool cpu_have_feature(unsigned int num); 392 unsigned long cpu_get_elf_hwcap(void); 393 unsigned long cpu_get_elf_hwcap2(void); 394 395 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name)) 396 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name)) 397 398 static __always_inline bool system_capabilities_finalized(void) 399 { 400 return static_branch_likely(&arm64_const_caps_ready); 401 } 402 403 /* 404 * Test for a capability with a runtime check. 405 * 406 * Before the capability is detected, this returns false. 407 */ 408 static inline bool cpus_have_cap(unsigned int num) 409 { 410 if (num >= ARM64_NCAPS) 411 return false; 412 return test_bit(num, cpu_hwcaps); 413 } 414 415 /* 416 * Test for a capability without a runtime check. 417 * 418 * Before capabilities are finalized, this returns false. 419 * After capabilities are finalized, this is patched to avoid a runtime check. 420 * 421 * @num must be a compile-time constant. 422 */ 423 static __always_inline bool __cpus_have_const_cap(int num) 424 { 425 if (num >= ARM64_NCAPS) 426 return false; 427 return static_branch_unlikely(&cpu_hwcap_keys[num]); 428 } 429 430 /* 431 * Test for a capability, possibly with a runtime check. 432 * 433 * Before capabilities are finalized, this behaves as cpus_have_cap(). 434 * After capabilities are finalized, this is patched to avoid a runtime check. 435 * 436 * @num must be a compile-time constant. 437 */ 438 static __always_inline bool cpus_have_const_cap(int num) 439 { 440 if (system_capabilities_finalized()) 441 return __cpus_have_const_cap(num); 442 else 443 return cpus_have_cap(num); 444 } 445 446 /* 447 * Test for a capability without a runtime check. 448 * 449 * Before capabilities are finalized, this will BUG(). 450 * After capabilities are finalized, this is patched to avoid a runtime check. 451 * 452 * @num must be a compile-time constant. 453 */ 454 static __always_inline bool cpus_have_final_cap(int num) 455 { 456 if (system_capabilities_finalized()) 457 return __cpus_have_const_cap(num); 458 else 459 BUG(); 460 } 461 462 static inline void cpus_set_cap(unsigned int num) 463 { 464 if (num >= ARM64_NCAPS) { 465 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n", 466 num, ARM64_NCAPS); 467 } else { 468 __set_bit(num, cpu_hwcaps); 469 } 470 } 471 472 static inline int __attribute_const__ 473 cpuid_feature_extract_signed_field_width(u64 features, int field, int width) 474 { 475 return (s64)(features << (64 - width - field)) >> (64 - width); 476 } 477 478 static inline int __attribute_const__ 479 cpuid_feature_extract_signed_field(u64 features, int field) 480 { 481 return cpuid_feature_extract_signed_field_width(features, field, 4); 482 } 483 484 static __always_inline unsigned int __attribute_const__ 485 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width) 486 { 487 return (u64)(features << (64 - width - field)) >> (64 - width); 488 } 489 490 static __always_inline unsigned int __attribute_const__ 491 cpuid_feature_extract_unsigned_field(u64 features, int field) 492 { 493 return cpuid_feature_extract_unsigned_field_width(features, field, 4); 494 } 495 496 /* 497 * Fields that identify the version of the Performance Monitors Extension do 498 * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825, 499 * "Alternative ID scheme used for the Performance Monitors Extension version". 500 */ 501 static inline u64 __attribute_const__ 502 cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap) 503 { 504 u64 val = cpuid_feature_extract_unsigned_field(features, field); 505 u64 mask = GENMASK_ULL(field + 3, field); 506 507 /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */ 508 if (val == 0xf) 509 val = 0; 510 511 if (val > cap) { 512 features &= ~mask; 513 features |= (cap << field) & mask; 514 } 515 516 return features; 517 } 518 519 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp) 520 { 521 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift); 522 } 523 524 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg) 525 { 526 return (reg->user_val | (reg->sys_val & reg->user_mask)); 527 } 528 529 static inline int __attribute_const__ 530 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign) 531 { 532 return (sign) ? 533 cpuid_feature_extract_signed_field_width(features, field, width) : 534 cpuid_feature_extract_unsigned_field_width(features, field, width); 535 } 536 537 static inline int __attribute_const__ 538 cpuid_feature_extract_field(u64 features, int field, bool sign) 539 { 540 return cpuid_feature_extract_field_width(features, field, 4, sign); 541 } 542 543 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val) 544 { 545 return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign); 546 } 547 548 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0) 549 { 550 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 || 551 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1; 552 } 553 554 static inline bool id_aa64pfr0_32bit_el1(u64 pfr0) 555 { 556 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL1_SHIFT); 557 558 return val == ID_AA64PFR0_EL1_32BIT_64BIT; 559 } 560 561 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0) 562 { 563 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT); 564 565 return val == ID_AA64PFR0_EL0_32BIT_64BIT; 566 } 567 568 static inline bool id_aa64pfr0_sve(u64 pfr0) 569 { 570 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT); 571 572 return val > 0; 573 } 574 575 void __init setup_cpu_features(void); 576 void check_local_cpu_capabilities(void); 577 578 u64 read_sanitised_ftr_reg(u32 id); 579 580 static inline bool cpu_supports_mixed_endian_el0(void) 581 { 582 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); 583 } 584 585 static inline bool system_supports_32bit_el0(void) 586 { 587 return cpus_have_const_cap(ARM64_HAS_32BIT_EL0); 588 } 589 590 static inline bool system_supports_4kb_granule(void) 591 { 592 u64 mmfr0; 593 u32 val; 594 595 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 596 val = cpuid_feature_extract_unsigned_field(mmfr0, 597 ID_AA64MMFR0_TGRAN4_SHIFT); 598 599 return val == ID_AA64MMFR0_TGRAN4_SUPPORTED; 600 } 601 602 static inline bool system_supports_64kb_granule(void) 603 { 604 u64 mmfr0; 605 u32 val; 606 607 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 608 val = cpuid_feature_extract_unsigned_field(mmfr0, 609 ID_AA64MMFR0_TGRAN64_SHIFT); 610 611 return val == ID_AA64MMFR0_TGRAN64_SUPPORTED; 612 } 613 614 static inline bool system_supports_16kb_granule(void) 615 { 616 u64 mmfr0; 617 u32 val; 618 619 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 620 val = cpuid_feature_extract_unsigned_field(mmfr0, 621 ID_AA64MMFR0_TGRAN16_SHIFT); 622 623 return val == ID_AA64MMFR0_TGRAN16_SUPPORTED; 624 } 625 626 static inline bool system_supports_mixed_endian_el0(void) 627 { 628 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1)); 629 } 630 631 static inline bool system_supports_mixed_endian(void) 632 { 633 u64 mmfr0; 634 u32 val; 635 636 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 637 val = cpuid_feature_extract_unsigned_field(mmfr0, 638 ID_AA64MMFR0_BIGENDEL_SHIFT); 639 640 return val == 0x1; 641 } 642 643 static __always_inline bool system_supports_fpsimd(void) 644 { 645 return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD); 646 } 647 648 static inline bool system_uses_ttbr0_pan(void) 649 { 650 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) && 651 !cpus_have_const_cap(ARM64_HAS_PAN); 652 } 653 654 static __always_inline bool system_supports_sve(void) 655 { 656 return IS_ENABLED(CONFIG_ARM64_SVE) && 657 cpus_have_const_cap(ARM64_SVE); 658 } 659 660 static __always_inline bool system_supports_cnp(void) 661 { 662 return IS_ENABLED(CONFIG_ARM64_CNP) && 663 cpus_have_const_cap(ARM64_HAS_CNP); 664 } 665 666 static inline bool system_supports_address_auth(void) 667 { 668 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) && 669 cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH); 670 } 671 672 static inline bool system_supports_generic_auth(void) 673 { 674 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) && 675 cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH); 676 } 677 678 static __always_inline bool system_uses_irq_prio_masking(void) 679 { 680 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 681 cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING); 682 } 683 684 static inline bool system_has_prio_mask_debugging(void) 685 { 686 return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) && 687 system_uses_irq_prio_masking(); 688 } 689 690 static inline bool system_supports_bti(void) 691 { 692 return IS_ENABLED(CONFIG_ARM64_BTI) && cpus_have_const_cap(ARM64_BTI); 693 } 694 695 static inline bool system_supports_tlb_range(void) 696 { 697 return IS_ENABLED(CONFIG_ARM64_TLB_RANGE) && 698 cpus_have_const_cap(ARM64_HAS_TLB_RANGE); 699 } 700 701 #define ARM64_BP_HARDEN_UNKNOWN -1 702 #define ARM64_BP_HARDEN_WA_NEEDED 0 703 #define ARM64_BP_HARDEN_NOT_REQUIRED 1 704 705 int get_spectre_v2_workaround_state(void); 706 707 #define ARM64_SSBD_UNKNOWN -1 708 #define ARM64_SSBD_FORCE_DISABLE 0 709 #define ARM64_SSBD_KERNEL 1 710 #define ARM64_SSBD_FORCE_ENABLE 2 711 #define ARM64_SSBD_MITIGATED 3 712 713 static inline int arm64_get_ssbd_state(void) 714 { 715 #ifdef CONFIG_ARM64_SSBD 716 extern int ssbd_state; 717 return ssbd_state; 718 #else 719 return ARM64_SSBD_UNKNOWN; 720 #endif 721 } 722 723 void arm64_set_ssbd_mitigation(bool state); 724 725 extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); 726 727 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) 728 { 729 switch (parange) { 730 case 0: return 32; 731 case 1: return 36; 732 case 2: return 40; 733 case 3: return 42; 734 case 4: return 44; 735 case 5: return 48; 736 case 6: return 52; 737 /* 738 * A future PE could use a value unknown to the kernel. 739 * However, by the "D10.1.4 Principles of the ID scheme 740 * for fields in ID registers", ARM DDI 0487C.a, any new 741 * value is guaranteed to be higher than what we know already. 742 * As a safe limit, we return the limit supported by the kernel. 743 */ 744 default: return CONFIG_ARM64_PA_BITS; 745 } 746 } 747 748 /* Check whether hardware update of the Access flag is supported */ 749 static inline bool cpu_has_hw_af(void) 750 { 751 u64 mmfr1; 752 753 if (!IS_ENABLED(CONFIG_ARM64_HW_AFDBM)) 754 return false; 755 756 mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 757 return cpuid_feature_extract_unsigned_field(mmfr1, 758 ID_AA64MMFR1_HADBS_SHIFT); 759 } 760 761 #ifdef CONFIG_ARM64_AMU_EXTN 762 /* Check whether the cpu supports the Activity Monitors Unit (AMU) */ 763 extern bool cpu_has_amu_feat(int cpu); 764 #endif 765 766 static inline unsigned int get_vmid_bits(u64 mmfr1) 767 { 768 int vmid_bits; 769 770 vmid_bits = cpuid_feature_extract_unsigned_field(mmfr1, 771 ID_AA64MMFR1_VMIDBITS_SHIFT); 772 if (vmid_bits == ID_AA64MMFR1_VMIDBITS_16) 773 return 16; 774 775 /* 776 * Return the default here even if any reserved 777 * value is fetched from the system register. 778 */ 779 return 8; 780 } 781 782 u32 get_kvm_ipa_limit(void); 783 void dump_cpu_features(void); 784 785 #endif /* __ASSEMBLY__ */ 786 787 #endif 788