1 /* 2 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef __ASM_CPUFEATURE_H 10 #define __ASM_CPUFEATURE_H 11 12 #include <asm/cpucaps.h> 13 #include <asm/cputype.h> 14 #include <asm/hwcap.h> 15 #include <asm/sysreg.h> 16 17 #define MAX_CPU_FEATURES 64 18 #define cpu_feature(x) KERNEL_HWCAP_ ## x 19 20 #ifndef __ASSEMBLY__ 21 22 #include <linux/bug.h> 23 #include <linux/jump_label.h> 24 #include <linux/kernel.h> 25 26 /* 27 * CPU feature register tracking 28 * 29 * The safe value of a CPUID feature field is dependent on the implications 30 * of the values assigned to it by the architecture. Based on the relationship 31 * between the values, the features are classified into 3 types - LOWER_SAFE, 32 * HIGHER_SAFE and EXACT. 33 * 34 * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest 35 * for HIGHER_SAFE. It is expected that all CPUs have the same value for 36 * a field when EXACT is specified, failing which, the safe value specified 37 * in the table is chosen. 38 */ 39 40 enum ftr_type { 41 FTR_EXACT, /* Use a predefined safe value */ 42 FTR_LOWER_SAFE, /* Smaller value is safe */ 43 FTR_HIGHER_SAFE,/* Bigger value is safe */ 44 }; 45 46 #define FTR_STRICT true /* SANITY check strict matching required */ 47 #define FTR_NONSTRICT false /* SANITY check ignored */ 48 49 #define FTR_SIGNED true /* Value should be treated as signed */ 50 #define FTR_UNSIGNED false /* Value should be treated as unsigned */ 51 52 #define FTR_VISIBLE true /* Feature visible to the user space */ 53 #define FTR_HIDDEN false /* Feature is hidden from the user */ 54 55 #define FTR_VISIBLE_IF_IS_ENABLED(config) \ 56 (IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN) 57 58 struct arm64_ftr_bits { 59 bool sign; /* Value is signed ? */ 60 bool visible; 61 bool strict; /* CPU Sanity check: strict matching required ? */ 62 enum ftr_type type; 63 u8 shift; 64 u8 width; 65 s64 safe_val; /* safe value for FTR_EXACT features */ 66 }; 67 68 /* 69 * @arm64_ftr_reg - Feature register 70 * @strict_mask Bits which should match across all CPUs for sanity. 71 * @sys_val Safe value across the CPUs (system view) 72 */ 73 struct arm64_ftr_reg { 74 const char *name; 75 u64 strict_mask; 76 u64 user_mask; 77 u64 sys_val; 78 u64 user_val; 79 const struct arm64_ftr_bits *ftr_bits; 80 }; 81 82 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; 83 84 /* 85 * CPU capabilities: 86 * 87 * We use arm64_cpu_capabilities to represent system features, errata work 88 * arounds (both used internally by kernel and tracked in cpu_hwcaps) and 89 * ELF HWCAPs (which are exposed to user). 90 * 91 * To support systems with heterogeneous CPUs, we need to make sure that we 92 * detect the capabilities correctly on the system and take appropriate 93 * measures to ensure there are no incompatibilities. 94 * 95 * This comment tries to explain how we treat the capabilities. 96 * Each capability has the following list of attributes : 97 * 98 * 1) Scope of Detection : The system detects a given capability by 99 * performing some checks at runtime. This could be, e.g, checking the 100 * value of a field in CPU ID feature register or checking the cpu 101 * model. The capability provides a call back ( @matches() ) to 102 * perform the check. Scope defines how the checks should be performed. 103 * There are three cases: 104 * 105 * a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one 106 * matches. This implies, we have to run the check on all the 107 * booting CPUs, until the system decides that state of the 108 * capability is finalised. (See section 2 below) 109 * Or 110 * b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs 111 * matches. This implies, we run the check only once, when the 112 * system decides to finalise the state of the capability. If the 113 * capability relies on a field in one of the CPU ID feature 114 * registers, we use the sanitised value of the register from the 115 * CPU feature infrastructure to make the decision. 116 * Or 117 * c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the 118 * feature. This category is for features that are "finalised" 119 * (or used) by the kernel very early even before the SMP cpus 120 * are brought up. 121 * 122 * The process of detection is usually denoted by "update" capability 123 * state in the code. 124 * 125 * 2) Finalise the state : The kernel should finalise the state of a 126 * capability at some point during its execution and take necessary 127 * actions if any. Usually, this is done, after all the boot-time 128 * enabled CPUs are brought up by the kernel, so that it can make 129 * better decision based on the available set of CPUs. However, there 130 * are some special cases, where the action is taken during the early 131 * boot by the primary boot CPU. (e.g, running the kernel at EL2 with 132 * Virtualisation Host Extensions). The kernel usually disallows any 133 * changes to the state of a capability once it finalises the capability 134 * and takes any action, as it may be impossible to execute the actions 135 * safely. A CPU brought up after a capability is "finalised" is 136 * referred to as "Late CPU" w.r.t the capability. e.g, all secondary 137 * CPUs are treated "late CPUs" for capabilities determined by the boot 138 * CPU. 139 * 140 * At the moment there are two passes of finalising the capabilities. 141 * a) Boot CPU scope capabilities - Finalised by primary boot CPU via 142 * setup_boot_cpu_capabilities(). 143 * b) Everything except (a) - Run via setup_system_capabilities(). 144 * 145 * 3) Verification: When a CPU is brought online (e.g, by user or by the 146 * kernel), the kernel should make sure that it is safe to use the CPU, 147 * by verifying that the CPU is compliant with the state of the 148 * capabilities finalised already. This happens via : 149 * 150 * secondary_start_kernel()-> check_local_cpu_capabilities() 151 * 152 * As explained in (2) above, capabilities could be finalised at 153 * different points in the execution. Each newly booted CPU is verified 154 * against the capabilities that have been finalised by the time it 155 * boots. 156 * 157 * a) SCOPE_BOOT_CPU : All CPUs are verified against the capability 158 * except for the primary boot CPU. 159 * 160 * b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the 161 * user after the kernel boot are verified against the capability. 162 * 163 * If there is a conflict, the kernel takes an action, based on the 164 * severity (e.g, a CPU could be prevented from booting or cause a 165 * kernel panic). The CPU is allowed to "affect" the state of the 166 * capability, if it has not been finalised already. See section 5 167 * for more details on conflicts. 168 * 169 * 4) Action: As mentioned in (2), the kernel can take an action for each 170 * detected capability, on all CPUs on the system. Appropriate actions 171 * include, turning on an architectural feature, modifying the control 172 * registers (e.g, SCTLR, TCR etc.) or patching the kernel via 173 * alternatives. The kernel patching is batched and performed at later 174 * point. The actions are always initiated only after the capability 175 * is finalised. This is usally denoted by "enabling" the capability. 176 * The actions are initiated as follows : 177 * a) Action is triggered on all online CPUs, after the capability is 178 * finalised, invoked within the stop_machine() context from 179 * enable_cpu_capabilitie(). 180 * 181 * b) Any late CPU, brought up after (1), the action is triggered via: 182 * 183 * check_local_cpu_capabilities() -> verify_local_cpu_capabilities() 184 * 185 * 5) Conflicts: Based on the state of the capability on a late CPU vs. 186 * the system state, we could have the following combinations : 187 * 188 * x-----------------------------x 189 * | Type | System | Late CPU | 190 * |-----------------------------| 191 * | a | y | n | 192 * |-----------------------------| 193 * | b | n | y | 194 * x-----------------------------x 195 * 196 * Two separate flag bits are defined to indicate whether each kind of 197 * conflict can be allowed: 198 * ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed 199 * ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed 200 * 201 * Case (a) is not permitted for a capability that the system requires 202 * all CPUs to have in order for the capability to be enabled. This is 203 * typical for capabilities that represent enhanced functionality. 204 * 205 * Case (b) is not permitted for a capability that must be enabled 206 * during boot if any CPU in the system requires it in order to run 207 * safely. This is typical for erratum work arounds that cannot be 208 * enabled after the corresponding capability is finalised. 209 * 210 * In some non-typical cases either both (a) and (b), or neither, 211 * should be permitted. This can be described by including neither 212 * or both flags in the capability's type field. 213 */ 214 215 216 /* 217 * Decide how the capability is detected. 218 * On any local CPU vs System wide vs the primary boot CPU 219 */ 220 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU ((u16)BIT(0)) 221 #define ARM64_CPUCAP_SCOPE_SYSTEM ((u16)BIT(1)) 222 /* 223 * The capabilitiy is detected on the Boot CPU and is used by kernel 224 * during early boot. i.e, the capability should be "detected" and 225 * "enabled" as early as possibly on all booting CPUs. 226 */ 227 #define ARM64_CPUCAP_SCOPE_BOOT_CPU ((u16)BIT(2)) 228 #define ARM64_CPUCAP_SCOPE_MASK \ 229 (ARM64_CPUCAP_SCOPE_SYSTEM | \ 230 ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 231 ARM64_CPUCAP_SCOPE_BOOT_CPU) 232 233 #define SCOPE_SYSTEM ARM64_CPUCAP_SCOPE_SYSTEM 234 #define SCOPE_LOCAL_CPU ARM64_CPUCAP_SCOPE_LOCAL_CPU 235 #define SCOPE_BOOT_CPU ARM64_CPUCAP_SCOPE_BOOT_CPU 236 #define SCOPE_ALL ARM64_CPUCAP_SCOPE_MASK 237 238 /* 239 * Is it permitted for a late CPU to have this capability when system 240 * hasn't already enabled it ? 241 */ 242 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU ((u16)BIT(4)) 243 /* Is it safe for a late CPU to miss this capability when system has it */ 244 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5)) 245 246 /* 247 * CPU errata workarounds that need to be enabled at boot time if one or 248 * more CPUs in the system requires it. When one of these capabilities 249 * has been enabled, it is safe to allow any CPU to boot that doesn't 250 * require the workaround. However, it is not safe if a "late" CPU 251 * requires a workaround and the system hasn't enabled it already. 252 */ 253 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM \ 254 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU) 255 /* 256 * CPU feature detected at boot time based on system-wide value of a 257 * feature. It is safe for a late CPU to have this feature even though 258 * the system hasn't enabled it, although the feature will not be used 259 * by Linux in this case. If the system has enabled this feature already, 260 * then every late CPU must have it. 261 */ 262 #define ARM64_CPUCAP_SYSTEM_FEATURE \ 263 (ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 264 /* 265 * CPU feature detected at boot time based on feature of one or more CPUs. 266 * All possible conflicts for a late CPU are ignored. 267 */ 268 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE \ 269 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 270 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU | \ 271 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU) 272 273 /* 274 * CPU feature detected at boot time, on one or more CPUs. A late CPU 275 * is not allowed to have the capability when the system doesn't have it. 276 * It is Ok for a late CPU to miss the feature. 277 */ 278 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE \ 279 (ARM64_CPUCAP_SCOPE_LOCAL_CPU | \ 280 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU) 281 282 /* 283 * CPU feature used early in the boot based on the boot CPU. All secondary 284 * CPUs must match the state of the capability as detected by the boot CPU. 285 */ 286 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE ARM64_CPUCAP_SCOPE_BOOT_CPU 287 288 struct arm64_cpu_capabilities { 289 const char *desc; 290 u16 capability; 291 u16 type; 292 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); 293 /* 294 * Take the appropriate actions to enable this capability for this CPU. 295 * For each successfully booted CPU, this method is called for each 296 * globally detected capability. 297 */ 298 void (*cpu_enable)(const struct arm64_cpu_capabilities *cap); 299 union { 300 struct { /* To be used for erratum handling only */ 301 struct midr_range midr_range; 302 const struct arm64_midr_revidr { 303 u32 midr_rv; /* revision/variant */ 304 u32 revidr_mask; 305 } * const fixed_revs; 306 }; 307 308 const struct midr_range *midr_range_list; 309 struct { /* Feature register checking */ 310 u32 sys_reg; 311 u8 field_pos; 312 u8 min_field_value; 313 u8 hwcap_type; 314 bool sign; 315 unsigned long hwcap; 316 }; 317 }; 318 319 /* 320 * An optional list of "matches/cpu_enable" pair for the same 321 * "capability" of the same "type" as described by the parent. 322 * Only matches(), cpu_enable() and fields relevant to these 323 * methods are significant in the list. The cpu_enable is 324 * invoked only if the corresponding entry "matches()". 325 * However, if a cpu_enable() method is associated 326 * with multiple matches(), care should be taken that either 327 * the match criteria are mutually exclusive, or that the 328 * method is robust against being called multiple times. 329 */ 330 const struct arm64_cpu_capabilities *match_list; 331 }; 332 333 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap) 334 { 335 return cap->type & ARM64_CPUCAP_SCOPE_MASK; 336 } 337 338 static inline bool 339 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) 340 { 341 return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU); 342 } 343 344 static inline bool 345 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) 346 { 347 return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); 348 } 349 350 /* 351 * Generic helper for handling capabilties with multiple (match,enable) pairs 352 * of call backs, sharing the same capability bit. 353 * Iterate over each entry to see if at least one matches. 354 */ 355 static inline bool 356 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry, 357 int scope) 358 { 359 const struct arm64_cpu_capabilities *caps; 360 361 for (caps = entry->match_list; caps->matches; caps++) 362 if (caps->matches(caps, scope)) 363 return true; 364 365 return false; 366 } 367 368 /* 369 * Take appropriate action for all matching entries in the shared capability 370 * entry. 371 */ 372 static inline void 373 cpucap_multi_entry_cap_cpu_enable(const struct arm64_cpu_capabilities *entry) 374 { 375 const struct arm64_cpu_capabilities *caps; 376 377 for (caps = entry->match_list; caps->matches; caps++) 378 if (caps->matches(caps, SCOPE_LOCAL_CPU) && 379 caps->cpu_enable) 380 caps->cpu_enable(caps); 381 } 382 383 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 384 extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS]; 385 extern struct static_key_false arm64_const_caps_ready; 386 387 /* ARM64 CAPS + alternative_cb */ 388 #define ARM64_NPATCHABLE (ARM64_NCAPS + 1) 389 extern DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); 390 391 #define for_each_available_cap(cap) \ 392 for_each_set_bit(cap, cpu_hwcaps, ARM64_NCAPS) 393 394 bool this_cpu_has_cap(unsigned int cap); 395 void cpu_set_feature(unsigned int num); 396 bool cpu_have_feature(unsigned int num); 397 unsigned long cpu_get_elf_hwcap(void); 398 unsigned long cpu_get_elf_hwcap2(void); 399 400 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name)) 401 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name)) 402 403 /* System capability check for constant caps */ 404 static __always_inline bool __cpus_have_const_cap(int num) 405 { 406 if (num >= ARM64_NCAPS) 407 return false; 408 return static_branch_unlikely(&cpu_hwcap_keys[num]); 409 } 410 411 static inline bool cpus_have_cap(unsigned int num) 412 { 413 if (num >= ARM64_NCAPS) 414 return false; 415 return test_bit(num, cpu_hwcaps); 416 } 417 418 static __always_inline bool cpus_have_const_cap(int num) 419 { 420 if (static_branch_likely(&arm64_const_caps_ready)) 421 return __cpus_have_const_cap(num); 422 else 423 return cpus_have_cap(num); 424 } 425 426 static inline void cpus_set_cap(unsigned int num) 427 { 428 if (num >= ARM64_NCAPS) { 429 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n", 430 num, ARM64_NCAPS); 431 } else { 432 __set_bit(num, cpu_hwcaps); 433 } 434 } 435 436 static inline int __attribute_const__ 437 cpuid_feature_extract_signed_field_width(u64 features, int field, int width) 438 { 439 return (s64)(features << (64 - width - field)) >> (64 - width); 440 } 441 442 static inline int __attribute_const__ 443 cpuid_feature_extract_signed_field(u64 features, int field) 444 { 445 return cpuid_feature_extract_signed_field_width(features, field, 4); 446 } 447 448 static inline unsigned int __attribute_const__ 449 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width) 450 { 451 return (u64)(features << (64 - width - field)) >> (64 - width); 452 } 453 454 static inline unsigned int __attribute_const__ 455 cpuid_feature_extract_unsigned_field(u64 features, int field) 456 { 457 return cpuid_feature_extract_unsigned_field_width(features, field, 4); 458 } 459 460 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp) 461 { 462 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift); 463 } 464 465 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg) 466 { 467 return (reg->user_val | (reg->sys_val & reg->user_mask)); 468 } 469 470 static inline int __attribute_const__ 471 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign) 472 { 473 return (sign) ? 474 cpuid_feature_extract_signed_field_width(features, field, width) : 475 cpuid_feature_extract_unsigned_field_width(features, field, width); 476 } 477 478 static inline int __attribute_const__ 479 cpuid_feature_extract_field(u64 features, int field, bool sign) 480 { 481 return cpuid_feature_extract_field_width(features, field, 4, sign); 482 } 483 484 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val) 485 { 486 return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign); 487 } 488 489 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0) 490 { 491 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 || 492 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1; 493 } 494 495 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0) 496 { 497 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT); 498 499 return val == ID_AA64PFR0_EL0_32BIT_64BIT; 500 } 501 502 static inline bool id_aa64pfr0_sve(u64 pfr0) 503 { 504 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT); 505 506 return val > 0; 507 } 508 509 void __init setup_cpu_features(void); 510 void check_local_cpu_capabilities(void); 511 512 u64 read_sanitised_ftr_reg(u32 id); 513 514 static inline bool cpu_supports_mixed_endian_el0(void) 515 { 516 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); 517 } 518 519 static inline bool system_supports_32bit_el0(void) 520 { 521 return cpus_have_const_cap(ARM64_HAS_32BIT_EL0); 522 } 523 524 static inline bool system_supports_4kb_granule(void) 525 { 526 u64 mmfr0; 527 u32 val; 528 529 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 530 val = cpuid_feature_extract_unsigned_field(mmfr0, 531 ID_AA64MMFR0_TGRAN4_SHIFT); 532 533 return val == ID_AA64MMFR0_TGRAN4_SUPPORTED; 534 } 535 536 static inline bool system_supports_64kb_granule(void) 537 { 538 u64 mmfr0; 539 u32 val; 540 541 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 542 val = cpuid_feature_extract_unsigned_field(mmfr0, 543 ID_AA64MMFR0_TGRAN64_SHIFT); 544 545 return val == ID_AA64MMFR0_TGRAN64_SUPPORTED; 546 } 547 548 static inline bool system_supports_16kb_granule(void) 549 { 550 u64 mmfr0; 551 u32 val; 552 553 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 554 val = cpuid_feature_extract_unsigned_field(mmfr0, 555 ID_AA64MMFR0_TGRAN16_SHIFT); 556 557 return val == ID_AA64MMFR0_TGRAN16_SUPPORTED; 558 } 559 560 static inline bool system_supports_mixed_endian_el0(void) 561 { 562 return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1)); 563 } 564 565 static inline bool system_supports_mixed_endian(void) 566 { 567 u64 mmfr0; 568 u32 val; 569 570 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 571 val = cpuid_feature_extract_unsigned_field(mmfr0, 572 ID_AA64MMFR0_BIGENDEL_SHIFT); 573 574 return val == 0x1; 575 } 576 577 static inline bool system_supports_fpsimd(void) 578 { 579 return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD); 580 } 581 582 static inline bool system_uses_ttbr0_pan(void) 583 { 584 return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) && 585 !cpus_have_const_cap(ARM64_HAS_PAN); 586 } 587 588 static inline bool system_supports_sve(void) 589 { 590 return IS_ENABLED(CONFIG_ARM64_SVE) && 591 cpus_have_const_cap(ARM64_SVE); 592 } 593 594 static inline bool system_supports_cnp(void) 595 { 596 return IS_ENABLED(CONFIG_ARM64_CNP) && 597 cpus_have_const_cap(ARM64_HAS_CNP); 598 } 599 600 static inline bool system_supports_address_auth(void) 601 { 602 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) && 603 (cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) || 604 cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF)); 605 } 606 607 static inline bool system_supports_generic_auth(void) 608 { 609 return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) && 610 (cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH_ARCH) || 611 cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF)); 612 } 613 614 static inline bool system_uses_irq_prio_masking(void) 615 { 616 return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) && 617 cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING); 618 } 619 620 #define ARM64_SSBD_UNKNOWN -1 621 #define ARM64_SSBD_FORCE_DISABLE 0 622 #define ARM64_SSBD_KERNEL 1 623 #define ARM64_SSBD_FORCE_ENABLE 2 624 #define ARM64_SSBD_MITIGATED 3 625 626 static inline int arm64_get_ssbd_state(void) 627 { 628 #ifdef CONFIG_ARM64_SSBD 629 extern int ssbd_state; 630 return ssbd_state; 631 #else 632 return ARM64_SSBD_UNKNOWN; 633 #endif 634 } 635 636 void arm64_set_ssbd_mitigation(bool state); 637 638 extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt); 639 640 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange) 641 { 642 switch (parange) { 643 case 0: return 32; 644 case 1: return 36; 645 case 2: return 40; 646 case 3: return 42; 647 case 4: return 44; 648 case 5: return 48; 649 case 6: return 52; 650 /* 651 * A future PE could use a value unknown to the kernel. 652 * However, by the "D10.1.4 Principles of the ID scheme 653 * for fields in ID registers", ARM DDI 0487C.a, any new 654 * value is guaranteed to be higher than what we know already. 655 * As a safe limit, we return the limit supported by the kernel. 656 */ 657 default: return CONFIG_ARM64_PA_BITS; 658 } 659 } 660 #endif /* __ASSEMBLY__ */ 661 662 #endif 663