1 /* 2 * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef __ASM_CPUFEATURE_H 10 #define __ASM_CPUFEATURE_H 11 12 #include <asm/hwcap.h> 13 #include <asm/sysreg.h> 14 15 /* 16 * In the arm64 world (as in the ARM world), elf_hwcap is used both internally 17 * in the kernel and for user space to keep track of which optional features 18 * are supported by the current system. So let's map feature 'x' to HWCAP_x. 19 * Note that HWCAP_x constants are bit fields so we need to take the log. 20 */ 21 22 #define MAX_CPU_FEATURES (8 * sizeof(elf_hwcap)) 23 #define cpu_feature(x) ilog2(HWCAP_ ## x) 24 25 #define ARM64_WORKAROUND_CLEAN_CACHE 0 26 #define ARM64_WORKAROUND_DEVICE_LOAD_ACQUIRE 1 27 #define ARM64_WORKAROUND_845719 2 28 #define ARM64_HAS_SYSREG_GIC_CPUIF 3 29 #define ARM64_HAS_PAN 4 30 #define ARM64_HAS_LSE_ATOMICS 5 31 #define ARM64_WORKAROUND_CAVIUM_23154 6 32 #define ARM64_WORKAROUND_834220 7 33 #define ARM64_HAS_NO_HW_PREFETCH 8 34 #define ARM64_HAS_UAO 9 35 #define ARM64_ALT_PAN_NOT_UAO 10 36 #define ARM64_HAS_VIRT_HOST_EXTN 11 37 #define ARM64_WORKAROUND_CAVIUM_27456 12 38 #define ARM64_HAS_32BIT_EL0 13 39 40 #define ARM64_NCAPS 14 41 42 #ifndef __ASSEMBLY__ 43 44 #include <linux/kernel.h> 45 46 /* CPU feature register tracking */ 47 enum ftr_type { 48 FTR_EXACT, /* Use a predefined safe value */ 49 FTR_LOWER_SAFE, /* Smaller value is safe */ 50 FTR_HIGHER_SAFE,/* Bigger value is safe */ 51 }; 52 53 #define FTR_STRICT true /* SANITY check strict matching required */ 54 #define FTR_NONSTRICT false /* SANITY check ignored */ 55 56 #define FTR_SIGNED true /* Value should be treated as signed */ 57 #define FTR_UNSIGNED false /* Value should be treated as unsigned */ 58 59 struct arm64_ftr_bits { 60 bool sign; /* Value is signed ? */ 61 bool strict; /* CPU Sanity check: strict matching required ? */ 62 enum ftr_type type; 63 u8 shift; 64 u8 width; 65 s64 safe_val; /* safe value for discrete features */ 66 }; 67 68 /* 69 * @arm64_ftr_reg - Feature register 70 * @strict_mask Bits which should match across all CPUs for sanity. 71 * @sys_val Safe value across the CPUs (system view) 72 */ 73 struct arm64_ftr_reg { 74 u32 sys_id; 75 const char *name; 76 u64 strict_mask; 77 u64 sys_val; 78 struct arm64_ftr_bits *ftr_bits; 79 }; 80 81 /* scope of capability check */ 82 enum { 83 SCOPE_SYSTEM, 84 SCOPE_LOCAL_CPU, 85 }; 86 87 struct arm64_cpu_capabilities { 88 const char *desc; 89 u16 capability; 90 int def_scope; /* default scope */ 91 bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope); 92 void (*enable)(void *); /* Called on all active CPUs */ 93 union { 94 struct { /* To be used for erratum handling only */ 95 u32 midr_model; 96 u32 midr_range_min, midr_range_max; 97 }; 98 99 struct { /* Feature register checking */ 100 u32 sys_reg; 101 u8 field_pos; 102 u8 min_field_value; 103 u8 hwcap_type; 104 bool sign; 105 unsigned long hwcap; 106 }; 107 }; 108 }; 109 110 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS); 111 112 bool this_cpu_has_cap(unsigned int cap); 113 114 static inline bool cpu_have_feature(unsigned int num) 115 { 116 return elf_hwcap & (1UL << num); 117 } 118 119 static inline bool cpus_have_cap(unsigned int num) 120 { 121 if (num >= ARM64_NCAPS) 122 return false; 123 return test_bit(num, cpu_hwcaps); 124 } 125 126 static inline void cpus_set_cap(unsigned int num) 127 { 128 if (num >= ARM64_NCAPS) 129 pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n", 130 num, ARM64_NCAPS); 131 else 132 __set_bit(num, cpu_hwcaps); 133 } 134 135 static inline int __attribute_const__ 136 cpuid_feature_extract_signed_field_width(u64 features, int field, int width) 137 { 138 return (s64)(features << (64 - width - field)) >> (64 - width); 139 } 140 141 static inline int __attribute_const__ 142 cpuid_feature_extract_signed_field(u64 features, int field) 143 { 144 return cpuid_feature_extract_signed_field_width(features, field, 4); 145 } 146 147 static inline unsigned int __attribute_const__ 148 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width) 149 { 150 return (u64)(features << (64 - width - field)) >> (64 - width); 151 } 152 153 static inline unsigned int __attribute_const__ 154 cpuid_feature_extract_unsigned_field(u64 features, int field) 155 { 156 return cpuid_feature_extract_unsigned_field_width(features, field, 4); 157 } 158 159 static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp) 160 { 161 return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift); 162 } 163 164 static inline int __attribute_const__ 165 cpuid_feature_extract_field(u64 features, int field, bool sign) 166 { 167 return (sign) ? 168 cpuid_feature_extract_signed_field(features, field) : 169 cpuid_feature_extract_unsigned_field(features, field); 170 } 171 172 static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val) 173 { 174 return (s64)cpuid_feature_extract_field(val, ftrp->shift, ftrp->sign); 175 } 176 177 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0) 178 { 179 return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 || 180 cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1; 181 } 182 183 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0) 184 { 185 u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT); 186 187 return val == ID_AA64PFR0_EL0_32BIT_64BIT; 188 } 189 190 void __init setup_cpu_features(void); 191 192 void update_cpu_capabilities(const struct arm64_cpu_capabilities *caps, 193 const char *info); 194 void check_local_cpu_errata(void); 195 196 void verify_local_cpu_errata(void); 197 void verify_local_cpu_capabilities(void); 198 199 u64 read_system_reg(u32 id); 200 201 static inline bool cpu_supports_mixed_endian_el0(void) 202 { 203 return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); 204 } 205 206 static inline bool system_supports_32bit_el0(void) 207 { 208 return cpus_have_cap(ARM64_HAS_32BIT_EL0); 209 } 210 211 static inline bool system_supports_mixed_endian_el0(void) 212 { 213 return id_aa64mmfr0_mixed_endian_el0(read_system_reg(SYS_ID_AA64MMFR0_EL1)); 214 } 215 216 #endif /* __ASSEMBLY__ */ 217 218 #endif 219