1 /* 2 * Copyright (C) 2012 ARM Ltd. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 #ifndef __ASM_CACHE_H 17 #define __ASM_CACHE_H 18 19 #include <asm/cputype.h> 20 21 #define CTR_L1IP_SHIFT 14 22 #define CTR_L1IP_MASK 3 23 #define CTR_CWG_SHIFT 24 24 #define CTR_CWG_MASK 15 25 26 #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) 27 28 #define ICACHE_POLICY_VPIPT 0 29 #define ICACHE_POLICY_VIPT 2 30 #define ICACHE_POLICY_PIPT 3 31 32 #define L1_CACHE_SHIFT 7 33 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) 34 35 /* 36 * Memory returned by kmalloc() may be used for DMA, so we must make 37 * sure that all such allocations are cache aligned. Otherwise, 38 * unrelated code may cause parts of the buffer to be read into the 39 * cache before the transfer is done, causing old data to be seen by 40 * the CPU. 41 */ 42 #define ARCH_DMA_MINALIGN L1_CACHE_BYTES 43 44 #ifndef __ASSEMBLY__ 45 46 #include <linux/bitops.h> 47 48 #define ICACHEF_ALIASING 0 49 #define ICACHEF_VPIPT 1 50 extern unsigned long __icache_flags; 51 52 /* 53 * Whilst the D-side always behaves as PIPT on AArch64, aliasing is 54 * permitted in the I-cache. 55 */ 56 static inline int icache_is_aliasing(void) 57 { 58 return test_bit(ICACHEF_ALIASING, &__icache_flags); 59 } 60 61 static inline int icache_is_vpipt(void) 62 { 63 return test_bit(ICACHEF_VPIPT, &__icache_flags); 64 } 65 66 static inline u32 cache_type_cwg(void) 67 { 68 return (read_cpuid_cachetype() >> CTR_CWG_SHIFT) & CTR_CWG_MASK; 69 } 70 71 #define __read_mostly __attribute__((__section__(".data..read_mostly"))) 72 73 static inline int cache_line_size(void) 74 { 75 u32 cwg = cache_type_cwg(); 76 return cwg ? 4 << cwg : L1_CACHE_BYTES; 77 } 78 79 #endif /* __ASSEMBLY__ */ 80 81 #endif 82