1 /* 2 * Based on arch/arm/include/asm/assembler.h, arch/arm/mm/proc-macros.S 3 * 4 * Copyright (C) 1996-2000 Russell King 5 * Copyright (C) 2012 ARM Ltd. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef __ASSEMBLY__ 20 #error "Only include this from assembly code" 21 #endif 22 23 #ifndef __ASM_ASSEMBLER_H 24 #define __ASM_ASSEMBLER_H 25 26 #include <asm/asm-offsets.h> 27 #include <asm/cpufeature.h> 28 #include <asm/debug-monitors.h> 29 #include <asm/page.h> 30 #include <asm/pgtable-hwdef.h> 31 #include <asm/ptrace.h> 32 #include <asm/thread_info.h> 33 34 .macro save_and_disable_daif, flags 35 mrs \flags, daif 36 msr daifset, #0xf 37 .endm 38 39 .macro disable_daif 40 msr daifset, #0xf 41 .endm 42 43 .macro enable_daif 44 msr daifclr, #0xf 45 .endm 46 47 .macro restore_daif, flags:req 48 msr daif, \flags 49 .endm 50 51 /* Only on aarch64 pstate, PSR_D_BIT is different for aarch32 */ 52 .macro inherit_daif, pstate:req, tmp:req 53 and \tmp, \pstate, #(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT) 54 msr daif, \tmp 55 .endm 56 57 /* IRQ is the lowest priority flag, unconditionally unmask the rest. */ 58 .macro enable_da_f 59 msr daifclr, #(8 | 4 | 1) 60 .endm 61 62 /* 63 * Enable and disable interrupts. 64 */ 65 .macro disable_irq 66 msr daifset, #2 67 .endm 68 69 .macro enable_irq 70 msr daifclr, #2 71 .endm 72 73 .macro save_and_disable_irq, flags 74 mrs \flags, daif 75 msr daifset, #2 76 .endm 77 78 .macro restore_irq, flags 79 msr daif, \flags 80 .endm 81 82 .macro enable_dbg 83 msr daifclr, #8 84 .endm 85 86 .macro disable_step_tsk, flgs, tmp 87 tbz \flgs, #TIF_SINGLESTEP, 9990f 88 mrs \tmp, mdscr_el1 89 bic \tmp, \tmp, #DBG_MDSCR_SS 90 msr mdscr_el1, \tmp 91 isb // Synchronise with enable_dbg 92 9990: 93 .endm 94 95 /* call with daif masked */ 96 .macro enable_step_tsk, flgs, tmp 97 tbz \flgs, #TIF_SINGLESTEP, 9990f 98 mrs \tmp, mdscr_el1 99 orr \tmp, \tmp, #DBG_MDSCR_SS 100 msr mdscr_el1, \tmp 101 9990: 102 .endm 103 104 /* 105 * SMP data memory barrier 106 */ 107 .macro smp_dmb, opt 108 dmb \opt 109 .endm 110 111 /* 112 * RAS Error Synchronization barrier 113 */ 114 .macro esb 115 hint #16 116 .endm 117 118 /* 119 * Value prediction barrier 120 */ 121 .macro csdb 122 hint #20 123 .endm 124 125 /* 126 * Sanitise a 64-bit bounded index wrt speculation, returning zero if out 127 * of bounds. 128 */ 129 .macro mask_nospec64, idx, limit, tmp 130 sub \tmp, \idx, \limit 131 bic \tmp, \tmp, \idx 132 and \idx, \idx, \tmp, asr #63 133 csdb 134 .endm 135 136 /* 137 * NOP sequence 138 */ 139 .macro nops, num 140 .rept \num 141 nop 142 .endr 143 .endm 144 145 /* 146 * Emit an entry into the exception table 147 */ 148 .macro _asm_extable, from, to 149 .pushsection __ex_table, "a" 150 .align 3 151 .long (\from - .), (\to - .) 152 .popsection 153 .endm 154 155 #define USER(l, x...) \ 156 9999: x; \ 157 _asm_extable 9999b, l 158 159 /* 160 * Register aliases. 161 */ 162 lr .req x30 // link register 163 164 /* 165 * Vector entry 166 */ 167 .macro ventry label 168 .align 7 169 b \label 170 .endm 171 172 /* 173 * Select code when configured for BE. 174 */ 175 #ifdef CONFIG_CPU_BIG_ENDIAN 176 #define CPU_BE(code...) code 177 #else 178 #define CPU_BE(code...) 179 #endif 180 181 /* 182 * Select code when configured for LE. 183 */ 184 #ifdef CONFIG_CPU_BIG_ENDIAN 185 #define CPU_LE(code...) 186 #else 187 #define CPU_LE(code...) code 188 #endif 189 190 /* 191 * Define a macro that constructs a 64-bit value by concatenating two 192 * 32-bit registers. Note that on big endian systems the order of the 193 * registers is swapped. 194 */ 195 #ifndef CONFIG_CPU_BIG_ENDIAN 196 .macro regs_to_64, rd, lbits, hbits 197 #else 198 .macro regs_to_64, rd, hbits, lbits 199 #endif 200 orr \rd, \lbits, \hbits, lsl #32 201 .endm 202 203 /* 204 * Pseudo-ops for PC-relative adr/ldr/str <reg>, <symbol> where 205 * <symbol> is within the range +/- 4 GB of the PC. 206 */ 207 /* 208 * @dst: destination register (64 bit wide) 209 * @sym: name of the symbol 210 */ 211 .macro adr_l, dst, sym 212 adrp \dst, \sym 213 add \dst, \dst, :lo12:\sym 214 .endm 215 216 /* 217 * @dst: destination register (32 or 64 bit wide) 218 * @sym: name of the symbol 219 * @tmp: optional 64-bit scratch register to be used if <dst> is a 220 * 32-bit wide register, in which case it cannot be used to hold 221 * the address 222 */ 223 .macro ldr_l, dst, sym, tmp= 224 .ifb \tmp 225 adrp \dst, \sym 226 ldr \dst, [\dst, :lo12:\sym] 227 .else 228 adrp \tmp, \sym 229 ldr \dst, [\tmp, :lo12:\sym] 230 .endif 231 .endm 232 233 /* 234 * @src: source register (32 or 64 bit wide) 235 * @sym: name of the symbol 236 * @tmp: mandatory 64-bit scratch register to calculate the address 237 * while <src> needs to be preserved. 238 */ 239 .macro str_l, src, sym, tmp 240 adrp \tmp, \sym 241 str \src, [\tmp, :lo12:\sym] 242 .endm 243 244 /* 245 * @dst: Result of per_cpu(sym, smp_processor_id()) (can be SP) 246 * @sym: The name of the per-cpu variable 247 * @tmp: scratch register 248 */ 249 .macro adr_this_cpu, dst, sym, tmp 250 adrp \tmp, \sym 251 add \dst, \tmp, #:lo12:\sym 252 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 253 mrs \tmp, tpidr_el1 254 alternative_else 255 mrs \tmp, tpidr_el2 256 alternative_endif 257 add \dst, \dst, \tmp 258 .endm 259 260 /* 261 * @dst: Result of READ_ONCE(per_cpu(sym, smp_processor_id())) 262 * @sym: The name of the per-cpu variable 263 * @tmp: scratch register 264 */ 265 .macro ldr_this_cpu dst, sym, tmp 266 adr_l \dst, \sym 267 alternative_if_not ARM64_HAS_VIRT_HOST_EXTN 268 mrs \tmp, tpidr_el1 269 alternative_else 270 mrs \tmp, tpidr_el2 271 alternative_endif 272 ldr \dst, [\dst, \tmp] 273 .endm 274 275 /* 276 * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) 277 */ 278 .macro vma_vm_mm, rd, rn 279 ldr \rd, [\rn, #VMA_VM_MM] 280 .endm 281 282 /* 283 * mmid - get context id from mm pointer (mm->context.id) 284 */ 285 .macro mmid, rd, rn 286 ldr \rd, [\rn, #MM_CONTEXT_ID] 287 .endm 288 /* 289 * read_ctr - read CTR_EL0. If the system has mismatched 290 * cache line sizes, provide the system wide safe value 291 * from arm64_ftr_reg_ctrel0.sys_val 292 */ 293 .macro read_ctr, reg 294 alternative_if_not ARM64_MISMATCHED_CACHE_LINE_SIZE 295 mrs \reg, ctr_el0 // read CTR 296 nop 297 alternative_else 298 ldr_l \reg, arm64_ftr_reg_ctrel0 + ARM64_FTR_SYSVAL 299 alternative_endif 300 .endm 301 302 303 /* 304 * raw_dcache_line_size - get the minimum D-cache line size on this CPU 305 * from the CTR register. 306 */ 307 .macro raw_dcache_line_size, reg, tmp 308 mrs \tmp, ctr_el0 // read CTR 309 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 310 mov \reg, #4 // bytes per word 311 lsl \reg, \reg, \tmp // actual cache line size 312 .endm 313 314 /* 315 * dcache_line_size - get the safe D-cache line size across all CPUs 316 */ 317 .macro dcache_line_size, reg, tmp 318 read_ctr \tmp 319 ubfm \tmp, \tmp, #16, #19 // cache line size encoding 320 mov \reg, #4 // bytes per word 321 lsl \reg, \reg, \tmp // actual cache line size 322 .endm 323 324 /* 325 * raw_icache_line_size - get the minimum I-cache line size on this CPU 326 * from the CTR register. 327 */ 328 .macro raw_icache_line_size, reg, tmp 329 mrs \tmp, ctr_el0 // read CTR 330 and \tmp, \tmp, #0xf // cache line size encoding 331 mov \reg, #4 // bytes per word 332 lsl \reg, \reg, \tmp // actual cache line size 333 .endm 334 335 /* 336 * icache_line_size - get the safe I-cache line size across all CPUs 337 */ 338 .macro icache_line_size, reg, tmp 339 read_ctr \tmp 340 and \tmp, \tmp, #0xf // cache line size encoding 341 mov \reg, #4 // bytes per word 342 lsl \reg, \reg, \tmp // actual cache line size 343 .endm 344 345 /* 346 * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map 347 */ 348 .macro tcr_set_idmap_t0sz, valreg, tmpreg 349 ldr_l \tmpreg, idmap_t0sz 350 bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH 351 .endm 352 353 /* 354 * tcr_compute_pa_size - set TCR.(I)PS to the highest supported 355 * ID_AA64MMFR0_EL1.PARange value 356 * 357 * tcr: register with the TCR_ELx value to be updated 358 * pos: IPS or PS bitfield position 359 * tmp{0,1}: temporary registers 360 */ 361 .macro tcr_compute_pa_size, tcr, pos, tmp0, tmp1 362 mrs \tmp0, ID_AA64MMFR0_EL1 363 // Narrow PARange to fit the PS field in TCR_ELx 364 ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3 365 mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX 366 cmp \tmp0, \tmp1 367 csel \tmp0, \tmp1, \tmp0, hi 368 bfi \tcr, \tmp0, \pos, #3 369 .endm 370 371 /* 372 * Macro to perform a data cache maintenance for the interval 373 * [kaddr, kaddr + size) 374 * 375 * op: operation passed to dc instruction 376 * domain: domain used in dsb instruciton 377 * kaddr: starting virtual address of the region 378 * size: size of the region 379 * Corrupts: kaddr, size, tmp1, tmp2 380 */ 381 .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2 382 dcache_line_size \tmp1, \tmp2 383 add \size, \kaddr, \size 384 sub \tmp2, \tmp1, #1 385 bic \kaddr, \kaddr, \tmp2 386 9998: 387 .if (\op == cvau || \op == cvac) 388 alternative_if_not ARM64_WORKAROUND_CLEAN_CACHE 389 dc \op, \kaddr 390 alternative_else 391 dc civac, \kaddr 392 alternative_endif 393 .elseif (\op == cvap) 394 alternative_if ARM64_HAS_DCPOP 395 sys 3, c7, c12, 1, \kaddr // dc cvap 396 alternative_else 397 dc cvac, \kaddr 398 alternative_endif 399 .else 400 dc \op, \kaddr 401 .endif 402 add \kaddr, \kaddr, \tmp1 403 cmp \kaddr, \size 404 b.lo 9998b 405 dsb \domain 406 .endm 407 408 /* 409 * Macro to perform an instruction cache maintenance for the interval 410 * [start, end) 411 * 412 * start, end: virtual addresses describing the region 413 * label: A label to branch to on user fault. 414 * Corrupts: tmp1, tmp2 415 */ 416 .macro invalidate_icache_by_line start, end, tmp1, tmp2, label 417 icache_line_size \tmp1, \tmp2 418 sub \tmp2, \tmp1, #1 419 bic \tmp2, \start, \tmp2 420 9997: 421 USER(\label, ic ivau, \tmp2) // invalidate I line PoU 422 add \tmp2, \tmp2, \tmp1 423 cmp \tmp2, \end 424 b.lo 9997b 425 dsb ish 426 isb 427 .endm 428 429 /* 430 * reset_pmuserenr_el0 - reset PMUSERENR_EL0 if PMUv3 present 431 */ 432 .macro reset_pmuserenr_el0, tmpreg 433 mrs \tmpreg, id_aa64dfr0_el1 // Check ID_AA64DFR0_EL1 PMUVer 434 sbfx \tmpreg, \tmpreg, #8, #4 435 cmp \tmpreg, #1 // Skip if no PMU present 436 b.lt 9000f 437 msr pmuserenr_el0, xzr // Disable PMU access from EL0 438 9000: 439 .endm 440 441 /* 442 * copy_page - copy src to dest using temp registers t1-t8 443 */ 444 .macro copy_page dest:req src:req t1:req t2:req t3:req t4:req t5:req t6:req t7:req t8:req 445 9998: ldp \t1, \t2, [\src] 446 ldp \t3, \t4, [\src, #16] 447 ldp \t5, \t6, [\src, #32] 448 ldp \t7, \t8, [\src, #48] 449 add \src, \src, #64 450 stnp \t1, \t2, [\dest] 451 stnp \t3, \t4, [\dest, #16] 452 stnp \t5, \t6, [\dest, #32] 453 stnp \t7, \t8, [\dest, #48] 454 add \dest, \dest, #64 455 tst \src, #(PAGE_SIZE - 1) 456 b.ne 9998b 457 .endm 458 459 /* 460 * Annotate a function as position independent, i.e., safe to be called before 461 * the kernel virtual mapping is activated. 462 */ 463 #define ENDPIPROC(x) \ 464 .globl __pi_##x; \ 465 .type __pi_##x, %function; \ 466 .set __pi_##x, x; \ 467 .size __pi_##x, . - x; \ 468 ENDPROC(x) 469 470 /* 471 * Annotate a function as being unsuitable for kprobes. 472 */ 473 #ifdef CONFIG_KPROBES 474 #define NOKPROBE(x) \ 475 .pushsection "_kprobe_blacklist", "aw"; \ 476 .quad x; \ 477 .popsection; 478 #else 479 #define NOKPROBE(x) 480 #endif 481 /* 482 * Emit a 64-bit absolute little endian symbol reference in a way that 483 * ensures that it will be resolved at build time, even when building a 484 * PIE binary. This requires cooperation from the linker script, which 485 * must emit the lo32/hi32 halves individually. 486 */ 487 .macro le64sym, sym 488 .long \sym\()_lo32 489 .long \sym\()_hi32 490 .endm 491 492 /* 493 * mov_q - move an immediate constant into a 64-bit register using 494 * between 2 and 4 movz/movk instructions (depending on the 495 * magnitude and sign of the operand) 496 */ 497 .macro mov_q, reg, val 498 .if (((\val) >> 31) == 0 || ((\val) >> 31) == 0x1ffffffff) 499 movz \reg, :abs_g1_s:\val 500 .else 501 .if (((\val) >> 47) == 0 || ((\val) >> 47) == 0x1ffff) 502 movz \reg, :abs_g2_s:\val 503 .else 504 movz \reg, :abs_g3:\val 505 movk \reg, :abs_g2_nc:\val 506 .endif 507 movk \reg, :abs_g1_nc:\val 508 .endif 509 movk \reg, :abs_g0_nc:\val 510 .endm 511 512 /* 513 * Return the current thread_info. 514 */ 515 .macro get_thread_info, rd 516 mrs \rd, sp_el0 517 .endm 518 519 /* 520 * Arrange a physical address in a TTBR register, taking care of 52-bit 521 * addresses. 522 * 523 * phys: physical address, preserved 524 * ttbr: returns the TTBR value 525 */ 526 .macro phys_to_ttbr, ttbr, phys 527 #ifdef CONFIG_ARM64_PA_BITS_52 528 orr \ttbr, \phys, \phys, lsr #46 529 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52 530 #else 531 mov \ttbr, \phys 532 #endif 533 .endm 534 535 .macro phys_to_pte, pte, phys 536 #ifdef CONFIG_ARM64_PA_BITS_52 537 /* 538 * We assume \phys is 64K aligned and this is guaranteed by only 539 * supporting this configuration with 64K pages. 540 */ 541 orr \pte, \phys, \phys, lsr #36 542 and \pte, \pte, #PTE_ADDR_MASK 543 #else 544 mov \pte, \phys 545 #endif 546 .endm 547 548 .macro pte_to_phys, phys, pte 549 #ifdef CONFIG_ARM64_PA_BITS_52 550 ubfiz \phys, \pte, #(48 - 16 - 12), #16 551 bfxil \phys, \pte, #16, #32 552 lsl \phys, \phys, #16 553 #else 554 and \phys, \pte, #PTE_ADDR_MASK 555 #endif 556 .endm 557 558 /** 559 * Errata workaround prior to disable MMU. Insert an ISB immediately prior 560 * to executing the MSR that will change SCTLR_ELn[M] from a value of 1 to 0. 561 */ 562 .macro pre_disable_mmu_workaround 563 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_E1041 564 isb 565 #endif 566 .endm 567 568 /* 569 * frame_push - Push @regcount callee saved registers to the stack, 570 * starting at x19, as well as x29/x30, and set x29 to 571 * the new value of sp. Add @extra bytes of stack space 572 * for locals. 573 */ 574 .macro frame_push, regcount:req, extra 575 __frame st, \regcount, \extra 576 .endm 577 578 /* 579 * frame_pop - Pop the callee saved registers from the stack that were 580 * pushed in the most recent call to frame_push, as well 581 * as x29/x30 and any extra stack space that may have been 582 * allocated. 583 */ 584 .macro frame_pop 585 __frame ld 586 .endm 587 588 .macro __frame_regs, reg1, reg2, op, num 589 .if .Lframe_regcount == \num 590 \op\()r \reg1, [sp, #(\num + 1) * 8] 591 .elseif .Lframe_regcount > \num 592 \op\()p \reg1, \reg2, [sp, #(\num + 1) * 8] 593 .endif 594 .endm 595 596 .macro __frame, op, regcount, extra=0 597 .ifc \op, st 598 .if (\regcount) < 0 || (\regcount) > 10 599 .error "regcount should be in the range [0 ... 10]" 600 .endif 601 .if ((\extra) % 16) != 0 602 .error "extra should be a multiple of 16 bytes" 603 .endif 604 .ifdef .Lframe_regcount 605 .if .Lframe_regcount != -1 606 .error "frame_push/frame_pop may not be nested" 607 .endif 608 .endif 609 .set .Lframe_regcount, \regcount 610 .set .Lframe_extra, \extra 611 .set .Lframe_local_offset, ((\regcount + 3) / 2) * 16 612 stp x29, x30, [sp, #-.Lframe_local_offset - .Lframe_extra]! 613 mov x29, sp 614 .endif 615 616 __frame_regs x19, x20, \op, 1 617 __frame_regs x21, x22, \op, 3 618 __frame_regs x23, x24, \op, 5 619 __frame_regs x25, x26, \op, 7 620 __frame_regs x27, x28, \op, 9 621 622 .ifc \op, ld 623 .if .Lframe_regcount == -1 624 .error "frame_push/frame_pop may not be nested" 625 .endif 626 ldp x29, x30, [sp], #.Lframe_local_offset + .Lframe_extra 627 .set .Lframe_regcount, -1 628 .endif 629 .endm 630 631 /* 632 * Check whether to yield to another runnable task from kernel mode NEON code 633 * (which runs with preemption disabled). 634 * 635 * if_will_cond_yield_neon 636 * // pre-yield patchup code 637 * do_cond_yield_neon 638 * // post-yield patchup code 639 * endif_yield_neon <label> 640 * 641 * where <label> is optional, and marks the point where execution will resume 642 * after a yield has been performed. If omitted, execution resumes right after 643 * the endif_yield_neon invocation. Note that the entire sequence, including 644 * the provided patchup code, will be omitted from the image if CONFIG_PREEMPT 645 * is not defined. 646 * 647 * As a convenience, in the case where no patchup code is required, the above 648 * sequence may be abbreviated to 649 * 650 * cond_yield_neon <label> 651 * 652 * Note that the patchup code does not support assembler directives that change 653 * the output section, any use of such directives is undefined. 654 * 655 * The yield itself consists of the following: 656 * - Check whether the preempt count is exactly 1, in which case disabling 657 * preemption once will make the task preemptible. If this is not the case, 658 * yielding is pointless. 659 * - Check whether TIF_NEED_RESCHED is set, and if so, disable and re-enable 660 * kernel mode NEON (which will trigger a reschedule), and branch to the 661 * yield fixup code. 662 * 663 * This macro sequence may clobber all CPU state that is not guaranteed by the 664 * AAPCS to be preserved across an ordinary function call. 665 */ 666 667 .macro cond_yield_neon, lbl 668 if_will_cond_yield_neon 669 do_cond_yield_neon 670 endif_yield_neon \lbl 671 .endm 672 673 .macro if_will_cond_yield_neon 674 #ifdef CONFIG_PREEMPT 675 get_thread_info x0 676 ldr w1, [x0, #TSK_TI_PREEMPT] 677 ldr x0, [x0, #TSK_TI_FLAGS] 678 cmp w1, #PREEMPT_DISABLE_OFFSET 679 csel x0, x0, xzr, eq 680 tbnz x0, #TIF_NEED_RESCHED, .Lyield_\@ // needs rescheduling? 681 /* fall through to endif_yield_neon */ 682 .subsection 1 683 .Lyield_\@ : 684 #else 685 .section ".discard.cond_yield_neon", "ax" 686 #endif 687 .endm 688 689 .macro do_cond_yield_neon 690 bl kernel_neon_end 691 bl kernel_neon_begin 692 .endm 693 694 .macro endif_yield_neon, lbl 695 .ifnb \lbl 696 b \lbl 697 .else 698 b .Lyield_out_\@ 699 .endif 700 .previous 701 .Lyield_out_\@ : 702 .endm 703 704 #endif /* __ASM_ASSEMBLER_H */ 705