xref: /openbmc/linux/arch/arm64/include/asm/arm_pmuv3.h (revision 0c6dfa75) 
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2012 ARM Ltd.
4  */
5 
6 #ifndef __ASM_PMUV3_H
7 #define __ASM_PMUV3_H
8 
9 #include <linux/kvm_host.h>
10 
11 #include <asm/cpufeature.h>
12 #include <asm/sysreg.h>
13 
14 #define RETURN_READ_PMEVCNTRN(n) \
15 	return read_sysreg(pmevcntr##n##_el0)
16 static inline unsigned long read_pmevcntrn(int n)
17 {
18 	PMEVN_SWITCH(n, RETURN_READ_PMEVCNTRN);
19 	return 0;
20 }
21 
22 #define WRITE_PMEVCNTRN(n) \
23 	write_sysreg(val, pmevcntr##n##_el0)
24 static inline void write_pmevcntrn(int n, unsigned long val)
25 {
26 	PMEVN_SWITCH(n, WRITE_PMEVCNTRN);
27 }
28 
29 #define WRITE_PMEVTYPERN(n) \
30 	write_sysreg(val, pmevtyper##n##_el0)
31 static inline void write_pmevtypern(int n, unsigned long val)
32 {
33 	PMEVN_SWITCH(n, WRITE_PMEVTYPERN);
34 }
35 
36 static inline unsigned long read_pmmir(void)
37 {
38 	return read_cpuid(PMMIR_EL1);
39 }
40 
41 static inline u32 read_pmuver(void)
42 {
43 	u64 dfr0 = read_sysreg(id_aa64dfr0_el1);
44 
45 	return cpuid_feature_extract_unsigned_field(dfr0,
46 			ID_AA64DFR0_EL1_PMUVer_SHIFT);
47 }
48 
49 static inline void write_pmcr(u32 val)
50 {
51 	write_sysreg(val, pmcr_el0);
52 }
53 
54 static inline u32 read_pmcr(void)
55 {
56 	return read_sysreg(pmcr_el0);
57 }
58 
59 static inline void write_pmselr(u32 val)
60 {
61 	write_sysreg(val, pmselr_el0);
62 }
63 
64 static inline void write_pmccntr(u64 val)
65 {
66 	write_sysreg(val, pmccntr_el0);
67 }
68 
69 static inline u64 read_pmccntr(void)
70 {
71 	return read_sysreg(pmccntr_el0);
72 }
73 
74 static inline void write_pmxevcntr(u32 val)
75 {
76 	write_sysreg(val, pmxevcntr_el0);
77 }
78 
79 static inline u32 read_pmxevcntr(void)
80 {
81 	return read_sysreg(pmxevcntr_el0);
82 }
83 
84 static inline void write_pmxevtyper(u32 val)
85 {
86 	write_sysreg(val, pmxevtyper_el0);
87 }
88 
89 static inline void write_pmcntenset(u32 val)
90 {
91 	write_sysreg(val, pmcntenset_el0);
92 }
93 
94 static inline void write_pmcntenclr(u32 val)
95 {
96 	write_sysreg(val, pmcntenclr_el0);
97 }
98 
99 static inline void write_pmintenset(u32 val)
100 {
101 	write_sysreg(val, pmintenset_el1);
102 }
103 
104 static inline void write_pmintenclr(u32 val)
105 {
106 	write_sysreg(val, pmintenclr_el1);
107 }
108 
109 static inline void write_pmccfiltr(u32 val)
110 {
111 	write_sysreg(val, pmccfiltr_el0);
112 }
113 
114 static inline void write_pmovsclr(u32 val)
115 {
116 	write_sysreg(val, pmovsclr_el0);
117 }
118 
119 static inline u32 read_pmovsclr(void)
120 {
121 	return read_sysreg(pmovsclr_el0);
122 }
123 
124 static inline void write_pmuserenr(u32 val)
125 {
126 	write_sysreg(val, pmuserenr_el0);
127 }
128 
129 static inline u32 read_pmceid0(void)
130 {
131 	return read_sysreg(pmceid0_el0);
132 }
133 
134 static inline u32 read_pmceid1(void)
135 {
136 	return read_sysreg(pmceid1_el0);
137 }
138 
139 static inline bool pmuv3_implemented(int pmuver)
140 {
141 	return !(pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF ||
142 		 pmuver == ID_AA64DFR0_EL1_PMUVer_NI);
143 }
144 
145 static inline bool is_pmuv3p4(int pmuver)
146 {
147 	return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P4;
148 }
149 
150 static inline bool is_pmuv3p5(int pmuver)
151 {
152 	return pmuver >= ID_AA64DFR0_EL1_PMUVer_V3P5;
153 }
154 
155 #endif
156