1 /*
2  * arch/arm64/include/asm/arch_timer.h
3  *
4  * Copyright (C) 2012 ARM Ltd.
5  * Author: Marc Zyngier <marc.zyngier@arm.com>
6  *
7  * This program is free software: you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License version 2 as
9  * published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 #ifndef __ASM_ARCH_TIMER_H
20 #define __ASM_ARCH_TIMER_H
21 
22 #include <asm/barrier.h>
23 
24 #include <linux/init.h>
25 #include <linux/types.h>
26 
27 #include <clocksource/arm_arch_timer.h>
28 
29 /*
30  * These register accessors are marked inline so the compiler can
31  * nicely work out which register we want, and chuck away the rest of
32  * the code.
33  */
34 static __always_inline
35 void arch_timer_reg_write_cp15(int access, enum arch_timer_reg reg, u32 val)
36 {
37 	if (access == ARCH_TIMER_PHYS_ACCESS) {
38 		switch (reg) {
39 		case ARCH_TIMER_REG_CTRL:
40 			asm volatile("msr cntp_ctl_el0,  %0" : : "r" (val));
41 			break;
42 		case ARCH_TIMER_REG_TVAL:
43 			asm volatile("msr cntp_tval_el0, %0" : : "r" (val));
44 			break;
45 		}
46 	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
47 		switch (reg) {
48 		case ARCH_TIMER_REG_CTRL:
49 			asm volatile("msr cntv_ctl_el0,  %0" : : "r" (val));
50 			break;
51 		case ARCH_TIMER_REG_TVAL:
52 			asm volatile("msr cntv_tval_el0, %0" : : "r" (val));
53 			break;
54 		}
55 	}
56 
57 	isb();
58 }
59 
60 static __always_inline
61 u32 arch_timer_reg_read_cp15(int access, enum arch_timer_reg reg)
62 {
63 	u32 val;
64 
65 	if (access == ARCH_TIMER_PHYS_ACCESS) {
66 		switch (reg) {
67 		case ARCH_TIMER_REG_CTRL:
68 			asm volatile("mrs %0,  cntp_ctl_el0" : "=r" (val));
69 			break;
70 		case ARCH_TIMER_REG_TVAL:
71 			asm volatile("mrs %0, cntp_tval_el0" : "=r" (val));
72 			break;
73 		}
74 	} else if (access == ARCH_TIMER_VIRT_ACCESS) {
75 		switch (reg) {
76 		case ARCH_TIMER_REG_CTRL:
77 			asm volatile("mrs %0,  cntv_ctl_el0" : "=r" (val));
78 			break;
79 		case ARCH_TIMER_REG_TVAL:
80 			asm volatile("mrs %0, cntv_tval_el0" : "=r" (val));
81 			break;
82 		}
83 	}
84 
85 	return val;
86 }
87 
88 static inline u32 arch_timer_get_cntfrq(void)
89 {
90 	u32 val;
91 	asm volatile("mrs %0,   cntfrq_el0" : "=r" (val));
92 	return val;
93 }
94 
95 static inline void arch_counter_set_user_access(void)
96 {
97 	u32 cntkctl;
98 
99 	/* Disable user access to the timers and the physical counter. */
100 	asm volatile("mrs	%0, cntkctl_el1" : "=r" (cntkctl));
101 	cntkctl &= ~((3 << 8) | (1 << 0));
102 
103 	/* Enable user access to the virtual counter and frequency. */
104 	cntkctl |= (1 << 1);
105 	asm volatile("msr	cntkctl_el1, %0" : : "r" (cntkctl));
106 }
107 
108 static inline u64 arch_counter_get_cntvct(void)
109 {
110 	u64 cval;
111 
112 	isb();
113 	asm volatile("mrs %0, cntvct_el0" : "=r" (cval));
114 
115 	return cval;
116 }
117 
118 static inline int arch_timer_arch_init(void)
119 {
120 	return 0;
121 }
122 
123 #endif
124