1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * arch/arm64/include/asm/arch_gicv3.h
4  *
5  * Copyright (C) 2015 ARM Ltd.
6  */
7 #ifndef __ASM_ARCH_GICV3_H
8 #define __ASM_ARCH_GICV3_H
9 
10 #include <asm/sysreg.h>
11 
12 #ifndef __ASSEMBLY__
13 
14 #include <linux/irqchip/arm-gic-common.h>
15 #include <linux/stringify.h>
16 #include <asm/barrier.h>
17 #include <asm/cacheflush.h>
18 
19 #define read_gicreg(r)			read_sysreg_s(SYS_ ## r)
20 #define write_gicreg(v, r)		write_sysreg_s(v, SYS_ ## r)
21 
22 /*
23  * Low-level accessors
24  *
25  * These system registers are 32 bits, but we make sure that the compiler
26  * sets the GP register's most significant bits to 0 with an explicit cast.
27  */
28 
29 static __always_inline void gic_write_dir(u32 irq)
30 {
31 	write_sysreg_s(irq, SYS_ICC_DIR_EL1);
32 	isb();
33 }
34 
35 static inline u64 gic_read_iar_common(void)
36 {
37 	u64 irqstat;
38 
39 	irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
40 	dsb(sy);
41 	return irqstat;
42 }
43 
44 /*
45  * Cavium ThunderX erratum 23154
46  *
47  * The gicv3 of ThunderX requires a modified version for reading the
48  * IAR status to ensure data synchronization (access to icc_iar1_el1
49  * is not sync'ed before and after).
50  *
51  * Erratum 38545
52  *
53  * When a IAR register read races with a GIC interrupt RELEASE event,
54  * GIC-CPU interface could wrongly return a valid INTID to the CPU
55  * for an interrupt that is already released(non activated) instead of 0x3ff.
56  *
57  * To workaround this, return a valid interrupt ID only if there is a change
58  * in the active priority list after the IAR read.
59  *
60  * Common function used for both the workarounds since,
61  * 1. On Thunderx 88xx 1.x both erratas are applicable.
62  * 2. Having extra nops doesn't add any side effects for Silicons where
63  *    erratum 23154 is not applicable.
64  */
65 static inline u64 gic_read_iar_cavium_thunderx(void)
66 {
67 	u64 irqstat, apr;
68 
69 	apr = read_sysreg_s(SYS_ICC_AP1R0_EL1);
70 	nops(8);
71 	irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
72 	nops(4);
73 	mb();
74 
75 	/* Max priority groups implemented is only 32 */
76 	if (likely(apr != read_sysreg_s(SYS_ICC_AP1R0_EL1)))
77 		return irqstat;
78 
79 	return 0x3ff;
80 }
81 
82 static inline void gic_write_ctlr(u32 val)
83 {
84 	write_sysreg_s(val, SYS_ICC_CTLR_EL1);
85 	isb();
86 }
87 
88 static inline u32 gic_read_ctlr(void)
89 {
90 	return read_sysreg_s(SYS_ICC_CTLR_EL1);
91 }
92 
93 static inline void gic_write_grpen1(u32 val)
94 {
95 	write_sysreg_s(val, SYS_ICC_IGRPEN1_EL1);
96 	isb();
97 }
98 
99 static inline void gic_write_sgi1r(u64 val)
100 {
101 	write_sysreg_s(val, SYS_ICC_SGI1R_EL1);
102 }
103 
104 static inline u32 gic_read_sre(void)
105 {
106 	return read_sysreg_s(SYS_ICC_SRE_EL1);
107 }
108 
109 static inline void gic_write_sre(u32 val)
110 {
111 	write_sysreg_s(val, SYS_ICC_SRE_EL1);
112 	isb();
113 }
114 
115 static inline void gic_write_bpr1(u32 val)
116 {
117 	write_sysreg_s(val, SYS_ICC_BPR1_EL1);
118 }
119 
120 static inline u32 gic_read_pmr(void)
121 {
122 	return read_sysreg_s(SYS_ICC_PMR_EL1);
123 }
124 
125 static __always_inline void gic_write_pmr(u32 val)
126 {
127 	write_sysreg_s(val, SYS_ICC_PMR_EL1);
128 }
129 
130 static inline u32 gic_read_rpr(void)
131 {
132 	return read_sysreg_s(SYS_ICC_RPR_EL1);
133 }
134 
135 #define gic_read_typer(c)		readq_relaxed(c)
136 #define gic_write_irouter(v, c)		writeq_relaxed(v, c)
137 #define gic_read_lpir(c)		readq_relaxed(c)
138 #define gic_write_lpir(v, c)		writeq_relaxed(v, c)
139 
140 #define gic_flush_dcache_to_poc(a,l)	\
141 	dcache_clean_inval_poc((unsigned long)(a), (unsigned long)(a)+(l))
142 
143 #define gits_read_baser(c)		readq_relaxed(c)
144 #define gits_write_baser(v, c)		writeq_relaxed(v, c)
145 
146 #define gits_read_cbaser(c)		readq_relaxed(c)
147 #define gits_write_cbaser(v, c)		writeq_relaxed(v, c)
148 
149 #define gits_write_cwriter(v, c)	writeq_relaxed(v, c)
150 
151 #define gicr_read_propbaser(c)		readq_relaxed(c)
152 #define gicr_write_propbaser(v, c)	writeq_relaxed(v, c)
153 
154 #define gicr_write_pendbaser(v, c)	writeq_relaxed(v, c)
155 #define gicr_read_pendbaser(c)		readq_relaxed(c)
156 
157 #define gicr_write_vpropbaser(v, c)	writeq_relaxed(v, c)
158 #define gicr_read_vpropbaser(c)		readq_relaxed(c)
159 
160 #define gicr_write_vpendbaser(v, c)	writeq_relaxed(v, c)
161 #define gicr_read_vpendbaser(c)		readq_relaxed(c)
162 
163 static inline bool gic_prio_masking_enabled(void)
164 {
165 	return system_uses_irq_prio_masking();
166 }
167 
168 static inline void gic_pmr_mask_irqs(void)
169 {
170 	BUILD_BUG_ON(GICD_INT_DEF_PRI < (__GIC_PRIO_IRQOFF |
171 					 GIC_PRIO_PSR_I_SET));
172 	BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
173 	/*
174 	 * Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared
175 	 * and non-secure PMR accesses are not subject to the shifts that
176 	 * are applied to IRQ priorities
177 	 */
178 	BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
179 	/*
180 	 * Same situation as above, but now we make sure that we can mask
181 	 * regular interrupts.
182 	 */
183 	BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) < (__GIC_PRIO_IRQOFF_NS |
184 							 GIC_PRIO_PSR_I_SET));
185 	gic_write_pmr(GIC_PRIO_IRQOFF);
186 }
187 
188 static inline void gic_arch_enable_irqs(void)
189 {
190 	asm volatile ("msr daifclr, #3" : : : "memory");
191 }
192 
193 static inline bool gic_has_relaxed_pmr_sync(void)
194 {
195 	return cpus_have_cap(ARM64_HAS_GIC_PRIO_RELAXED_SYNC);
196 }
197 
198 #endif /* __ASSEMBLY__ */
199 #endif /* __ASM_ARCH_GICV3_H */
200