1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_ALTERNATIVE_H 3 #define __ASM_ALTERNATIVE_H 4 5 #include <asm/cpucaps.h> 6 #include <asm/insn.h> 7 8 #define ARM64_CB_PATCH ARM64_NCAPS 9 10 #ifndef __ASSEMBLY__ 11 12 #include <linux/init.h> 13 #include <linux/types.h> 14 #include <linux/stddef.h> 15 #include <linux/stringify.h> 16 17 extern int alternatives_applied; 18 19 struct alt_instr { 20 s32 orig_offset; /* offset to original instruction */ 21 s32 alt_offset; /* offset to replacement instruction */ 22 u16 cpufeature; /* cpufeature bit set for replacement */ 23 u8 orig_len; /* size of original instruction(s) */ 24 u8 alt_len; /* size of new instruction(s), <= orig_len */ 25 }; 26 27 typedef void (*alternative_cb_t)(struct alt_instr *alt, 28 __le32 *origptr, __le32 *updptr, int nr_inst); 29 30 void __init apply_alternatives_all(void); 31 void apply_alternatives(void *start, size_t length); 32 33 #define ALTINSTR_ENTRY(feature,cb) \ 34 " .word 661b - .\n" /* label */ \ 35 " .if " __stringify(cb) " == 0\n" \ 36 " .word 663f - .\n" /* new instruction */ \ 37 " .else\n" \ 38 " .word " __stringify(cb) "- .\n" /* callback */ \ 39 " .endif\n" \ 40 " .hword " __stringify(feature) "\n" /* feature bit */ \ 41 " .byte 662b-661b\n" /* source len */ \ 42 " .byte 664f-663f\n" /* replacement len */ 43 44 /* 45 * alternative assembly primitive: 46 * 47 * If any of these .org directive fail, it means that insn1 and insn2 48 * don't have the same length. This used to be written as 49 * 50 * .if ((664b-663b) != (662b-661b)) 51 * .error "Alternatives instruction length mismatch" 52 * .endif 53 * 54 * but most assemblers die if insn1 or insn2 have a .inst. This should 55 * be fixed in a binutils release posterior to 2.25.51.0.2 (anything 56 * containing commit 4e4d08cf7399b606 or c1baaddf8861). 57 * 58 * Alternatives with callbacks do not generate replacement instructions. 59 */ 60 #define __ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg_enabled, cb) \ 61 ".if "__stringify(cfg_enabled)" == 1\n" \ 62 "661:\n\t" \ 63 oldinstr "\n" \ 64 "662:\n" \ 65 ".pushsection .altinstructions,\"a\"\n" \ 66 ALTINSTR_ENTRY(feature,cb) \ 67 ".popsection\n" \ 68 " .if " __stringify(cb) " == 0\n" \ 69 ".pushsection .altinstr_replacement, \"a\"\n" \ 70 "663:\n\t" \ 71 newinstr "\n" \ 72 "664:\n\t" \ 73 ".popsection\n\t" \ 74 ".org . - (664b-663b) + (662b-661b)\n\t" \ 75 ".org . - (662b-661b) + (664b-663b)\n" \ 76 ".else\n\t" \ 77 "663:\n\t" \ 78 "664:\n\t" \ 79 ".endif\n" \ 80 ".endif\n" 81 82 #define _ALTERNATIVE_CFG(oldinstr, newinstr, feature, cfg, ...) \ 83 __ALTERNATIVE_CFG(oldinstr, newinstr, feature, IS_ENABLED(cfg), 0) 84 85 #define ALTERNATIVE_CB(oldinstr, cb) \ 86 __ALTERNATIVE_CFG(oldinstr, "NOT_AN_INSTRUCTION", ARM64_CB_PATCH, 1, cb) 87 #else 88 89 #include <asm/assembler.h> 90 91 .macro altinstruction_entry orig_offset alt_offset feature orig_len alt_len 92 .word \orig_offset - . 93 .word \alt_offset - . 94 .hword \feature 95 .byte \orig_len 96 .byte \alt_len 97 .endm 98 99 .macro alternative_insn insn1, insn2, cap, enable = 1 100 .if \enable 101 661: \insn1 102 662: .pushsection .altinstructions, "a" 103 altinstruction_entry 661b, 663f, \cap, 662b-661b, 664f-663f 104 .popsection 105 .pushsection .altinstr_replacement, "ax" 106 663: \insn2 107 664: .popsection 108 .org . - (664b-663b) + (662b-661b) 109 .org . - (662b-661b) + (664b-663b) 110 .endif 111 .endm 112 113 /* 114 * Alternative sequences 115 * 116 * The code for the case where the capability is not present will be 117 * assembled and linked as normal. There are no restrictions on this 118 * code. 119 * 120 * The code for the case where the capability is present will be 121 * assembled into a special section to be used for dynamic patching. 122 * Code for that case must: 123 * 124 * 1. Be exactly the same length (in bytes) as the default code 125 * sequence. 126 * 127 * 2. Not contain a branch target that is used outside of the 128 * alternative sequence it is defined in (branches into an 129 * alternative sequence are not fixed up). 130 */ 131 132 /* 133 * Begin an alternative code sequence. 134 */ 135 .macro alternative_if_not cap 136 .set .Lasm_alt_mode, 0 137 .pushsection .altinstructions, "a" 138 altinstruction_entry 661f, 663f, \cap, 662f-661f, 664f-663f 139 .popsection 140 661: 141 .endm 142 143 .macro alternative_if cap 144 .set .Lasm_alt_mode, 1 145 .pushsection .altinstructions, "a" 146 altinstruction_entry 663f, 661f, \cap, 664f-663f, 662f-661f 147 .popsection 148 .pushsection .altinstr_replacement, "ax" 149 .align 2 /* So GAS knows label 661 is suitably aligned */ 150 661: 151 .endm 152 153 .macro alternative_cb cb 154 .set .Lasm_alt_mode, 0 155 .pushsection .altinstructions, "a" 156 altinstruction_entry 661f, \cb, ARM64_CB_PATCH, 662f-661f, 0 157 .popsection 158 661: 159 .endm 160 161 /* 162 * Provide the other half of the alternative code sequence. 163 */ 164 .macro alternative_else 165 662: 166 .if .Lasm_alt_mode==0 167 .pushsection .altinstr_replacement, "ax" 168 .else 169 .popsection 170 .endif 171 663: 172 .endm 173 174 /* 175 * Complete an alternative code sequence. 176 */ 177 .macro alternative_endif 178 664: 179 .if .Lasm_alt_mode==0 180 .popsection 181 .endif 182 .org . - (664b-663b) + (662b-661b) 183 .org . - (662b-661b) + (664b-663b) 184 .endm 185 186 /* 187 * Callback-based alternative epilogue 188 */ 189 .macro alternative_cb_end 190 662: 191 .endm 192 193 /* 194 * Provides a trivial alternative or default sequence consisting solely 195 * of NOPs. The number of NOPs is chosen automatically to match the 196 * previous case. 197 */ 198 .macro alternative_else_nop_endif 199 alternative_else 200 nops (662b-661b) / AARCH64_INSN_SIZE 201 alternative_endif 202 .endm 203 204 #define _ALTERNATIVE_CFG(insn1, insn2, cap, cfg, ...) \ 205 alternative_insn insn1, insn2, cap, IS_ENABLED(cfg) 206 207 .macro user_alt, label, oldinstr, newinstr, cond 208 9999: alternative_insn "\oldinstr", "\newinstr", \cond 209 _ASM_EXTABLE 9999b, \label 210 .endm 211 212 /* 213 * Generate the assembly for UAO alternatives with exception table entries. 214 * This is complicated as there is no post-increment or pair versions of the 215 * unprivileged instructions, and USER() only works for single instructions. 216 */ 217 #ifdef CONFIG_ARM64_UAO 218 .macro uao_ldp l, reg1, reg2, addr, post_inc 219 alternative_if_not ARM64_HAS_UAO 220 8888: ldp \reg1, \reg2, [\addr], \post_inc; 221 8889: nop; 222 nop; 223 alternative_else 224 ldtr \reg1, [\addr]; 225 ldtr \reg2, [\addr, #8]; 226 add \addr, \addr, \post_inc; 227 alternative_endif 228 229 _asm_extable 8888b,\l; 230 _asm_extable 8889b,\l; 231 .endm 232 233 .macro uao_stp l, reg1, reg2, addr, post_inc 234 alternative_if_not ARM64_HAS_UAO 235 8888: stp \reg1, \reg2, [\addr], \post_inc; 236 8889: nop; 237 nop; 238 alternative_else 239 sttr \reg1, [\addr]; 240 sttr \reg2, [\addr, #8]; 241 add \addr, \addr, \post_inc; 242 alternative_endif 243 244 _asm_extable 8888b,\l; 245 _asm_extable 8889b,\l; 246 .endm 247 248 .macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc 249 alternative_if_not ARM64_HAS_UAO 250 8888: \inst \reg, [\addr], \post_inc; 251 nop; 252 alternative_else 253 \alt_inst \reg, [\addr]; 254 add \addr, \addr, \post_inc; 255 alternative_endif 256 257 _asm_extable 8888b,\l; 258 .endm 259 #else 260 .macro uao_ldp l, reg1, reg2, addr, post_inc 261 USER(\l, ldp \reg1, \reg2, [\addr], \post_inc) 262 .endm 263 .macro uao_stp l, reg1, reg2, addr, post_inc 264 USER(\l, stp \reg1, \reg2, [\addr], \post_inc) 265 .endm 266 .macro uao_user_alternative l, inst, alt_inst, reg, addr, post_inc 267 USER(\l, \inst \reg, [\addr], \post_inc) 268 .endm 269 #endif 270 271 #endif /* __ASSEMBLY__ */ 272 273 /* 274 * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature)); 275 * 276 * Usage: asm(ALTERNATIVE(oldinstr, newinstr, feature, CONFIG_FOO)); 277 * N.B. If CONFIG_FOO is specified, but not selected, the whole block 278 * will be omitted, including oldinstr. 279 */ 280 #define ALTERNATIVE(oldinstr, newinstr, ...) \ 281 _ALTERNATIVE_CFG(oldinstr, newinstr, __VA_ARGS__, 1) 282 283 #endif /* __ASM_ALTERNATIVE_H */ 284