1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2015, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15/ { 16 compatible = "xlnx,zynqmp"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a53", "arm,armv8"; 26 device_type = "cpu"; 27 enable-method = "psci"; 28 operating-points-v2 = <&cpu_opp_table>; 29 reg = <0x0>; 30 cpu-idle-states = <&CPU_SLEEP_0>; 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "arm,cortex-a53", "arm,armv8"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x1>; 38 operating-points-v2 = <&cpu_opp_table>; 39 cpu-idle-states = <&CPU_SLEEP_0>; 40 }; 41 42 cpu2: cpu@2 { 43 compatible = "arm,cortex-a53", "arm,armv8"; 44 device_type = "cpu"; 45 enable-method = "psci"; 46 reg = <0x2>; 47 operating-points-v2 = <&cpu_opp_table>; 48 cpu-idle-states = <&CPU_SLEEP_0>; 49 }; 50 51 cpu3: cpu@3 { 52 compatible = "arm,cortex-a53", "arm,armv8"; 53 device_type = "cpu"; 54 enable-method = "psci"; 55 reg = <0x3>; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-idle-states = <&CPU_SLEEP_0>; 58 }; 59 60 idle-states { 61 entry-method = "psci"; 62 63 CPU_SLEEP_0: cpu-sleep-0 { 64 compatible = "arm,idle-state"; 65 arm,psci-suspend-param = <0x40000000>; 66 local-timer-stop; 67 entry-latency-us = <300>; 68 exit-latency-us = <600>; 69 min-residency-us = <10000>; 70 }; 71 }; 72 }; 73 74 cpu_opp_table: cpu_opp_table { 75 compatible = "operating-points-v2"; 76 opp-shared; 77 opp00 { 78 opp-hz = /bits/ 64 <1199999988>; 79 opp-microvolt = <1000000>; 80 clock-latency-ns = <500000>; 81 }; 82 opp01 { 83 opp-hz = /bits/ 64 <599999994>; 84 opp-microvolt = <1000000>; 85 clock-latency-ns = <500000>; 86 }; 87 opp02 { 88 opp-hz = /bits/ 64 <399999996>; 89 opp-microvolt = <1000000>; 90 clock-latency-ns = <500000>; 91 }; 92 opp03 { 93 opp-hz = /bits/ 64 <299999997>; 94 opp-microvolt = <1000000>; 95 clock-latency-ns = <500000>; 96 }; 97 }; 98 99 dcc: dcc { 100 compatible = "arm,dcc"; 101 status = "disabled"; 102 }; 103 104 pmu { 105 compatible = "arm,armv8-pmuv3"; 106 interrupt-parent = <&gic>; 107 interrupts = <0 143 4>, 108 <0 144 4>, 109 <0 145 4>, 110 <0 146 4>; 111 }; 112 113 psci { 114 compatible = "arm,psci-0.2"; 115 method = "smc"; 116 }; 117 118 timer { 119 compatible = "arm,armv8-timer"; 120 interrupt-parent = <&gic>; 121 interrupts = <1 13 0xf08>, 122 <1 14 0xf08>, 123 <1 11 0xf08>, 124 <1 10 0xf08>; 125 }; 126 127 amba_apu: amba_apu@0 { 128 compatible = "simple-bus"; 129 #address-cells = <2>; 130 #size-cells = <1>; 131 ranges = <0 0 0 0 0xffffffff>; 132 133 gic: interrupt-controller@f9010000 { 134 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 135 #interrupt-cells = <3>; 136 reg = <0x0 0xf9010000 0x10000>, 137 <0x0 0xf9020000 0x20000>, 138 <0x0 0xf9040000 0x20000>, 139 <0x0 0xf9060000 0x20000>; 140 interrupt-controller; 141 interrupt-parent = <&gic>; 142 interrupts = <1 9 0xf04>; 143 }; 144 }; 145 146 amba: amba { 147 compatible = "simple-bus"; 148 #address-cells = <2>; 149 #size-cells = <2>; 150 ranges; 151 152 can0: can@ff060000 { 153 compatible = "xlnx,zynq-can-1.0"; 154 status = "disabled"; 155 clock-names = "can_clk", "pclk"; 156 reg = <0x0 0xff060000 0x0 0x1000>; 157 interrupts = <0 23 4>; 158 interrupt-parent = <&gic>; 159 tx-fifo-depth = <0x40>; 160 rx-fifo-depth = <0x40>; 161 }; 162 163 can1: can@ff070000 { 164 compatible = "xlnx,zynq-can-1.0"; 165 status = "disabled"; 166 clock-names = "can_clk", "pclk"; 167 reg = <0x0 0xff070000 0x0 0x1000>; 168 interrupts = <0 24 4>; 169 interrupt-parent = <&gic>; 170 tx-fifo-depth = <0x40>; 171 rx-fifo-depth = <0x40>; 172 }; 173 174 cci: cci@fd6e0000 { 175 compatible = "arm,cci-400"; 176 reg = <0x0 0xfd6e0000 0x0 0x9000>; 177 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 181 pmu@9000 { 182 compatible = "arm,cci-400-pmu,r1"; 183 reg = <0x9000 0x5000>; 184 interrupt-parent = <&gic>; 185 interrupts = <0 123 4>, 186 <0 123 4>, 187 <0 123 4>, 188 <0 123 4>, 189 <0 123 4>; 190 }; 191 }; 192 193 /* GDMA */ 194 fpd_dma_chan1: dma@fd500000 { 195 status = "disabled"; 196 compatible = "xlnx,zynqmp-dma-1.0"; 197 reg = <0x0 0xfd500000 0x0 0x1000>; 198 interrupt-parent = <&gic>; 199 interrupts = <0 124 4>; 200 clock-names = "clk_main", "clk_apb"; 201 xlnx,bus-width = <128>; 202 }; 203 204 fpd_dma_chan2: dma@fd510000 { 205 status = "disabled"; 206 compatible = "xlnx,zynqmp-dma-1.0"; 207 reg = <0x0 0xfd510000 0x0 0x1000>; 208 interrupt-parent = <&gic>; 209 interrupts = <0 125 4>; 210 clock-names = "clk_main", "clk_apb"; 211 xlnx,bus-width = <128>; 212 }; 213 214 fpd_dma_chan3: dma@fd520000 { 215 status = "disabled"; 216 compatible = "xlnx,zynqmp-dma-1.0"; 217 reg = <0x0 0xfd520000 0x0 0x1000>; 218 interrupt-parent = <&gic>; 219 interrupts = <0 126 4>; 220 clock-names = "clk_main", "clk_apb"; 221 xlnx,bus-width = <128>; 222 }; 223 224 fpd_dma_chan4: dma@fd530000 { 225 status = "disabled"; 226 compatible = "xlnx,zynqmp-dma-1.0"; 227 reg = <0x0 0xfd530000 0x0 0x1000>; 228 interrupt-parent = <&gic>; 229 interrupts = <0 127 4>; 230 clock-names = "clk_main", "clk_apb"; 231 xlnx,bus-width = <128>; 232 }; 233 234 fpd_dma_chan5: dma@fd540000 { 235 status = "disabled"; 236 compatible = "xlnx,zynqmp-dma-1.0"; 237 reg = <0x0 0xfd540000 0x0 0x1000>; 238 interrupt-parent = <&gic>; 239 interrupts = <0 128 4>; 240 clock-names = "clk_main", "clk_apb"; 241 xlnx,bus-width = <128>; 242 }; 243 244 fpd_dma_chan6: dma@fd550000 { 245 status = "disabled"; 246 compatible = "xlnx,zynqmp-dma-1.0"; 247 reg = <0x0 0xfd550000 0x0 0x1000>; 248 interrupt-parent = <&gic>; 249 interrupts = <0 129 4>; 250 clock-names = "clk_main", "clk_apb"; 251 xlnx,bus-width = <128>; 252 }; 253 254 fpd_dma_chan7: dma@fd560000 { 255 status = "disabled"; 256 compatible = "xlnx,zynqmp-dma-1.0"; 257 reg = <0x0 0xfd560000 0x0 0x1000>; 258 interrupt-parent = <&gic>; 259 interrupts = <0 130 4>; 260 clock-names = "clk_main", "clk_apb"; 261 xlnx,bus-width = <128>; 262 }; 263 264 fpd_dma_chan8: dma@fd570000 { 265 status = "disabled"; 266 compatible = "xlnx,zynqmp-dma-1.0"; 267 reg = <0x0 0xfd570000 0x0 0x1000>; 268 interrupt-parent = <&gic>; 269 interrupts = <0 131 4>; 270 clock-names = "clk_main", "clk_apb"; 271 xlnx,bus-width = <128>; 272 }; 273 274 /* LPDDMA default allows only secured access. inorder to enable 275 * These dma channels, Users should ensure that these dma 276 * Channels are allowed for non secure access. 277 */ 278 lpd_dma_chan1: dma@ffa80000 { 279 status = "disabled"; 280 compatible = "xlnx,zynqmp-dma-1.0"; 281 reg = <0x0 0xffa80000 0x0 0x1000>; 282 interrupt-parent = <&gic>; 283 interrupts = <0 77 4>; 284 clock-names = "clk_main", "clk_apb"; 285 xlnx,bus-width = <64>; 286 }; 287 288 lpd_dma_chan2: dma@ffa90000 { 289 status = "disabled"; 290 compatible = "xlnx,zynqmp-dma-1.0"; 291 reg = <0x0 0xffa90000 0x0 0x1000>; 292 interrupt-parent = <&gic>; 293 interrupts = <0 78 4>; 294 clock-names = "clk_main", "clk_apb"; 295 xlnx,bus-width = <64>; 296 }; 297 298 lpd_dma_chan3: dma@ffaa0000 { 299 status = "disabled"; 300 compatible = "xlnx,zynqmp-dma-1.0"; 301 reg = <0x0 0xffaa0000 0x0 0x1000>; 302 interrupt-parent = <&gic>; 303 interrupts = <0 79 4>; 304 clock-names = "clk_main", "clk_apb"; 305 xlnx,bus-width = <64>; 306 }; 307 308 lpd_dma_chan4: dma@ffab0000 { 309 status = "disabled"; 310 compatible = "xlnx,zynqmp-dma-1.0"; 311 reg = <0x0 0xffab0000 0x0 0x1000>; 312 interrupt-parent = <&gic>; 313 interrupts = <0 80 4>; 314 clock-names = "clk_main", "clk_apb"; 315 xlnx,bus-width = <64>; 316 }; 317 318 lpd_dma_chan5: dma@ffac0000 { 319 status = "disabled"; 320 compatible = "xlnx,zynqmp-dma-1.0"; 321 reg = <0x0 0xffac0000 0x0 0x1000>; 322 interrupt-parent = <&gic>; 323 interrupts = <0 81 4>; 324 clock-names = "clk_main", "clk_apb"; 325 xlnx,bus-width = <64>; 326 }; 327 328 lpd_dma_chan6: dma@ffad0000 { 329 status = "disabled"; 330 compatible = "xlnx,zynqmp-dma-1.0"; 331 reg = <0x0 0xffad0000 0x0 0x1000>; 332 interrupt-parent = <&gic>; 333 interrupts = <0 82 4>; 334 clock-names = "clk_main", "clk_apb"; 335 xlnx,bus-width = <64>; 336 }; 337 338 lpd_dma_chan7: dma@ffae0000 { 339 status = "disabled"; 340 compatible = "xlnx,zynqmp-dma-1.0"; 341 reg = <0x0 0xffae0000 0x0 0x1000>; 342 interrupt-parent = <&gic>; 343 interrupts = <0 83 4>; 344 clock-names = "clk_main", "clk_apb"; 345 xlnx,bus-width = <64>; 346 }; 347 348 lpd_dma_chan8: dma@ffaf0000 { 349 status = "disabled"; 350 compatible = "xlnx,zynqmp-dma-1.0"; 351 reg = <0x0 0xffaf0000 0x0 0x1000>; 352 interrupt-parent = <&gic>; 353 interrupts = <0 84 4>; 354 clock-names = "clk_main", "clk_apb"; 355 xlnx,bus-width = <64>; 356 }; 357 358 gem0: ethernet@ff0b0000 { 359 compatible = "cdns,zynqmp-gem", "cdns,gem"; 360 status = "disabled"; 361 interrupt-parent = <&gic>; 362 interrupts = <0 57 4>, <0 57 4>; 363 reg = <0x0 0xff0b0000 0x0 0x1000>; 364 clock-names = "pclk", "hclk", "tx_clk"; 365 #address-cells = <1>; 366 #size-cells = <0>; 367 }; 368 369 gem1: ethernet@ff0c0000 { 370 compatible = "cdns,zynqmp-gem", "cdns,gem"; 371 status = "disabled"; 372 interrupt-parent = <&gic>; 373 interrupts = <0 59 4>, <0 59 4>; 374 reg = <0x0 0xff0c0000 0x0 0x1000>; 375 clock-names = "pclk", "hclk", "tx_clk"; 376 #address-cells = <1>; 377 #size-cells = <0>; 378 }; 379 380 gem2: ethernet@ff0d0000 { 381 compatible = "cdns,zynqmp-gem", "cdns,gem"; 382 status = "disabled"; 383 interrupt-parent = <&gic>; 384 interrupts = <0 61 4>, <0 61 4>; 385 reg = <0x0 0xff0d0000 0x0 0x1000>; 386 clock-names = "pclk", "hclk", "tx_clk"; 387 #address-cells = <1>; 388 #size-cells = <0>; 389 }; 390 391 gem3: ethernet@ff0e0000 { 392 compatible = "cdns,zynqmp-gem", "cdns,gem"; 393 status = "disabled"; 394 interrupt-parent = <&gic>; 395 interrupts = <0 63 4>, <0 63 4>; 396 reg = <0x0 0xff0e0000 0x0 0x1000>; 397 clock-names = "pclk", "hclk", "tx_clk"; 398 #address-cells = <1>; 399 #size-cells = <0>; 400 }; 401 402 gpio: gpio@ff0a0000 { 403 compatible = "xlnx,zynqmp-gpio-1.0"; 404 status = "disabled"; 405 #gpio-cells = <0x2>; 406 interrupt-parent = <&gic>; 407 interrupts = <0 16 4>; 408 interrupt-controller; 409 #interrupt-cells = <2>; 410 reg = <0x0 0xff0a0000 0x0 0x1000>; 411 }; 412 413 i2c0: i2c@ff020000 { 414 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 415 status = "disabled"; 416 interrupt-parent = <&gic>; 417 interrupts = <0 17 4>; 418 reg = <0x0 0xff020000 0x0 0x1000>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 }; 422 423 i2c1: i2c@ff030000 { 424 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 425 status = "disabled"; 426 interrupt-parent = <&gic>; 427 interrupts = <0 18 4>; 428 reg = <0x0 0xff030000 0x0 0x1000>; 429 #address-cells = <1>; 430 #size-cells = <0>; 431 }; 432 433 pcie: pcie@fd0e0000 { 434 compatible = "xlnx,nwl-pcie-2.11"; 435 status = "disabled"; 436 #address-cells = <3>; 437 #size-cells = <2>; 438 #interrupt-cells = <1>; 439 msi-controller; 440 device_type = "pci"; 441 interrupt-parent = <&gic>; 442 interrupts = <0 118 4>, 443 <0 117 4>, 444 <0 116 4>, 445 <0 115 4>, /* MSI_1 [63...32] */ 446 <0 114 4>; /* MSI_0 [31...0] */ 447 interrupt-names = "misc", "dummy", "intx", 448 "msi1", "msi0"; 449 msi-parent = <&pcie>; 450 reg = <0x0 0xfd0e0000 0x0 0x1000>, 451 <0x0 0xfd480000 0x0 0x1000>, 452 <0x80 0x00000000 0x0 0x1000000>; 453 reg-names = "breg", "pcireg", "cfg"; 454 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 455 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 456 bus-range = <0x00 0xff>; 457 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 458 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 459 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 460 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 461 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 462 pcie_intc: legacy-interrupt-controller { 463 interrupt-controller; 464 #address-cells = <0>; 465 #interrupt-cells = <1>; 466 }; 467 }; 468 469 rtc: rtc@ffa60000 { 470 compatible = "xlnx,zynqmp-rtc"; 471 status = "disabled"; 472 reg = <0x0 0xffa60000 0x0 0x100>; 473 interrupt-parent = <&gic>; 474 interrupts = <0 26 4>, <0 27 4>; 475 interrupt-names = "alarm", "sec"; 476 calibration = <0x8000>; 477 }; 478 479 sata: ahci@fd0c0000 { 480 compatible = "ceva,ahci-1v84"; 481 status = "disabled"; 482 reg = <0x0 0xfd0c0000 0x0 0x2000>; 483 interrupt-parent = <&gic>; 484 interrupts = <0 133 4>; 485 }; 486 487 sdhci0: sdhci@ff160000 { 488 compatible = "arasan,sdhci-8.9a"; 489 status = "disabled"; 490 interrupt-parent = <&gic>; 491 interrupts = <0 48 4>; 492 reg = <0x0 0xff160000 0x0 0x1000>; 493 clock-names = "clk_xin", "clk_ahb"; 494 }; 495 496 sdhci1: sdhci@ff170000 { 497 compatible = "arasan,sdhci-8.9a"; 498 status = "disabled"; 499 interrupt-parent = <&gic>; 500 interrupts = <0 49 4>; 501 reg = <0x0 0xff170000 0x0 0x1000>; 502 clock-names = "clk_xin", "clk_ahb"; 503 }; 504 505 smmu: smmu@fd800000 { 506 compatible = "arm,mmu-500"; 507 reg = <0x0 0xfd800000 0x0 0x20000>; 508 status = "disabled"; 509 #global-interrupts = <1>; 510 interrupt-parent = <&gic>; 511 interrupts = <0 155 4>, 512 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 513 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 514 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 515 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 516 }; 517 518 spi0: spi@ff040000 { 519 compatible = "cdns,spi-r1p6"; 520 status = "disabled"; 521 interrupt-parent = <&gic>; 522 interrupts = <0 19 4>; 523 reg = <0x0 0xff040000 0x0 0x1000>; 524 clock-names = "ref_clk", "pclk"; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 }; 528 529 spi1: spi@ff050000 { 530 compatible = "cdns,spi-r1p6"; 531 status = "disabled"; 532 interrupt-parent = <&gic>; 533 interrupts = <0 20 4>; 534 reg = <0x0 0xff050000 0x0 0x1000>; 535 clock-names = "ref_clk", "pclk"; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 }; 539 540 ttc0: timer@ff110000 { 541 compatible = "cdns,ttc"; 542 status = "disabled"; 543 interrupt-parent = <&gic>; 544 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 545 reg = <0x0 0xff110000 0x0 0x1000>; 546 timer-width = <32>; 547 }; 548 549 ttc1: timer@ff120000 { 550 compatible = "cdns,ttc"; 551 status = "disabled"; 552 interrupt-parent = <&gic>; 553 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 554 reg = <0x0 0xff120000 0x0 0x1000>; 555 timer-width = <32>; 556 }; 557 558 ttc2: timer@ff130000 { 559 compatible = "cdns,ttc"; 560 status = "disabled"; 561 interrupt-parent = <&gic>; 562 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 563 reg = <0x0 0xff130000 0x0 0x1000>; 564 timer-width = <32>; 565 }; 566 567 ttc3: timer@ff140000 { 568 compatible = "cdns,ttc"; 569 status = "disabled"; 570 interrupt-parent = <&gic>; 571 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 572 reg = <0x0 0xff140000 0x0 0x1000>; 573 timer-width = <32>; 574 }; 575 576 uart0: serial@ff000000 { 577 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 578 status = "disabled"; 579 interrupt-parent = <&gic>; 580 interrupts = <0 21 4>; 581 reg = <0x0 0xff000000 0x0 0x1000>; 582 clock-names = "uart_clk", "pclk"; 583 }; 584 585 uart1: serial@ff010000 { 586 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 587 status = "disabled"; 588 interrupt-parent = <&gic>; 589 interrupts = <0 22 4>; 590 reg = <0x0 0xff010000 0x0 0x1000>; 591 clock-names = "uart_clk", "pclk"; 592 }; 593 594 usb0: usb@fe200000 { 595 compatible = "snps,dwc3"; 596 status = "disabled"; 597 interrupt-parent = <&gic>; 598 interrupts = <0 65 4>; 599 reg = <0x0 0xfe200000 0x0 0x40000>; 600 clock-names = "clk_xin", "clk_ahb"; 601 }; 602 603 usb1: usb@fe300000 { 604 compatible = "snps,dwc3"; 605 status = "disabled"; 606 interrupt-parent = <&gic>; 607 interrupts = <0 70 4>; 608 reg = <0x0 0xfe300000 0x0 0x40000>; 609 clock-names = "clk_xin", "clk_ahb"; 610 }; 611 612 watchdog0: watchdog@fd4d0000 { 613 compatible = "cdns,wdt-r1p2"; 614 status = "disabled"; 615 interrupt-parent = <&gic>; 616 interrupts = <0 113 1>; 617 reg = <0x0 0xfd4d0000 0x0 0x1000>; 618 timeout-sec = <10>; 619 }; 620 }; 621}; 622