1/* 2 * dts file for Xilinx ZynqMP 3 * 4 * (C) Copyright 2014 - 2015, Xilinx, Inc. 5 * 6 * Michal Simek <michal.simek@xilinx.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 */ 13 14/ { 15 compatible = "xlnx,zynqmp"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 compatible = "arm,cortex-a53", "arm,armv8"; 25 device_type = "cpu"; 26 enable-method = "psci"; 27 operating-points-v2 = <&cpu_opp_table>; 28 reg = <0x0>; 29 cpu-idle-states = <&CPU_SLEEP_0>; 30 }; 31 32 cpu1: cpu@1 { 33 compatible = "arm,cortex-a53", "arm,armv8"; 34 device_type = "cpu"; 35 enable-method = "psci"; 36 reg = <0x1>; 37 operating-points-v2 = <&cpu_opp_table>; 38 cpu-idle-states = <&CPU_SLEEP_0>; 39 }; 40 41 cpu2: cpu@2 { 42 compatible = "arm,cortex-a53", "arm,armv8"; 43 device_type = "cpu"; 44 enable-method = "psci"; 45 reg = <0x2>; 46 operating-points-v2 = <&cpu_opp_table>; 47 cpu-idle-states = <&CPU_SLEEP_0>; 48 }; 49 50 cpu3: cpu@3 { 51 compatible = "arm,cortex-a53", "arm,armv8"; 52 device_type = "cpu"; 53 enable-method = "psci"; 54 reg = <0x3>; 55 operating-points-v2 = <&cpu_opp_table>; 56 cpu-idle-states = <&CPU_SLEEP_0>; 57 }; 58 59 idle-states { 60 entry-method = "arm,psci"; 61 62 CPU_SLEEP_0: cpu-sleep-0 { 63 compatible = "arm,idle-state"; 64 arm,psci-suspend-param = <0x40000000>; 65 local-timer-stop; 66 entry-latency-us = <300>; 67 exit-latency-us = <600>; 68 min-residency-us = <10000>; 69 }; 70 }; 71 }; 72 73 cpu_opp_table: cpu_opp_table { 74 compatible = "operating-points-v2"; 75 opp-shared; 76 opp00 { 77 opp-hz = /bits/ 64 <1199999988>; 78 opp-microvolt = <1000000>; 79 clock-latency-ns = <500000>; 80 }; 81 opp01 { 82 opp-hz = /bits/ 64 <599999994>; 83 opp-microvolt = <1000000>; 84 clock-latency-ns = <500000>; 85 }; 86 opp02 { 87 opp-hz = /bits/ 64 <399999996>; 88 opp-microvolt = <1000000>; 89 clock-latency-ns = <500000>; 90 }; 91 opp03 { 92 opp-hz = /bits/ 64 <299999997>; 93 opp-microvolt = <1000000>; 94 clock-latency-ns = <500000>; 95 }; 96 }; 97 98 dcc: dcc { 99 compatible = "arm,dcc"; 100 status = "disabled"; 101 }; 102 103 pmu { 104 compatible = "arm,armv8-pmuv3"; 105 interrupt-parent = <&gic>; 106 interrupts = <0 143 4>, 107 <0 144 4>, 108 <0 145 4>, 109 <0 146 4>; 110 }; 111 112 psci { 113 compatible = "arm,psci-0.2"; 114 method = "smc"; 115 }; 116 117 timer { 118 compatible = "arm,armv8-timer"; 119 interrupt-parent = <&gic>; 120 interrupts = <1 13 0xf08>, 121 <1 14 0xf08>, 122 <1 11 0xf08>, 123 <1 10 0xf08>; 124 }; 125 126 amba_apu: amba_apu@0 { 127 compatible = "simple-bus"; 128 #address-cells = <2>; 129 #size-cells = <1>; 130 ranges = <0 0 0 0 0xffffffff>; 131 132 gic: interrupt-controller@f9010000 { 133 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 134 #interrupt-cells = <3>; 135 reg = <0x0 0xf9010000 0x10000>, 136 <0x0 0xf9020000 0x20000>, 137 <0x0 0xf9040000 0x20000>, 138 <0x0 0xf9060000 0x20000>; 139 interrupt-controller; 140 interrupt-parent = <&gic>; 141 interrupts = <1 9 0xf04>; 142 }; 143 }; 144 145 amba: amba { 146 compatible = "simple-bus"; 147 #address-cells = <2>; 148 #size-cells = <2>; 149 ranges; 150 151 can0: can@ff060000 { 152 compatible = "xlnx,zynq-can-1.0"; 153 status = "disabled"; 154 clock-names = "can_clk", "pclk"; 155 reg = <0x0 0xff060000 0x0 0x1000>; 156 interrupts = <0 23 4>; 157 interrupt-parent = <&gic>; 158 tx-fifo-depth = <0x40>; 159 rx-fifo-depth = <0x40>; 160 }; 161 162 can1: can@ff070000 { 163 compatible = "xlnx,zynq-can-1.0"; 164 status = "disabled"; 165 clock-names = "can_clk", "pclk"; 166 reg = <0x0 0xff070000 0x0 0x1000>; 167 interrupts = <0 24 4>; 168 interrupt-parent = <&gic>; 169 tx-fifo-depth = <0x40>; 170 rx-fifo-depth = <0x40>; 171 }; 172 173 cci: cci@fd6e0000 { 174 compatible = "arm,cci-400"; 175 reg = <0x0 0xfd6e0000 0x0 0x9000>; 176 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 180 pmu@9000 { 181 compatible = "arm,cci-400-pmu,r1"; 182 reg = <0x9000 0x5000>; 183 interrupt-parent = <&gic>; 184 interrupts = <0 123 4>, 185 <0 123 4>, 186 <0 123 4>, 187 <0 123 4>, 188 <0 123 4>; 189 }; 190 }; 191 192 /* GDMA */ 193 fpd_dma_chan1: dma@fd500000 { 194 status = "disabled"; 195 compatible = "xlnx,zynqmp-dma-1.0"; 196 reg = <0x0 0xfd500000 0x0 0x1000>; 197 interrupt-parent = <&gic>; 198 interrupts = <0 124 4>; 199 clock-names = "clk_main", "clk_apb"; 200 xlnx,bus-width = <128>; 201 }; 202 203 fpd_dma_chan2: dma@fd510000 { 204 status = "disabled"; 205 compatible = "xlnx,zynqmp-dma-1.0"; 206 reg = <0x0 0xfd510000 0x0 0x1000>; 207 interrupt-parent = <&gic>; 208 interrupts = <0 125 4>; 209 clock-names = "clk_main", "clk_apb"; 210 xlnx,bus-width = <128>; 211 }; 212 213 fpd_dma_chan3: dma@fd520000 { 214 status = "disabled"; 215 compatible = "xlnx,zynqmp-dma-1.0"; 216 reg = <0x0 0xfd520000 0x0 0x1000>; 217 interrupt-parent = <&gic>; 218 interrupts = <0 126 4>; 219 clock-names = "clk_main", "clk_apb"; 220 xlnx,bus-width = <128>; 221 }; 222 223 fpd_dma_chan4: dma@fd530000 { 224 status = "disabled"; 225 compatible = "xlnx,zynqmp-dma-1.0"; 226 reg = <0x0 0xfd530000 0x0 0x1000>; 227 interrupt-parent = <&gic>; 228 interrupts = <0 127 4>; 229 clock-names = "clk_main", "clk_apb"; 230 xlnx,bus-width = <128>; 231 }; 232 233 fpd_dma_chan5: dma@fd540000 { 234 status = "disabled"; 235 compatible = "xlnx,zynqmp-dma-1.0"; 236 reg = <0x0 0xfd540000 0x0 0x1000>; 237 interrupt-parent = <&gic>; 238 interrupts = <0 128 4>; 239 clock-names = "clk_main", "clk_apb"; 240 xlnx,bus-width = <128>; 241 }; 242 243 fpd_dma_chan6: dma@fd550000 { 244 status = "disabled"; 245 compatible = "xlnx,zynqmp-dma-1.0"; 246 reg = <0x0 0xfd550000 0x0 0x1000>; 247 interrupt-parent = <&gic>; 248 interrupts = <0 129 4>; 249 clock-names = "clk_main", "clk_apb"; 250 xlnx,bus-width = <128>; 251 }; 252 253 fpd_dma_chan7: dma@fd560000 { 254 status = "disabled"; 255 compatible = "xlnx,zynqmp-dma-1.0"; 256 reg = <0x0 0xfd560000 0x0 0x1000>; 257 interrupt-parent = <&gic>; 258 interrupts = <0 130 4>; 259 clock-names = "clk_main", "clk_apb"; 260 xlnx,bus-width = <128>; 261 }; 262 263 fpd_dma_chan8: dma@fd570000 { 264 status = "disabled"; 265 compatible = "xlnx,zynqmp-dma-1.0"; 266 reg = <0x0 0xfd570000 0x0 0x1000>; 267 interrupt-parent = <&gic>; 268 interrupts = <0 131 4>; 269 clock-names = "clk_main", "clk_apb"; 270 xlnx,bus-width = <128>; 271 }; 272 273 /* LPDDMA default allows only secured access. inorder to enable 274 * These dma channels, Users should ensure that these dma 275 * Channels are allowed for non secure access. 276 */ 277 lpd_dma_chan1: dma@ffa80000 { 278 status = "disabled"; 279 compatible = "xlnx,zynqmp-dma-1.0"; 280 reg = <0x0 0xffa80000 0x0 0x1000>; 281 interrupt-parent = <&gic>; 282 interrupts = <0 77 4>; 283 clock-names = "clk_main", "clk_apb"; 284 xlnx,bus-width = <64>; 285 }; 286 287 lpd_dma_chan2: dma@ffa90000 { 288 status = "disabled"; 289 compatible = "xlnx,zynqmp-dma-1.0"; 290 reg = <0x0 0xffa90000 0x0 0x1000>; 291 interrupt-parent = <&gic>; 292 interrupts = <0 78 4>; 293 clock-names = "clk_main", "clk_apb"; 294 xlnx,bus-width = <64>; 295 }; 296 297 lpd_dma_chan3: dma@ffaa0000 { 298 status = "disabled"; 299 compatible = "xlnx,zynqmp-dma-1.0"; 300 reg = <0x0 0xffaa0000 0x0 0x1000>; 301 interrupt-parent = <&gic>; 302 interrupts = <0 79 4>; 303 clock-names = "clk_main", "clk_apb"; 304 xlnx,bus-width = <64>; 305 }; 306 307 lpd_dma_chan4: dma@ffab0000 { 308 status = "disabled"; 309 compatible = "xlnx,zynqmp-dma-1.0"; 310 reg = <0x0 0xffab0000 0x0 0x1000>; 311 interrupt-parent = <&gic>; 312 interrupts = <0 80 4>; 313 clock-names = "clk_main", "clk_apb"; 314 xlnx,bus-width = <64>; 315 }; 316 317 lpd_dma_chan5: dma@ffac0000 { 318 status = "disabled"; 319 compatible = "xlnx,zynqmp-dma-1.0"; 320 reg = <0x0 0xffac0000 0x0 0x1000>; 321 interrupt-parent = <&gic>; 322 interrupts = <0 81 4>; 323 clock-names = "clk_main", "clk_apb"; 324 xlnx,bus-width = <64>; 325 }; 326 327 lpd_dma_chan6: dma@ffad0000 { 328 status = "disabled"; 329 compatible = "xlnx,zynqmp-dma-1.0"; 330 reg = <0x0 0xffad0000 0x0 0x1000>; 331 interrupt-parent = <&gic>; 332 interrupts = <0 82 4>; 333 clock-names = "clk_main", "clk_apb"; 334 xlnx,bus-width = <64>; 335 }; 336 337 lpd_dma_chan7: dma@ffae0000 { 338 status = "disabled"; 339 compatible = "xlnx,zynqmp-dma-1.0"; 340 reg = <0x0 0xffae0000 0x0 0x1000>; 341 interrupt-parent = <&gic>; 342 interrupts = <0 83 4>; 343 clock-names = "clk_main", "clk_apb"; 344 xlnx,bus-width = <64>; 345 }; 346 347 lpd_dma_chan8: dma@ffaf0000 { 348 status = "disabled"; 349 compatible = "xlnx,zynqmp-dma-1.0"; 350 reg = <0x0 0xffaf0000 0x0 0x1000>; 351 interrupt-parent = <&gic>; 352 interrupts = <0 84 4>; 353 clock-names = "clk_main", "clk_apb"; 354 xlnx,bus-width = <64>; 355 }; 356 357 gem0: ethernet@ff0b0000 { 358 compatible = "cdns,gem"; 359 status = "disabled"; 360 interrupt-parent = <&gic>; 361 interrupts = <0 57 4>, <0 57 4>; 362 reg = <0x0 0xff0b0000 0x0 0x1000>; 363 clock-names = "pclk", "hclk", "tx_clk"; 364 #address-cells = <1>; 365 #size-cells = <0>; 366 }; 367 368 gem1: ethernet@ff0c0000 { 369 compatible = "cdns,gem"; 370 status = "disabled"; 371 interrupt-parent = <&gic>; 372 interrupts = <0 59 4>, <0 59 4>; 373 reg = <0x0 0xff0c0000 0x0 0x1000>; 374 clock-names = "pclk", "hclk", "tx_clk"; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 }; 378 379 gem2: ethernet@ff0d0000 { 380 compatible = "cdns,gem"; 381 status = "disabled"; 382 interrupt-parent = <&gic>; 383 interrupts = <0 61 4>, <0 61 4>; 384 reg = <0x0 0xff0d0000 0x0 0x1000>; 385 clock-names = "pclk", "hclk", "tx_clk"; 386 #address-cells = <1>; 387 #size-cells = <0>; 388 }; 389 390 gem3: ethernet@ff0e0000 { 391 compatible = "cdns,gem"; 392 status = "disabled"; 393 interrupt-parent = <&gic>; 394 interrupts = <0 63 4>, <0 63 4>; 395 reg = <0x0 0xff0e0000 0x0 0x1000>; 396 clock-names = "pclk", "hclk", "tx_clk"; 397 #address-cells = <1>; 398 #size-cells = <0>; 399 }; 400 401 gpio: gpio@ff0a0000 { 402 compatible = "xlnx,zynqmp-gpio-1.0"; 403 status = "disabled"; 404 #gpio-cells = <0x2>; 405 interrupt-parent = <&gic>; 406 interrupts = <0 16 4>; 407 interrupt-controller; 408 #interrupt-cells = <2>; 409 reg = <0x0 0xff0a0000 0x0 0x1000>; 410 }; 411 412 i2c0: i2c@ff020000 { 413 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 414 status = "disabled"; 415 interrupt-parent = <&gic>; 416 interrupts = <0 17 4>; 417 reg = <0x0 0xff020000 0x0 0x1000>; 418 #address-cells = <1>; 419 #size-cells = <0>; 420 }; 421 422 i2c1: i2c@ff030000 { 423 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 424 status = "disabled"; 425 interrupt-parent = <&gic>; 426 interrupts = <0 18 4>; 427 reg = <0x0 0xff030000 0x0 0x1000>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 }; 431 432 pcie: pcie@fd0e0000 { 433 compatible = "xlnx,nwl-pcie-2.11"; 434 status = "disabled"; 435 #address-cells = <3>; 436 #size-cells = <2>; 437 #interrupt-cells = <1>; 438 msi-controller; 439 device_type = "pci"; 440 interrupt-parent = <&gic>; 441 interrupts = <0 118 4>, 442 <0 117 4>, 443 <0 116 4>, 444 <0 115 4>, /* MSI_1 [63...32] */ 445 <0 114 4>; /* MSI_0 [31...0] */ 446 interrupt-names = "misc", "dummy", "intx", 447 "msi1", "msi0"; 448 msi-parent = <&pcie>; 449 reg = <0x0 0xfd0e0000 0x0 0x1000>, 450 <0x0 0xfd480000 0x0 0x1000>, 451 <0x80 0x00000000 0x0 0x1000000>; 452 reg-names = "breg", "pcireg", "cfg"; 453 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 454 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 455 bus-range = <0x00 0xff>; 456 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 457 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 458 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 459 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 460 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 461 pcie_intc: legacy-interrupt-controller { 462 interrupt-controller; 463 #address-cells = <0>; 464 #interrupt-cells = <1>; 465 }; 466 }; 467 468 rtc: rtc@ffa60000 { 469 compatible = "xlnx,zynqmp-rtc"; 470 status = "disabled"; 471 reg = <0x0 0xffa60000 0x0 0x100>; 472 interrupt-parent = <&gic>; 473 interrupts = <0 26 4>, <0 27 4>; 474 interrupt-names = "alarm", "sec"; 475 calibration = <0x8000>; 476 }; 477 478 sata: ahci@fd0c0000 { 479 compatible = "ceva,ahci-1v84"; 480 status = "disabled"; 481 reg = <0x0 0xfd0c0000 0x0 0x2000>; 482 interrupt-parent = <&gic>; 483 interrupts = <0 133 4>; 484 }; 485 486 sdhci0: sdhci@ff160000 { 487 compatible = "arasan,sdhci-8.9a"; 488 status = "disabled"; 489 interrupt-parent = <&gic>; 490 interrupts = <0 48 4>; 491 reg = <0x0 0xff160000 0x0 0x1000>; 492 clock-names = "clk_xin", "clk_ahb"; 493 }; 494 495 sdhci1: sdhci@ff170000 { 496 compatible = "arasan,sdhci-8.9a"; 497 status = "disabled"; 498 interrupt-parent = <&gic>; 499 interrupts = <0 49 4>; 500 reg = <0x0 0xff170000 0x0 0x1000>; 501 clock-names = "clk_xin", "clk_ahb"; 502 }; 503 504 smmu: smmu@fd800000 { 505 compatible = "arm,mmu-500"; 506 reg = <0x0 0xfd800000 0x0 0x20000>; 507 status = "disabled"; 508 #global-interrupts = <1>; 509 interrupt-parent = <&gic>; 510 interrupts = <0 155 4>, 511 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 512 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 513 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 514 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 515 }; 516 517 spi0: spi@ff040000 { 518 compatible = "cdns,spi-r1p6"; 519 status = "disabled"; 520 interrupt-parent = <&gic>; 521 interrupts = <0 19 4>; 522 reg = <0x0 0xff040000 0x0 0x1000>; 523 clock-names = "ref_clk", "pclk"; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 }; 527 528 spi1: spi@ff050000 { 529 compatible = "cdns,spi-r1p6"; 530 status = "disabled"; 531 interrupt-parent = <&gic>; 532 interrupts = <0 20 4>; 533 reg = <0x0 0xff050000 0x0 0x1000>; 534 clock-names = "ref_clk", "pclk"; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 }; 538 539 ttc0: timer@ff110000 { 540 compatible = "cdns,ttc"; 541 status = "disabled"; 542 interrupt-parent = <&gic>; 543 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 544 reg = <0x0 0xff110000 0x0 0x1000>; 545 timer-width = <32>; 546 }; 547 548 ttc1: timer@ff120000 { 549 compatible = "cdns,ttc"; 550 status = "disabled"; 551 interrupt-parent = <&gic>; 552 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 553 reg = <0x0 0xff120000 0x0 0x1000>; 554 timer-width = <32>; 555 }; 556 557 ttc2: timer@ff130000 { 558 compatible = "cdns,ttc"; 559 status = "disabled"; 560 interrupt-parent = <&gic>; 561 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 562 reg = <0x0 0xff130000 0x0 0x1000>; 563 timer-width = <32>; 564 }; 565 566 ttc3: timer@ff140000 { 567 compatible = "cdns,ttc"; 568 status = "disabled"; 569 interrupt-parent = <&gic>; 570 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 571 reg = <0x0 0xff140000 0x0 0x1000>; 572 timer-width = <32>; 573 }; 574 575 uart0: serial@ff000000 { 576 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 577 status = "disabled"; 578 interrupt-parent = <&gic>; 579 interrupts = <0 21 4>; 580 reg = <0x0 0xff000000 0x0 0x1000>; 581 clock-names = "uart_clk", "pclk"; 582 }; 583 584 uart1: serial@ff010000 { 585 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 586 status = "disabled"; 587 interrupt-parent = <&gic>; 588 interrupts = <0 22 4>; 589 reg = <0x0 0xff010000 0x0 0x1000>; 590 clock-names = "uart_clk", "pclk"; 591 }; 592 593 usb0: usb@fe200000 { 594 compatible = "snps,dwc3"; 595 status = "disabled"; 596 interrupt-parent = <&gic>; 597 interrupts = <0 65 4>; 598 reg = <0x0 0xfe200000 0x0 0x40000>; 599 clock-names = "clk_xin", "clk_ahb"; 600 }; 601 602 usb1: usb@fe300000 { 603 compatible = "snps,dwc3"; 604 status = "disabled"; 605 interrupt-parent = <&gic>; 606 interrupts = <0 70 4>; 607 reg = <0x0 0xfe300000 0x0 0x40000>; 608 clock-names = "clk_xin", "clk_ahb"; 609 }; 610 611 watchdog0: watchdog@fd4d0000 { 612 compatible = "cdns,wdt-r1p2"; 613 status = "disabled"; 614 interrupt-parent = <&gic>; 615 interrupts = <0 113 1>; 616 reg = <0x0 0xfd4d0000 0x0 0x1000>; 617 timeout-sec = <10>; 618 }; 619 }; 620}; 621