1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/power/xlnx-zynqmp-power.h> 17#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 18 19/ { 20 compatible = "xlnx,zynqmp"; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 cpus { 25 #address-cells = <1>; 26 #size-cells = <0>; 27 28 cpu0: cpu@0 { 29 compatible = "arm,cortex-a53"; 30 device_type = "cpu"; 31 enable-method = "psci"; 32 operating-points-v2 = <&cpu_opp_table>; 33 reg = <0x0>; 34 cpu-idle-states = <&CPU_SLEEP_0>; 35 }; 36 37 cpu1: cpu@1 { 38 compatible = "arm,cortex-a53"; 39 device_type = "cpu"; 40 enable-method = "psci"; 41 reg = <0x1>; 42 operating-points-v2 = <&cpu_opp_table>; 43 cpu-idle-states = <&CPU_SLEEP_0>; 44 }; 45 46 cpu2: cpu@2 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 enable-method = "psci"; 50 reg = <0x2>; 51 operating-points-v2 = <&cpu_opp_table>; 52 cpu-idle-states = <&CPU_SLEEP_0>; 53 }; 54 55 cpu3: cpu@3 { 56 compatible = "arm,cortex-a53"; 57 device_type = "cpu"; 58 enable-method = "psci"; 59 reg = <0x3>; 60 operating-points-v2 = <&cpu_opp_table>; 61 cpu-idle-states = <&CPU_SLEEP_0>; 62 }; 63 64 idle-states { 65 entry-method = "psci"; 66 67 CPU_SLEEP_0: cpu-sleep-0 { 68 compatible = "arm,idle-state"; 69 arm,psci-suspend-param = <0x40000000>; 70 local-timer-stop; 71 entry-latency-us = <300>; 72 exit-latency-us = <600>; 73 min-residency-us = <10000>; 74 }; 75 }; 76 }; 77 78 cpu_opp_table: cpu-opp-table { 79 compatible = "operating-points-v2"; 80 opp-shared; 81 opp00 { 82 opp-hz = /bits/ 64 <1199999988>; 83 opp-microvolt = <1000000>; 84 clock-latency-ns = <500000>; 85 }; 86 opp01 { 87 opp-hz = /bits/ 64 <599999994>; 88 opp-microvolt = <1000000>; 89 clock-latency-ns = <500000>; 90 }; 91 opp02 { 92 opp-hz = /bits/ 64 <399999996>; 93 opp-microvolt = <1000000>; 94 clock-latency-ns = <500000>; 95 }; 96 opp03 { 97 opp-hz = /bits/ 64 <299999997>; 98 opp-microvolt = <1000000>; 99 clock-latency-ns = <500000>; 100 }; 101 }; 102 103 reserved-memory { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 ranges; 107 108 rproc_0_fw_image: memory@3ed00000 { 109 no-map; 110 reg = <0x0 0x3ed00000 0x0 0x40000>; 111 }; 112 113 rproc_1_fw_image: memory@3ef00000 { 114 no-map; 115 reg = <0x0 0x3ef00000 0x0 0x40000>; 116 }; 117 }; 118 119 zynqmp_ipi: zynqmp_ipi { 120 compatible = "xlnx,zynqmp-ipi-mailbox"; 121 interrupt-parent = <&gic>; 122 interrupts = <0 35 4>; 123 xlnx,ipi-id = <0>; 124 #address-cells = <2>; 125 #size-cells = <2>; 126 ranges; 127 128 ipi_mailbox_pmu1: mailbox@ff990400 { 129 reg = <0x0 0xff9905c0 0x0 0x20>, 130 <0x0 0xff9905e0 0x0 0x20>, 131 <0x0 0xff990e80 0x0 0x20>, 132 <0x0 0xff990ea0 0x0 0x20>; 133 reg-names = "local_request_region", 134 "local_response_region", 135 "remote_request_region", 136 "remote_response_region"; 137 #mbox-cells = <1>; 138 xlnx,ipi-id = <4>; 139 }; 140 }; 141 142 dcc: dcc { 143 compatible = "arm,dcc"; 144 status = "disabled"; 145 }; 146 147 pmu { 148 compatible = "arm,armv8-pmuv3"; 149 interrupt-parent = <&gic>; 150 interrupts = <0 143 4>, 151 <0 144 4>, 152 <0 145 4>, 153 <0 146 4>; 154 }; 155 156 psci { 157 compatible = "arm,psci-0.2"; 158 method = "smc"; 159 }; 160 161 firmware { 162 zynqmp_firmware: zynqmp-firmware { 163 compatible = "xlnx,zynqmp-firmware"; 164 #power-domain-cells = <1>; 165 method = "smc"; 166 167 zynqmp_power: zynqmp-power { 168 compatible = "xlnx,zynqmp-power"; 169 interrupt-parent = <&gic>; 170 interrupts = <0 35 4>; 171 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 172 mbox-names = "tx", "rx"; 173 }; 174 175 nvmem_firmware { 176 compatible = "xlnx,zynqmp-nvmem-fw"; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 180 soc_revision: soc_revision@0 { 181 reg = <0x0 0x4>; 182 }; 183 }; 184 185 zynqmp_pcap: pcap { 186 compatible = "xlnx,zynqmp-pcap-fpga"; 187 }; 188 189 xlnx_aes: zynqmp-aes { 190 compatible = "xlnx,zynqmp-aes"; 191 }; 192 193 zynqmp_reset: reset-controller { 194 compatible = "xlnx,zynqmp-reset"; 195 #reset-cells = <1>; 196 }; 197 198 pinctrl0: pinctrl { 199 compatible = "xlnx,zynqmp-pinctrl"; 200 status = "disabled"; 201 }; 202 }; 203 }; 204 205 timer { 206 compatible = "arm,armv8-timer"; 207 interrupt-parent = <&gic>; 208 interrupts = <1 13 0xf08>, 209 <1 14 0xf08>, 210 <1 11 0xf08>, 211 <1 10 0xf08>; 212 }; 213 214 fpga_full: fpga-full { 215 compatible = "fpga-region"; 216 fpga-mgr = <&zynqmp_pcap>; 217 #address-cells = <2>; 218 #size-cells = <2>; 219 ranges; 220 }; 221 222 remoteproc { 223 compatible = "xlnx,zynqmp-r5fss"; 224 xlnx,cluster-mode = <1>; 225 226 r5f-0 { 227 compatible = "xlnx,zynqmp-r5f"; 228 power-domains = <&zynqmp_firmware PD_RPU_0>; 229 memory-region = <&rproc_0_fw_image>; 230 }; 231 232 r5f-1 { 233 compatible = "xlnx,zynqmp-r5f"; 234 power-domains = <&zynqmp_firmware PD_RPU_1>; 235 memory-region = <&rproc_1_fw_image>; 236 }; 237 }; 238 239 amba: axi { 240 compatible = "simple-bus"; 241 #address-cells = <2>; 242 #size-cells = <2>; 243 ranges; 244 245 can0: can@ff060000 { 246 compatible = "xlnx,zynq-can-1.0"; 247 status = "disabled"; 248 clock-names = "can_clk", "pclk"; 249 reg = <0x0 0xff060000 0x0 0x1000>; 250 interrupts = <0 23 4>; 251 interrupt-parent = <&gic>; 252 tx-fifo-depth = <0x40>; 253 rx-fifo-depth = <0x40>; 254 power-domains = <&zynqmp_firmware PD_CAN_0>; 255 }; 256 257 can1: can@ff070000 { 258 compatible = "xlnx,zynq-can-1.0"; 259 status = "disabled"; 260 clock-names = "can_clk", "pclk"; 261 reg = <0x0 0xff070000 0x0 0x1000>; 262 interrupts = <0 24 4>; 263 interrupt-parent = <&gic>; 264 tx-fifo-depth = <0x40>; 265 rx-fifo-depth = <0x40>; 266 power-domains = <&zynqmp_firmware PD_CAN_1>; 267 }; 268 269 cci: cci@fd6e0000 { 270 compatible = "arm,cci-400"; 271 status = "disabled"; 272 reg = <0x0 0xfd6e0000 0x0 0x9000>; 273 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 274 #address-cells = <1>; 275 #size-cells = <1>; 276 277 pmu@9000 { 278 compatible = "arm,cci-400-pmu,r1"; 279 reg = <0x9000 0x5000>; 280 interrupt-parent = <&gic>; 281 interrupts = <0 123 4>, 282 <0 123 4>, 283 <0 123 4>, 284 <0 123 4>, 285 <0 123 4>; 286 }; 287 }; 288 289 /* GDMA */ 290 fpd_dma_chan1: dma-controller@fd500000 { 291 status = "disabled"; 292 compatible = "xlnx,zynqmp-dma-1.0"; 293 reg = <0x0 0xfd500000 0x0 0x1000>; 294 interrupt-parent = <&gic>; 295 interrupts = <0 124 4>; 296 clock-names = "clk_main", "clk_apb"; 297 #dma-cells = <1>; 298 xlnx,bus-width = <128>; 299 iommus = <&smmu 0x14e8>; 300 power-domains = <&zynqmp_firmware PD_GDMA>; 301 }; 302 303 fpd_dma_chan2: dma-controller@fd510000 { 304 status = "disabled"; 305 compatible = "xlnx,zynqmp-dma-1.0"; 306 reg = <0x0 0xfd510000 0x0 0x1000>; 307 interrupt-parent = <&gic>; 308 interrupts = <0 125 4>; 309 clock-names = "clk_main", "clk_apb"; 310 #dma-cells = <1>; 311 xlnx,bus-width = <128>; 312 iommus = <&smmu 0x14e9>; 313 power-domains = <&zynqmp_firmware PD_GDMA>; 314 }; 315 316 fpd_dma_chan3: dma-controller@fd520000 { 317 status = "disabled"; 318 compatible = "xlnx,zynqmp-dma-1.0"; 319 reg = <0x0 0xfd520000 0x0 0x1000>; 320 interrupt-parent = <&gic>; 321 interrupts = <0 126 4>; 322 clock-names = "clk_main", "clk_apb"; 323 #dma-cells = <1>; 324 xlnx,bus-width = <128>; 325 iommus = <&smmu 0x14ea>; 326 power-domains = <&zynqmp_firmware PD_GDMA>; 327 }; 328 329 fpd_dma_chan4: dma-controller@fd530000 { 330 status = "disabled"; 331 compatible = "xlnx,zynqmp-dma-1.0"; 332 reg = <0x0 0xfd530000 0x0 0x1000>; 333 interrupt-parent = <&gic>; 334 interrupts = <0 127 4>; 335 clock-names = "clk_main", "clk_apb"; 336 #dma-cells = <1>; 337 xlnx,bus-width = <128>; 338 iommus = <&smmu 0x14eb>; 339 power-domains = <&zynqmp_firmware PD_GDMA>; 340 }; 341 342 fpd_dma_chan5: dma-controller@fd540000 { 343 status = "disabled"; 344 compatible = "xlnx,zynqmp-dma-1.0"; 345 reg = <0x0 0xfd540000 0x0 0x1000>; 346 interrupt-parent = <&gic>; 347 interrupts = <0 128 4>; 348 clock-names = "clk_main", "clk_apb"; 349 #dma-cells = <1>; 350 xlnx,bus-width = <128>; 351 iommus = <&smmu 0x14ec>; 352 power-domains = <&zynqmp_firmware PD_GDMA>; 353 }; 354 355 fpd_dma_chan6: dma-controller@fd550000 { 356 status = "disabled"; 357 compatible = "xlnx,zynqmp-dma-1.0"; 358 reg = <0x0 0xfd550000 0x0 0x1000>; 359 interrupt-parent = <&gic>; 360 interrupts = <0 129 4>; 361 clock-names = "clk_main", "clk_apb"; 362 #dma-cells = <1>; 363 xlnx,bus-width = <128>; 364 iommus = <&smmu 0x14ed>; 365 power-domains = <&zynqmp_firmware PD_GDMA>; 366 }; 367 368 fpd_dma_chan7: dma-controller@fd560000 { 369 status = "disabled"; 370 compatible = "xlnx,zynqmp-dma-1.0"; 371 reg = <0x0 0xfd560000 0x0 0x1000>; 372 interrupt-parent = <&gic>; 373 interrupts = <0 130 4>; 374 clock-names = "clk_main", "clk_apb"; 375 #dma-cells = <1>; 376 xlnx,bus-width = <128>; 377 iommus = <&smmu 0x14ee>; 378 power-domains = <&zynqmp_firmware PD_GDMA>; 379 }; 380 381 fpd_dma_chan8: dma-controller@fd570000 { 382 status = "disabled"; 383 compatible = "xlnx,zynqmp-dma-1.0"; 384 reg = <0x0 0xfd570000 0x0 0x1000>; 385 interrupt-parent = <&gic>; 386 interrupts = <0 131 4>; 387 clock-names = "clk_main", "clk_apb"; 388 #dma-cells = <1>; 389 xlnx,bus-width = <128>; 390 iommus = <&smmu 0x14ef>; 391 power-domains = <&zynqmp_firmware PD_GDMA>; 392 }; 393 394 gic: interrupt-controller@f9010000 { 395 compatible = "arm,gic-400"; 396 #address-cells = <0>; 397 #interrupt-cells = <3>; 398 reg = <0x0 0xf9010000 0x0 0x10000>, 399 <0x0 0xf9020000 0x0 0x20000>, 400 <0x0 0xf9040000 0x0 0x20000>, 401 <0x0 0xf9060000 0x0 0x20000>; 402 interrupt-controller; 403 interrupt-parent = <&gic>; 404 interrupts = <1 9 0xf04>; 405 }; 406 407 /* LPDDMA default allows only secured access. inorder to enable 408 * These dma channels, Users should ensure that these dma 409 * Channels are allowed for non secure access. 410 */ 411 lpd_dma_chan1: dma-controller@ffa80000 { 412 status = "disabled"; 413 compatible = "xlnx,zynqmp-dma-1.0"; 414 reg = <0x0 0xffa80000 0x0 0x1000>; 415 interrupt-parent = <&gic>; 416 interrupts = <0 77 4>; 417 clock-names = "clk_main", "clk_apb"; 418 #dma-cells = <1>; 419 xlnx,bus-width = <64>; 420 iommus = <&smmu 0x868>; 421 power-domains = <&zynqmp_firmware PD_ADMA>; 422 }; 423 424 lpd_dma_chan2: dma-controller@ffa90000 { 425 status = "disabled"; 426 compatible = "xlnx,zynqmp-dma-1.0"; 427 reg = <0x0 0xffa90000 0x0 0x1000>; 428 interrupt-parent = <&gic>; 429 interrupts = <0 78 4>; 430 clock-names = "clk_main", "clk_apb"; 431 #dma-cells = <1>; 432 xlnx,bus-width = <64>; 433 iommus = <&smmu 0x869>; 434 power-domains = <&zynqmp_firmware PD_ADMA>; 435 }; 436 437 lpd_dma_chan3: dma-controller@ffaa0000 { 438 status = "disabled"; 439 compatible = "xlnx,zynqmp-dma-1.0"; 440 reg = <0x0 0xffaa0000 0x0 0x1000>; 441 interrupt-parent = <&gic>; 442 interrupts = <0 79 4>; 443 clock-names = "clk_main", "clk_apb"; 444 #dma-cells = <1>; 445 xlnx,bus-width = <64>; 446 iommus = <&smmu 0x86a>; 447 power-domains = <&zynqmp_firmware PD_ADMA>; 448 }; 449 450 lpd_dma_chan4: dma-controller@ffab0000 { 451 status = "disabled"; 452 compatible = "xlnx,zynqmp-dma-1.0"; 453 reg = <0x0 0xffab0000 0x0 0x1000>; 454 interrupt-parent = <&gic>; 455 interrupts = <0 80 4>; 456 clock-names = "clk_main", "clk_apb"; 457 #dma-cells = <1>; 458 xlnx,bus-width = <64>; 459 iommus = <&smmu 0x86b>; 460 power-domains = <&zynqmp_firmware PD_ADMA>; 461 }; 462 463 lpd_dma_chan5: dma-controller@ffac0000 { 464 status = "disabled"; 465 compatible = "xlnx,zynqmp-dma-1.0"; 466 reg = <0x0 0xffac0000 0x0 0x1000>; 467 interrupt-parent = <&gic>; 468 interrupts = <0 81 4>; 469 clock-names = "clk_main", "clk_apb"; 470 #dma-cells = <1>; 471 xlnx,bus-width = <64>; 472 iommus = <&smmu 0x86c>; 473 power-domains = <&zynqmp_firmware PD_ADMA>; 474 }; 475 476 lpd_dma_chan6: dma-controller@ffad0000 { 477 status = "disabled"; 478 compatible = "xlnx,zynqmp-dma-1.0"; 479 reg = <0x0 0xffad0000 0x0 0x1000>; 480 interrupt-parent = <&gic>; 481 interrupts = <0 82 4>; 482 clock-names = "clk_main", "clk_apb"; 483 #dma-cells = <1>; 484 xlnx,bus-width = <64>; 485 iommus = <&smmu 0x86d>; 486 power-domains = <&zynqmp_firmware PD_ADMA>; 487 }; 488 489 lpd_dma_chan7: dma-controller@ffae0000 { 490 status = "disabled"; 491 compatible = "xlnx,zynqmp-dma-1.0"; 492 reg = <0x0 0xffae0000 0x0 0x1000>; 493 interrupt-parent = <&gic>; 494 interrupts = <0 83 4>; 495 clock-names = "clk_main", "clk_apb"; 496 #dma-cells = <1>; 497 xlnx,bus-width = <64>; 498 iommus = <&smmu 0x86e>; 499 power-domains = <&zynqmp_firmware PD_ADMA>; 500 }; 501 502 lpd_dma_chan8: dma-controller@ffaf0000 { 503 status = "disabled"; 504 compatible = "xlnx,zynqmp-dma-1.0"; 505 reg = <0x0 0xffaf0000 0x0 0x1000>; 506 interrupt-parent = <&gic>; 507 interrupts = <0 84 4>; 508 clock-names = "clk_main", "clk_apb"; 509 #dma-cells = <1>; 510 xlnx,bus-width = <64>; 511 iommus = <&smmu 0x86f>; 512 power-domains = <&zynqmp_firmware PD_ADMA>; 513 }; 514 515 mc: memory-controller@fd070000 { 516 compatible = "xlnx,zynqmp-ddrc-2.40a"; 517 reg = <0x0 0xfd070000 0x0 0x30000>; 518 interrupt-parent = <&gic>; 519 interrupts = <0 112 4>; 520 }; 521 522 nand0: nand-controller@ff100000 { 523 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 524 status = "disabled"; 525 reg = <0x0 0xff100000 0x0 0x1000>; 526 clock-names = "controller", "bus"; 527 interrupt-parent = <&gic>; 528 interrupts = <0 14 4>; 529 #address-cells = <1>; 530 #size-cells = <0>; 531 iommus = <&smmu 0x872>; 532 power-domains = <&zynqmp_firmware PD_NAND>; 533 }; 534 535 gem0: ethernet@ff0b0000 { 536 compatible = "cdns,zynqmp-gem", "cdns,gem"; 537 status = "disabled"; 538 interrupt-parent = <&gic>; 539 interrupts = <0 57 4>, <0 57 4>; 540 reg = <0x0 0xff0b0000 0x0 0x1000>; 541 clock-names = "pclk", "hclk", "tx_clk"; 542 #address-cells = <1>; 543 #size-cells = <0>; 544 iommus = <&smmu 0x874>; 545 power-domains = <&zynqmp_firmware PD_ETH_0>; 546 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; 547 reset-names = "gem0_rst"; 548 }; 549 550 gem1: ethernet@ff0c0000 { 551 compatible = "cdns,zynqmp-gem", "cdns,gem"; 552 status = "disabled"; 553 interrupt-parent = <&gic>; 554 interrupts = <0 59 4>, <0 59 4>; 555 reg = <0x0 0xff0c0000 0x0 0x1000>; 556 clock-names = "pclk", "hclk", "tx_clk"; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 iommus = <&smmu 0x875>; 560 power-domains = <&zynqmp_firmware PD_ETH_1>; 561 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 562 reset-names = "gem1_rst"; 563 }; 564 565 gem2: ethernet@ff0d0000 { 566 compatible = "cdns,zynqmp-gem", "cdns,gem"; 567 status = "disabled"; 568 interrupt-parent = <&gic>; 569 interrupts = <0 61 4>, <0 61 4>; 570 reg = <0x0 0xff0d0000 0x0 0x1000>; 571 clock-names = "pclk", "hclk", "tx_clk"; 572 #address-cells = <1>; 573 #size-cells = <0>; 574 iommus = <&smmu 0x876>; 575 power-domains = <&zynqmp_firmware PD_ETH_2>; 576 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; 577 reset-names = "gem2_rst"; 578 }; 579 580 gem3: ethernet@ff0e0000 { 581 compatible = "cdns,zynqmp-gem", "cdns,gem"; 582 status = "disabled"; 583 interrupt-parent = <&gic>; 584 interrupts = <0 63 4>, <0 63 4>; 585 reg = <0x0 0xff0e0000 0x0 0x1000>; 586 clock-names = "pclk", "hclk", "tx_clk"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 iommus = <&smmu 0x877>; 590 power-domains = <&zynqmp_firmware PD_ETH_3>; 591 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; 592 reset-names = "gem3_rst"; 593 }; 594 595 gpio: gpio@ff0a0000 { 596 compatible = "xlnx,zynqmp-gpio-1.0"; 597 status = "disabled"; 598 #address-cells = <0>; 599 #gpio-cells = <0x2>; 600 gpio-controller; 601 interrupt-parent = <&gic>; 602 interrupts = <0 16 4>; 603 interrupt-controller; 604 #interrupt-cells = <2>; 605 reg = <0x0 0xff0a0000 0x0 0x1000>; 606 power-domains = <&zynqmp_firmware PD_GPIO>; 607 }; 608 609 i2c0: i2c@ff020000 { 610 compatible = "cdns,i2c-r1p14"; 611 status = "disabled"; 612 interrupt-parent = <&gic>; 613 interrupts = <0 17 4>; 614 reg = <0x0 0xff020000 0x0 0x1000>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 power-domains = <&zynqmp_firmware PD_I2C_0>; 618 }; 619 620 i2c1: i2c@ff030000 { 621 compatible = "cdns,i2c-r1p14"; 622 status = "disabled"; 623 interrupt-parent = <&gic>; 624 interrupts = <0 18 4>; 625 reg = <0x0 0xff030000 0x0 0x1000>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 power-domains = <&zynqmp_firmware PD_I2C_1>; 629 }; 630 631 pcie: pcie@fd0e0000 { 632 compatible = "xlnx,nwl-pcie-2.11"; 633 status = "disabled"; 634 #address-cells = <3>; 635 #size-cells = <2>; 636 #interrupt-cells = <1>; 637 msi-controller; 638 device_type = "pci"; 639 interrupt-parent = <&gic>; 640 interrupts = <0 118 4>, 641 <0 117 4>, 642 <0 116 4>, 643 <0 115 4>, /* MSI_1 [63...32] */ 644 <0 114 4>; /* MSI_0 [31...0] */ 645 interrupt-names = "misc", "dummy", "intx", 646 "msi1", "msi0"; 647 msi-parent = <&pcie>; 648 reg = <0x0 0xfd0e0000 0x0 0x1000>, 649 <0x0 0xfd480000 0x0 0x1000>, 650 <0x80 0x00000000 0x0 0x1000000>; 651 reg-names = "breg", "pcireg", "cfg"; 652 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 653 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 654 bus-range = <0x00 0xff>; 655 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 656 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 657 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 658 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 659 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 660 iommus = <&smmu 0x4d0>; 661 power-domains = <&zynqmp_firmware PD_PCIE>; 662 pcie_intc: legacy-interrupt-controller { 663 interrupt-controller; 664 #address-cells = <0>; 665 #interrupt-cells = <1>; 666 }; 667 }; 668 669 qspi: spi@ff0f0000 { 670 compatible = "xlnx,zynqmp-qspi-1.0"; 671 status = "disabled"; 672 clock-names = "ref_clk", "pclk"; 673 interrupts = <0 15 4>; 674 interrupt-parent = <&gic>; 675 num-cs = <1>; 676 reg = <0x0 0xff0f0000 0x0 0x1000>, 677 <0x0 0xc0000000 0x0 0x8000000>; 678 #address-cells = <1>; 679 #size-cells = <0>; 680 iommus = <&smmu 0x873>; 681 power-domains = <&zynqmp_firmware PD_QSPI>; 682 }; 683 684 psgtr: phy@fd400000 { 685 compatible = "xlnx,zynqmp-psgtr-v1.1"; 686 status = "disabled"; 687 reg = <0x0 0xfd400000 0x0 0x40000>, 688 <0x0 0xfd3d0000 0x0 0x1000>; 689 reg-names = "serdes", "siou"; 690 #phy-cells = <4>; 691 }; 692 693 rtc: rtc@ffa60000 { 694 compatible = "xlnx,zynqmp-rtc"; 695 status = "disabled"; 696 reg = <0x0 0xffa60000 0x0 0x100>; 697 interrupt-parent = <&gic>; 698 interrupts = <0 26 4>, <0 27 4>; 699 interrupt-names = "alarm", "sec"; 700 calibration = <0x7FFF>; 701 }; 702 703 sata: ahci@fd0c0000 { 704 compatible = "ceva,ahci-1v84"; 705 status = "disabled"; 706 reg = <0x0 0xfd0c0000 0x0 0x2000>; 707 interrupt-parent = <&gic>; 708 interrupts = <0 133 4>; 709 power-domains = <&zynqmp_firmware PD_SATA>; 710 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 711 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, 712 <&smmu 0x4c2>, <&smmu 0x4c3>; 713 }; 714 715 sdhci0: mmc@ff160000 { 716 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 717 status = "disabled"; 718 interrupt-parent = <&gic>; 719 interrupts = <0 48 4>; 720 reg = <0x0 0xff160000 0x0 0x1000>; 721 clock-names = "clk_xin", "clk_ahb"; 722 iommus = <&smmu 0x870>; 723 #clock-cells = <1>; 724 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 725 power-domains = <&zynqmp_firmware PD_SD_0>; 726 }; 727 728 sdhci1: mmc@ff170000 { 729 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 730 status = "disabled"; 731 interrupt-parent = <&gic>; 732 interrupts = <0 49 4>; 733 reg = <0x0 0xff170000 0x0 0x1000>; 734 clock-names = "clk_xin", "clk_ahb"; 735 iommus = <&smmu 0x871>; 736 #clock-cells = <1>; 737 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 738 power-domains = <&zynqmp_firmware PD_SD_1>; 739 }; 740 741 smmu: iommu@fd800000 { 742 compatible = "arm,mmu-500"; 743 reg = <0x0 0xfd800000 0x0 0x20000>; 744 #iommu-cells = <1>; 745 status = "disabled"; 746 #global-interrupts = <1>; 747 interrupt-parent = <&gic>; 748 interrupts = <0 155 4>, 749 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 750 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 751 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 752 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 753 }; 754 755 spi0: spi@ff040000 { 756 compatible = "cdns,spi-r1p6"; 757 status = "disabled"; 758 interrupt-parent = <&gic>; 759 interrupts = <0 19 4>; 760 reg = <0x0 0xff040000 0x0 0x1000>; 761 clock-names = "ref_clk", "pclk"; 762 #address-cells = <1>; 763 #size-cells = <0>; 764 power-domains = <&zynqmp_firmware PD_SPI_0>; 765 }; 766 767 spi1: spi@ff050000 { 768 compatible = "cdns,spi-r1p6"; 769 status = "disabled"; 770 interrupt-parent = <&gic>; 771 interrupts = <0 20 4>; 772 reg = <0x0 0xff050000 0x0 0x1000>; 773 clock-names = "ref_clk", "pclk"; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 power-domains = <&zynqmp_firmware PD_SPI_1>; 777 }; 778 779 ttc0: timer@ff110000 { 780 compatible = "cdns,ttc"; 781 status = "disabled"; 782 interrupt-parent = <&gic>; 783 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 784 reg = <0x0 0xff110000 0x0 0x1000>; 785 timer-width = <32>; 786 power-domains = <&zynqmp_firmware PD_TTC_0>; 787 }; 788 789 ttc1: timer@ff120000 { 790 compatible = "cdns,ttc"; 791 status = "disabled"; 792 interrupt-parent = <&gic>; 793 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 794 reg = <0x0 0xff120000 0x0 0x1000>; 795 timer-width = <32>; 796 power-domains = <&zynqmp_firmware PD_TTC_1>; 797 }; 798 799 ttc2: timer@ff130000 { 800 compatible = "cdns,ttc"; 801 status = "disabled"; 802 interrupt-parent = <&gic>; 803 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 804 reg = <0x0 0xff130000 0x0 0x1000>; 805 timer-width = <32>; 806 power-domains = <&zynqmp_firmware PD_TTC_2>; 807 }; 808 809 ttc3: timer@ff140000 { 810 compatible = "cdns,ttc"; 811 status = "disabled"; 812 interrupt-parent = <&gic>; 813 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 814 reg = <0x0 0xff140000 0x0 0x1000>; 815 timer-width = <32>; 816 power-domains = <&zynqmp_firmware PD_TTC_3>; 817 }; 818 819 uart0: serial@ff000000 { 820 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 821 status = "disabled"; 822 interrupt-parent = <&gic>; 823 interrupts = <0 21 4>; 824 reg = <0x0 0xff000000 0x0 0x1000>; 825 clock-names = "uart_clk", "pclk"; 826 power-domains = <&zynqmp_firmware PD_UART_0>; 827 }; 828 829 uart1: serial@ff010000 { 830 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 831 status = "disabled"; 832 interrupt-parent = <&gic>; 833 interrupts = <0 22 4>; 834 reg = <0x0 0xff010000 0x0 0x1000>; 835 clock-names = "uart_clk", "pclk"; 836 power-domains = <&zynqmp_firmware PD_UART_1>; 837 }; 838 839 usb0: usb@ff9d0000 { 840 #address-cells = <2>; 841 #size-cells = <2>; 842 status = "disabled"; 843 compatible = "xlnx,zynqmp-dwc3"; 844 reg = <0x0 0xff9d0000 0x0 0x100>; 845 power-domains = <&zynqmp_firmware PD_USB_0>; 846 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 847 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 848 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 849 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 850 ranges; 851 852 dwc3_0: usb@fe200000 { 853 compatible = "snps,dwc3"; 854 reg = <0x0 0xfe200000 0x0 0x40000>; 855 interrupt-parent = <&gic>; 856 interrupt-names = "dwc_usb3", "otg"; 857 interrupts = <0 65 4>, <0 69 4>; 858 clock-names = "bus_early", "ref"; 859 iommus = <&smmu 0x860>; 860 snps,quirk-frame-length-adjustment = <0x20>; 861 /* dma-coherent; */ 862 }; 863 }; 864 865 usb1: usb@ff9e0000 { 866 #address-cells = <2>; 867 #size-cells = <2>; 868 status = "disabled"; 869 compatible = "xlnx,zynqmp-dwc3"; 870 reg = <0x0 0xff9e0000 0x0 0x100>; 871 power-domains = <&zynqmp_firmware PD_USB_1>; 872 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 873 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 874 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 875 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 876 ranges; 877 878 dwc3_1: usb@fe300000 { 879 compatible = "snps,dwc3"; 880 reg = <0x0 0xfe300000 0x0 0x40000>; 881 interrupt-parent = <&gic>; 882 interrupt-names = "dwc_usb3", "otg"; 883 interrupts = <0 70 4>, <0 74 4>; 884 clock-names = "bus_early", "ref"; 885 iommus = <&smmu 0x861>; 886 snps,quirk-frame-length-adjustment = <0x20>; 887 /* dma-coherent; */ 888 }; 889 }; 890 891 watchdog0: watchdog@fd4d0000 { 892 compatible = "cdns,wdt-r1p2"; 893 status = "disabled"; 894 interrupt-parent = <&gic>; 895 interrupts = <0 113 1>; 896 reg = <0x0 0xfd4d0000 0x0 0x1000>; 897 timeout-sec = <60>; 898 reset-on-timeout; 899 }; 900 901 lpd_watchdog: watchdog@ff150000 { 902 compatible = "cdns,wdt-r1p2"; 903 status = "disabled"; 904 interrupt-parent = <&gic>; 905 interrupts = <0 52 1>; 906 reg = <0x0 0xff150000 0x0 0x1000>; 907 timeout-sec = <10>; 908 }; 909 910 xilinx_ams: ams@ffa50000 { 911 compatible = "xlnx,zynqmp-ams"; 912 status = "disabled"; 913 interrupt-parent = <&gic>; 914 interrupts = <0 56 4>; 915 reg = <0x0 0xffa50000 0x0 0x800>; 916 #address-cells = <1>; 917 #size-cells = <1>; 918 #io-channel-cells = <1>; 919 ranges = <0 0 0xffa50800 0x800>; 920 921 ams_ps: ams_ps@0 { 922 compatible = "xlnx,zynqmp-ams-ps"; 923 status = "disabled"; 924 reg = <0x0 0x400>; 925 }; 926 927 ams_pl: ams_pl@400 { 928 compatible = "xlnx,zynqmp-ams-pl"; 929 status = "disabled"; 930 reg = <0x400 0x400>; 931 #address-cells = <1>; 932 #size-cells = <0>; 933 }; 934 }; 935 936 zynqmp_dpdma: dma-controller@fd4c0000 { 937 compatible = "xlnx,zynqmp-dpdma"; 938 status = "disabled"; 939 reg = <0x0 0xfd4c0000 0x0 0x1000>; 940 interrupts = <0 122 4>; 941 interrupt-parent = <&gic>; 942 clock-names = "axi_clk"; 943 power-domains = <&zynqmp_firmware PD_DP>; 944 #dma-cells = <1>; 945 }; 946 947 zynqmp_dpsub: display@fd4a0000 { 948 compatible = "xlnx,zynqmp-dpsub-1.7"; 949 status = "disabled"; 950 reg = <0x0 0xfd4a0000 0x0 0x1000>, 951 <0x0 0xfd4aa000 0x0 0x1000>, 952 <0x0 0xfd4ab000 0x0 0x1000>, 953 <0x0 0xfd4ac000 0x0 0x1000>; 954 reg-names = "dp", "blend", "av_buf", "aud"; 955 interrupts = <0 119 4>; 956 interrupt-parent = <&gic>; 957 clock-names = "dp_apb_clk", "dp_aud_clk", 958 "dp_vtc_pixel_clk_in"; 959 power-domains = <&zynqmp_firmware PD_DP>; 960 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 961 dma-names = "vid0", "vid1", "vid2", "gfx0"; 962 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 963 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 964 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 965 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; 966 967 ports { 968 #address-cells = <1>; 969 #size-cells = <0>; 970 971 port@0 { 972 reg = <0>; 973 }; 974 port@1 { 975 reg = <1>; 976 }; 977 port@2 { 978 reg = <2>; 979 }; 980 port@3 { 981 reg = <3>; 982 }; 983 port@4 { 984 reg = <4>; 985 }; 986 port@5 { 987 reg = <5>; 988 }; 989 }; 990 }; 991 }; 992}; 993