1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP
4 *
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 */
14
15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
16#include <dt-bindings/power/xlnx-zynqmp-power.h>
17#include <dt-bindings/reset/xlnx-zynqmp-resets.h>
18
19/ {
20	compatible = "xlnx,zynqmp";
21	#address-cells = <2>;
22	#size-cells = <2>;
23
24	cpus {
25		#address-cells = <1>;
26		#size-cells = <0>;
27
28		cpu0: cpu@0 {
29			compatible = "arm,cortex-a53";
30			device_type = "cpu";
31			enable-method = "psci";
32			operating-points-v2 = <&cpu_opp_table>;
33			reg = <0x0>;
34			cpu-idle-states = <&CPU_SLEEP_0>;
35		};
36
37		cpu1: cpu@1 {
38			compatible = "arm,cortex-a53";
39			device_type = "cpu";
40			enable-method = "psci";
41			reg = <0x1>;
42			operating-points-v2 = <&cpu_opp_table>;
43			cpu-idle-states = <&CPU_SLEEP_0>;
44		};
45
46		cpu2: cpu@2 {
47			compatible = "arm,cortex-a53";
48			device_type = "cpu";
49			enable-method = "psci";
50			reg = <0x2>;
51			operating-points-v2 = <&cpu_opp_table>;
52			cpu-idle-states = <&CPU_SLEEP_0>;
53		};
54
55		cpu3: cpu@3 {
56			compatible = "arm,cortex-a53";
57			device_type = "cpu";
58			enable-method = "psci";
59			reg = <0x3>;
60			operating-points-v2 = <&cpu_opp_table>;
61			cpu-idle-states = <&CPU_SLEEP_0>;
62		};
63
64		idle-states {
65			entry-method = "psci";
66
67			CPU_SLEEP_0: cpu-sleep-0 {
68				compatible = "arm,idle-state";
69				arm,psci-suspend-param = <0x40000000>;
70				local-timer-stop;
71				entry-latency-us = <300>;
72				exit-latency-us = <600>;
73				min-residency-us = <10000>;
74			};
75		};
76	};
77
78	cpu_opp_table: cpu-opp-table {
79		compatible = "operating-points-v2";
80		opp-shared;
81		opp00 {
82			opp-hz = /bits/ 64 <1199999988>;
83			opp-microvolt = <1000000>;
84			clock-latency-ns = <500000>;
85		};
86		opp01 {
87			opp-hz = /bits/ 64 <599999994>;
88			opp-microvolt = <1000000>;
89			clock-latency-ns = <500000>;
90		};
91		opp02 {
92			opp-hz = /bits/ 64 <399999996>;
93			opp-microvolt = <1000000>;
94			clock-latency-ns = <500000>;
95		};
96		opp03 {
97			opp-hz = /bits/ 64 <299999997>;
98			opp-microvolt = <1000000>;
99			clock-latency-ns = <500000>;
100		};
101	};
102
103	zynqmp_ipi: zynqmp_ipi {
104		compatible = "xlnx,zynqmp-ipi-mailbox";
105		interrupt-parent = <&gic>;
106		interrupts = <0 35 4>;
107		xlnx,ipi-id = <0>;
108		#address-cells = <2>;
109		#size-cells = <2>;
110		ranges;
111
112		ipi_mailbox_pmu1: mailbox@ff990400 {
113			reg = <0x0 0xff9905c0 0x0 0x20>,
114			      <0x0 0xff9905e0 0x0 0x20>,
115			      <0x0 0xff990e80 0x0 0x20>,
116			      <0x0 0xff990ea0 0x0 0x20>;
117			reg-names = "local_request_region",
118				    "local_response_region",
119				    "remote_request_region",
120				    "remote_response_region";
121			#mbox-cells = <1>;
122			xlnx,ipi-id = <4>;
123		};
124	};
125
126	dcc: dcc {
127		compatible = "arm,dcc";
128		status = "disabled";
129	};
130
131	pmu {
132		compatible = "arm,armv8-pmuv3";
133		interrupt-parent = <&gic>;
134		interrupts = <0 143 4>,
135			     <0 144 4>,
136			     <0 145 4>,
137			     <0 146 4>;
138	};
139
140	psci {
141		compatible = "arm,psci-0.2";
142		method = "smc";
143	};
144
145	firmware {
146		zynqmp_firmware: zynqmp-firmware {
147			compatible = "xlnx,zynqmp-firmware";
148			#power-domain-cells = <1>;
149			method = "smc";
150
151			zynqmp_power: zynqmp-power {
152				compatible = "xlnx,zynqmp-power";
153				interrupt-parent = <&gic>;
154				interrupts = <0 35 4>;
155				mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>;
156				mbox-names = "tx", "rx";
157			};
158
159			zynqmp_clk: clock-controller {
160				#clock-cells = <1>;
161				compatible = "xlnx,zynqmp-clk";
162				clocks = <&pss_ref_clk>,
163					 <&video_clk>,
164					 <&pss_alt_ref_clk>,
165					 <&aux_ref_clk>,
166					 <&gt_crx_ref_clk>;
167				clock-names = "pss_ref_clk",
168					      "video_clk",
169					      "pss_alt_ref_clk",
170					      "aux_ref_clk",
171					      "gt_crx_ref_clk";
172			};
173
174			nvmem_firmware {
175				compatible = "xlnx,zynqmp-nvmem-fw";
176				#address-cells = <1>;
177				#size-cells = <1>;
178
179				soc_revision: soc_revision@0 {
180					reg = <0x0 0x4>;
181				};
182			};
183
184			zynqmp_pcap: pcap {
185				compatible = "xlnx,zynqmp-pcap-fpga";
186			};
187
188			xlnx_aes: zynqmp-aes {
189				compatible = "xlnx,zynqmp-aes";
190			};
191
192			zynqmp_reset: reset-controller {
193				compatible = "xlnx,zynqmp-reset";
194				#reset-cells = <1>;
195			};
196		};
197	};
198
199	timer {
200		compatible = "arm,armv8-timer";
201		interrupt-parent = <&gic>;
202		interrupts = <1 13 0xf08>,
203			     <1 14 0xf08>,
204			     <1 11 0xf08>,
205			     <1 10 0xf08>;
206	};
207
208	fpga_full: fpga-full {
209		compatible = "fpga-region";
210		fpga-mgr = <&zynqmp_pcap>;
211		#address-cells = <2>;
212		#size-cells = <2>;
213		ranges;
214	};
215
216	amba: axi {
217		compatible = "simple-bus";
218		#address-cells = <2>;
219		#size-cells = <2>;
220		ranges;
221
222		can0: can@ff060000 {
223			compatible = "xlnx,zynq-can-1.0";
224			status = "disabled";
225			clock-names = "can_clk", "pclk";
226			reg = <0x0 0xff060000 0x0 0x1000>;
227			interrupts = <0 23 4>;
228			interrupt-parent = <&gic>;
229			tx-fifo-depth = <0x40>;
230			rx-fifo-depth = <0x40>;
231			power-domains = <&zynqmp_firmware PD_CAN_0>;
232		};
233
234		can1: can@ff070000 {
235			compatible = "xlnx,zynq-can-1.0";
236			status = "disabled";
237			clock-names = "can_clk", "pclk";
238			reg = <0x0 0xff070000 0x0 0x1000>;
239			interrupts = <0 24 4>;
240			interrupt-parent = <&gic>;
241			tx-fifo-depth = <0x40>;
242			rx-fifo-depth = <0x40>;
243			power-domains = <&zynqmp_firmware PD_CAN_1>;
244		};
245
246		cci: cci@fd6e0000 {
247			compatible = "arm,cci-400";
248			reg = <0x0 0xfd6e0000 0x0 0x9000>;
249			ranges = <0x0 0x0 0xfd6e0000 0x10000>;
250			#address-cells = <1>;
251			#size-cells = <1>;
252
253			pmu@9000 {
254				compatible = "arm,cci-400-pmu,r1";
255				reg = <0x9000 0x5000>;
256				interrupt-parent = <&gic>;
257				interrupts = <0 123 4>,
258					     <0 123 4>,
259					     <0 123 4>,
260					     <0 123 4>,
261					     <0 123 4>;
262			};
263		};
264
265		/* GDMA */
266		fpd_dma_chan1: dma@fd500000 {
267			status = "disabled";
268			compatible = "xlnx,zynqmp-dma-1.0";
269			reg = <0x0 0xfd500000 0x0 0x1000>;
270			interrupt-parent = <&gic>;
271			interrupts = <0 124 4>;
272			clock-names = "clk_main", "clk_apb";
273			xlnx,bus-width = <128>;
274			#stream-id-cells = <1>;
275			iommus = <&smmu 0x14e8>;
276			power-domains = <&zynqmp_firmware PD_GDMA>;
277		};
278
279		fpd_dma_chan2: dma@fd510000 {
280			status = "disabled";
281			compatible = "xlnx,zynqmp-dma-1.0";
282			reg = <0x0 0xfd510000 0x0 0x1000>;
283			interrupt-parent = <&gic>;
284			interrupts = <0 125 4>;
285			clock-names = "clk_main", "clk_apb";
286			xlnx,bus-width = <128>;
287			#stream-id-cells = <1>;
288			iommus = <&smmu 0x14e9>;
289			power-domains = <&zynqmp_firmware PD_GDMA>;
290		};
291
292		fpd_dma_chan3: dma@fd520000 {
293			status = "disabled";
294			compatible = "xlnx,zynqmp-dma-1.0";
295			reg = <0x0 0xfd520000 0x0 0x1000>;
296			interrupt-parent = <&gic>;
297			interrupts = <0 126 4>;
298			clock-names = "clk_main", "clk_apb";
299			xlnx,bus-width = <128>;
300			#stream-id-cells = <1>;
301			iommus = <&smmu 0x14ea>;
302			power-domains = <&zynqmp_firmware PD_GDMA>;
303		};
304
305		fpd_dma_chan4: dma@fd530000 {
306			status = "disabled";
307			compatible = "xlnx,zynqmp-dma-1.0";
308			reg = <0x0 0xfd530000 0x0 0x1000>;
309			interrupt-parent = <&gic>;
310			interrupts = <0 127 4>;
311			clock-names = "clk_main", "clk_apb";
312			xlnx,bus-width = <128>;
313			#stream-id-cells = <1>;
314			iommus = <&smmu 0x14eb>;
315			power-domains = <&zynqmp_firmware PD_GDMA>;
316		};
317
318		fpd_dma_chan5: dma@fd540000 {
319			status = "disabled";
320			compatible = "xlnx,zynqmp-dma-1.0";
321			reg = <0x0 0xfd540000 0x0 0x1000>;
322			interrupt-parent = <&gic>;
323			interrupts = <0 128 4>;
324			clock-names = "clk_main", "clk_apb";
325			xlnx,bus-width = <128>;
326			#stream-id-cells = <1>;
327			iommus = <&smmu 0x14ec>;
328			power-domains = <&zynqmp_firmware PD_GDMA>;
329		};
330
331		fpd_dma_chan6: dma@fd550000 {
332			status = "disabled";
333			compatible = "xlnx,zynqmp-dma-1.0";
334			reg = <0x0 0xfd550000 0x0 0x1000>;
335			interrupt-parent = <&gic>;
336			interrupts = <0 129 4>;
337			clock-names = "clk_main", "clk_apb";
338			xlnx,bus-width = <128>;
339			#stream-id-cells = <1>;
340			iommus = <&smmu 0x14ed>;
341			power-domains = <&zynqmp_firmware PD_GDMA>;
342		};
343
344		fpd_dma_chan7: dma@fd560000 {
345			status = "disabled";
346			compatible = "xlnx,zynqmp-dma-1.0";
347			reg = <0x0 0xfd560000 0x0 0x1000>;
348			interrupt-parent = <&gic>;
349			interrupts = <0 130 4>;
350			clock-names = "clk_main", "clk_apb";
351			xlnx,bus-width = <128>;
352			#stream-id-cells = <1>;
353			iommus = <&smmu 0x14ee>;
354			power-domains = <&zynqmp_firmware PD_GDMA>;
355		};
356
357		fpd_dma_chan8: dma@fd570000 {
358			status = "disabled";
359			compatible = "xlnx,zynqmp-dma-1.0";
360			reg = <0x0 0xfd570000 0x0 0x1000>;
361			interrupt-parent = <&gic>;
362			interrupts = <0 131 4>;
363			clock-names = "clk_main", "clk_apb";
364			xlnx,bus-width = <128>;
365			#stream-id-cells = <1>;
366			iommus = <&smmu 0x14ef>;
367			power-domains = <&zynqmp_firmware PD_GDMA>;
368		};
369
370		gic: interrupt-controller@f9010000 {
371			compatible = "arm,gic-400";
372			#address-cells = <0>;
373			#interrupt-cells = <3>;
374			reg = <0x0 0xf9010000 0x0 0x10000>,
375			      <0x0 0xf9020000 0x0 0x20000>,
376			      <0x0 0xf9040000 0x0 0x20000>,
377			      <0x0 0xf9060000 0x0 0x20000>;
378			interrupt-controller;
379			interrupt-parent = <&gic>;
380			interrupts = <1 9 0xf04>;
381		};
382
383		/* LPDDMA default allows only secured access. inorder to enable
384		 * These dma channels, Users should ensure that these dma
385		 * Channels are allowed for non secure access.
386		 */
387		lpd_dma_chan1: dma@ffa80000 {
388			status = "disabled";
389			compatible = "xlnx,zynqmp-dma-1.0";
390			reg = <0x0 0xffa80000 0x0 0x1000>;
391			interrupt-parent = <&gic>;
392			interrupts = <0 77 4>;
393			clock-names = "clk_main", "clk_apb";
394			xlnx,bus-width = <64>;
395			#stream-id-cells = <1>;
396			iommus = <&smmu 0x868>;
397			power-domains = <&zynqmp_firmware PD_ADMA>;
398		};
399
400		lpd_dma_chan2: dma@ffa90000 {
401			status = "disabled";
402			compatible = "xlnx,zynqmp-dma-1.0";
403			reg = <0x0 0xffa90000 0x0 0x1000>;
404			interrupt-parent = <&gic>;
405			interrupts = <0 78 4>;
406			clock-names = "clk_main", "clk_apb";
407			xlnx,bus-width = <64>;
408			#stream-id-cells = <1>;
409			iommus = <&smmu 0x869>;
410			power-domains = <&zynqmp_firmware PD_ADMA>;
411		};
412
413		lpd_dma_chan3: dma@ffaa0000 {
414			status = "disabled";
415			compatible = "xlnx,zynqmp-dma-1.0";
416			reg = <0x0 0xffaa0000 0x0 0x1000>;
417			interrupt-parent = <&gic>;
418			interrupts = <0 79 4>;
419			clock-names = "clk_main", "clk_apb";
420			xlnx,bus-width = <64>;
421			#stream-id-cells = <1>;
422			iommus = <&smmu 0x86a>;
423			power-domains = <&zynqmp_firmware PD_ADMA>;
424		};
425
426		lpd_dma_chan4: dma@ffab0000 {
427			status = "disabled";
428			compatible = "xlnx,zynqmp-dma-1.0";
429			reg = <0x0 0xffab0000 0x0 0x1000>;
430			interrupt-parent = <&gic>;
431			interrupts = <0 80 4>;
432			clock-names = "clk_main", "clk_apb";
433			xlnx,bus-width = <64>;
434			#stream-id-cells = <1>;
435			iommus = <&smmu 0x86b>;
436			power-domains = <&zynqmp_firmware PD_ADMA>;
437		};
438
439		lpd_dma_chan5: dma@ffac0000 {
440			status = "disabled";
441			compatible = "xlnx,zynqmp-dma-1.0";
442			reg = <0x0 0xffac0000 0x0 0x1000>;
443			interrupt-parent = <&gic>;
444			interrupts = <0 81 4>;
445			clock-names = "clk_main", "clk_apb";
446			xlnx,bus-width = <64>;
447			#stream-id-cells = <1>;
448			iommus = <&smmu 0x86c>;
449			power-domains = <&zynqmp_firmware PD_ADMA>;
450		};
451
452		lpd_dma_chan6: dma@ffad0000 {
453			status = "disabled";
454			compatible = "xlnx,zynqmp-dma-1.0";
455			reg = <0x0 0xffad0000 0x0 0x1000>;
456			interrupt-parent = <&gic>;
457			interrupts = <0 82 4>;
458			clock-names = "clk_main", "clk_apb";
459			xlnx,bus-width = <64>;
460			#stream-id-cells = <1>;
461			iommus = <&smmu 0x86d>;
462			power-domains = <&zynqmp_firmware PD_ADMA>;
463		};
464
465		lpd_dma_chan7: dma@ffae0000 {
466			status = "disabled";
467			compatible = "xlnx,zynqmp-dma-1.0";
468			reg = <0x0 0xffae0000 0x0 0x1000>;
469			interrupt-parent = <&gic>;
470			interrupts = <0 83 4>;
471			clock-names = "clk_main", "clk_apb";
472			xlnx,bus-width = <64>;
473			#stream-id-cells = <1>;
474			iommus = <&smmu 0x86e>;
475			power-domains = <&zynqmp_firmware PD_ADMA>;
476		};
477
478		lpd_dma_chan8: dma@ffaf0000 {
479			status = "disabled";
480			compatible = "xlnx,zynqmp-dma-1.0";
481			reg = <0x0 0xffaf0000 0x0 0x1000>;
482			interrupt-parent = <&gic>;
483			interrupts = <0 84 4>;
484			clock-names = "clk_main", "clk_apb";
485			xlnx,bus-width = <64>;
486			#stream-id-cells = <1>;
487			iommus = <&smmu 0x86f>;
488			power-domains = <&zynqmp_firmware PD_ADMA>;
489		};
490
491		mc: memory-controller@fd070000 {
492			compatible = "xlnx,zynqmp-ddrc-2.40a";
493			reg = <0x0 0xfd070000 0x0 0x30000>;
494			interrupt-parent = <&gic>;
495			interrupts = <0 112 4>;
496		};
497
498		nand0: nand-controller@ff100000 {
499			compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10";
500			status = "disabled";
501			reg = <0x0 0xff100000 0x0 0x1000>;
502			clock-names = "controller", "bus";
503			interrupt-parent = <&gic>;
504			interrupts = <0 14 4>;
505			#address-cells = <1>;
506			#size-cells = <0>;
507			#stream-id-cells = <1>;
508			iommus = <&smmu 0x872>;
509			power-domains = <&zynqmp_firmware PD_NAND>;
510		};
511
512		gem0: ethernet@ff0b0000 {
513			compatible = "cdns,zynqmp-gem", "cdns,gem";
514			status = "disabled";
515			interrupt-parent = <&gic>;
516			interrupts = <0 57 4>, <0 57 4>;
517			reg = <0x0 0xff0b0000 0x0 0x1000>;
518			clock-names = "pclk", "hclk", "tx_clk";
519			#address-cells = <1>;
520			#size-cells = <0>;
521			#stream-id-cells = <1>;
522			iommus = <&smmu 0x874>;
523			power-domains = <&zynqmp_firmware PD_ETH_0>;
524		};
525
526		gem1: ethernet@ff0c0000 {
527			compatible = "cdns,zynqmp-gem", "cdns,gem";
528			status = "disabled";
529			interrupt-parent = <&gic>;
530			interrupts = <0 59 4>, <0 59 4>;
531			reg = <0x0 0xff0c0000 0x0 0x1000>;
532			clock-names = "pclk", "hclk", "tx_clk";
533			#address-cells = <1>;
534			#size-cells = <0>;
535			#stream-id-cells = <1>;
536			iommus = <&smmu 0x875>;
537			power-domains = <&zynqmp_firmware PD_ETH_1>;
538		};
539
540		gem2: ethernet@ff0d0000 {
541			compatible = "cdns,zynqmp-gem", "cdns,gem";
542			status = "disabled";
543			interrupt-parent = <&gic>;
544			interrupts = <0 61 4>, <0 61 4>;
545			reg = <0x0 0xff0d0000 0x0 0x1000>;
546			clock-names = "pclk", "hclk", "tx_clk";
547			#address-cells = <1>;
548			#size-cells = <0>;
549			#stream-id-cells = <1>;
550			iommus = <&smmu 0x876>;
551			power-domains = <&zynqmp_firmware PD_ETH_2>;
552		};
553
554		gem3: ethernet@ff0e0000 {
555			compatible = "cdns,zynqmp-gem", "cdns,gem";
556			status = "disabled";
557			interrupt-parent = <&gic>;
558			interrupts = <0 63 4>, <0 63 4>;
559			reg = <0x0 0xff0e0000 0x0 0x1000>;
560			clock-names = "pclk", "hclk", "tx_clk";
561			#address-cells = <1>;
562			#size-cells = <0>;
563			#stream-id-cells = <1>;
564			iommus = <&smmu 0x877>;
565			power-domains = <&zynqmp_firmware PD_ETH_3>;
566		};
567
568		gpio: gpio@ff0a0000 {
569			compatible = "xlnx,zynqmp-gpio-1.0";
570			status = "disabled";
571			#address-cells = <0>;
572			#gpio-cells = <0x2>;
573			gpio-controller;
574			interrupt-parent = <&gic>;
575			interrupts = <0 16 4>;
576			interrupt-controller;
577			#interrupt-cells = <2>;
578			reg = <0x0 0xff0a0000 0x0 0x1000>;
579			power-domains = <&zynqmp_firmware PD_GPIO>;
580		};
581
582		i2c0: i2c@ff020000 {
583			compatible = "cdns,i2c-r1p14";
584			status = "disabled";
585			interrupt-parent = <&gic>;
586			interrupts = <0 17 4>;
587			reg = <0x0 0xff020000 0x0 0x1000>;
588			#address-cells = <1>;
589			#size-cells = <0>;
590			power-domains = <&zynqmp_firmware PD_I2C_0>;
591		};
592
593		i2c1: i2c@ff030000 {
594			compatible = "cdns,i2c-r1p14";
595			status = "disabled";
596			interrupt-parent = <&gic>;
597			interrupts = <0 18 4>;
598			reg = <0x0 0xff030000 0x0 0x1000>;
599			#address-cells = <1>;
600			#size-cells = <0>;
601			power-domains = <&zynqmp_firmware PD_I2C_1>;
602		};
603
604		pcie: pcie@fd0e0000 {
605			compatible = "xlnx,nwl-pcie-2.11";
606			status = "disabled";
607			#address-cells = <3>;
608			#size-cells = <2>;
609			#interrupt-cells = <1>;
610			msi-controller;
611			device_type = "pci";
612			interrupt-parent = <&gic>;
613			interrupts = <0 118 4>,
614				     <0 117 4>,
615				     <0 116 4>,
616				     <0 115 4>,	/* MSI_1 [63...32] */
617				     <0 114 4>;	/* MSI_0 [31...0] */
618			interrupt-names = "misc", "dummy", "intx",
619					  "msi1", "msi0";
620			msi-parent = <&pcie>;
621			reg = <0x0 0xfd0e0000 0x0 0x1000>,
622			      <0x0 0xfd480000 0x0 0x1000>,
623			      <0x80 0x00000000 0x0 0x1000000>;
624			reg-names = "breg", "pcireg", "cfg";
625			ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
626				 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
627			bus-range = <0x00 0xff>;
628			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
629			interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
630					<0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
631					<0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
632					<0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
633			power-domains = <&zynqmp_firmware PD_PCIE>;
634			pcie_intc: legacy-interrupt-controller {
635				interrupt-controller;
636				#address-cells = <0>;
637				#interrupt-cells = <1>;
638			};
639		};
640
641		qspi: spi@ff0f0000 {
642			compatible = "xlnx,zynqmp-qspi-1.0";
643			status = "disabled";
644			clock-names = "ref_clk", "pclk";
645			interrupts = <0 15 4>;
646			interrupt-parent = <&gic>;
647			num-cs = <1>;
648			reg = <0x0 0xff0f0000 0x0 0x1000>,
649			      <0x0 0xc0000000 0x0 0x8000000>;
650			#address-cells = <1>;
651			#size-cells = <0>;
652			#stream-id-cells = <1>;
653			iommus = <&smmu 0x873>;
654			power-domains = <&zynqmp_firmware PD_QSPI>;
655		};
656
657		psgtr: phy@fd400000 {
658			compatible = "xlnx,zynqmp-psgtr-v1.1";
659			status = "disabled";
660			reg = <0x0 0xfd400000 0x0 0x40000>,
661			      <0x0 0xfd3d0000 0x0 0x1000>;
662			reg-names = "serdes", "siou";
663			#phy-cells = <4>;
664		};
665
666		rtc: rtc@ffa60000 {
667			compatible = "xlnx,zynqmp-rtc";
668			status = "disabled";
669			reg = <0x0 0xffa60000 0x0 0x100>;
670			interrupt-parent = <&gic>;
671			interrupts = <0 26 4>, <0 27 4>;
672			interrupt-names = "alarm", "sec";
673			calibration = <0x8000>;
674		};
675
676		sata: ahci@fd0c0000 {
677			compatible = "ceva,ahci-1v84";
678			status = "disabled";
679			reg = <0x0 0xfd0c0000 0x0 0x2000>;
680			interrupt-parent = <&gic>;
681			interrupts = <0 133 4>;
682			power-domains = <&zynqmp_firmware PD_SATA>;
683			#stream-id-cells = <4>;
684			iommus = <&smmu 0x4c0>, <&smmu 0x4c1>,
685				 <&smmu 0x4c2>, <&smmu 0x4c3>;
686		};
687
688		sdhci0: mmc@ff160000 {
689			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
690			status = "disabled";
691			interrupt-parent = <&gic>;
692			interrupts = <0 48 4>;
693			reg = <0x0 0xff160000 0x0 0x1000>;
694			clock-names = "clk_xin", "clk_ahb";
695			#stream-id-cells = <1>;
696			iommus = <&smmu 0x870>;
697			#clock-cells = <1>;
698			clock-output-names = "clk_out_sd0", "clk_in_sd0";
699			power-domains = <&zynqmp_firmware PD_SD_0>;
700		};
701
702		sdhci1: mmc@ff170000 {
703			compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
704			status = "disabled";
705			interrupt-parent = <&gic>;
706			interrupts = <0 49 4>;
707			reg = <0x0 0xff170000 0x0 0x1000>;
708			clock-names = "clk_xin", "clk_ahb";
709			#stream-id-cells = <1>;
710			iommus = <&smmu 0x871>;
711			#clock-cells = <1>;
712			clock-output-names = "clk_out_sd1", "clk_in_sd1";
713			power-domains = <&zynqmp_firmware PD_SD_1>;
714		};
715
716		smmu: iommu@fd800000 {
717			compatible = "arm,mmu-500";
718			reg = <0x0 0xfd800000 0x0 0x20000>;
719			#iommu-cells = <1>;
720			status = "disabled";
721			#global-interrupts = <1>;
722			interrupt-parent = <&gic>;
723			interrupts = <0 155 4>,
724				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
725				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
726				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
727				<0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
728		};
729
730		spi0: spi@ff040000 {
731			compatible = "cdns,spi-r1p6";
732			status = "disabled";
733			interrupt-parent = <&gic>;
734			interrupts = <0 19 4>;
735			reg = <0x0 0xff040000 0x0 0x1000>;
736			clock-names = "ref_clk", "pclk";
737			#address-cells = <1>;
738			#size-cells = <0>;
739			power-domains = <&zynqmp_firmware PD_SPI_0>;
740		};
741
742		spi1: spi@ff050000 {
743			compatible = "cdns,spi-r1p6";
744			status = "disabled";
745			interrupt-parent = <&gic>;
746			interrupts = <0 20 4>;
747			reg = <0x0 0xff050000 0x0 0x1000>;
748			clock-names = "ref_clk", "pclk";
749			#address-cells = <1>;
750			#size-cells = <0>;
751			power-domains = <&zynqmp_firmware PD_SPI_1>;
752		};
753
754		ttc0: timer@ff110000 {
755			compatible = "cdns,ttc";
756			status = "disabled";
757			interrupt-parent = <&gic>;
758			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
759			reg = <0x0 0xff110000 0x0 0x1000>;
760			timer-width = <32>;
761			power-domains = <&zynqmp_firmware PD_TTC_0>;
762		};
763
764		ttc1: timer@ff120000 {
765			compatible = "cdns,ttc";
766			status = "disabled";
767			interrupt-parent = <&gic>;
768			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
769			reg = <0x0 0xff120000 0x0 0x1000>;
770			timer-width = <32>;
771			power-domains = <&zynqmp_firmware PD_TTC_1>;
772		};
773
774		ttc2: timer@ff130000 {
775			compatible = "cdns,ttc";
776			status = "disabled";
777			interrupt-parent = <&gic>;
778			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
779			reg = <0x0 0xff130000 0x0 0x1000>;
780			timer-width = <32>;
781			power-domains = <&zynqmp_firmware PD_TTC_2>;
782		};
783
784		ttc3: timer@ff140000 {
785			compatible = "cdns,ttc";
786			status = "disabled";
787			interrupt-parent = <&gic>;
788			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
789			reg = <0x0 0xff140000 0x0 0x1000>;
790			timer-width = <32>;
791			power-domains = <&zynqmp_firmware PD_TTC_3>;
792		};
793
794		uart0: serial@ff000000 {
795			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
796			status = "disabled";
797			interrupt-parent = <&gic>;
798			interrupts = <0 21 4>;
799			reg = <0x0 0xff000000 0x0 0x1000>;
800			clock-names = "uart_clk", "pclk";
801			power-domains = <&zynqmp_firmware PD_UART_0>;
802		};
803
804		uart1: serial@ff010000 {
805			compatible = "cdns,uart-r1p12", "xlnx,xuartps";
806			status = "disabled";
807			interrupt-parent = <&gic>;
808			interrupts = <0 22 4>;
809			reg = <0x0 0xff010000 0x0 0x1000>;
810			clock-names = "uart_clk", "pclk";
811			power-domains = <&zynqmp_firmware PD_UART_1>;
812		};
813
814		usb0: usb@fe200000 {
815			compatible = "snps,dwc3";
816			status = "disabled";
817			interrupt-parent = <&gic>;
818			interrupts = <0 65 4>;
819			reg = <0x0 0xfe200000 0x0 0x40000>;
820			clock-names = "clk_xin", "clk_ahb";
821			power-domains = <&zynqmp_firmware PD_USB_0>;
822		};
823
824		usb1: usb@fe300000 {
825			compatible = "snps,dwc3";
826			status = "disabled";
827			interrupt-parent = <&gic>;
828			interrupts = <0 70 4>;
829			reg = <0x0 0xfe300000 0x0 0x40000>;
830			clock-names = "clk_xin", "clk_ahb";
831			power-domains = <&zynqmp_firmware PD_USB_1>;
832		};
833
834		watchdog0: watchdog@fd4d0000 {
835			compatible = "cdns,wdt-r1p2";
836			status = "disabled";
837			interrupt-parent = <&gic>;
838			interrupts = <0 113 1>;
839			reg = <0x0 0xfd4d0000 0x0 0x1000>;
840			timeout-sec = <10>;
841		};
842
843		lpd_watchdog: watchdog@ff150000 {
844			compatible = "cdns,wdt-r1p2";
845			status = "disabled";
846			interrupt-parent = <&gic>;
847			interrupts = <0 52 1>;
848			reg = <0x0 0xff150000 0x0 0x1000>;
849			timeout-sec = <10>;
850		};
851
852		zynqmp_dpdma: dma-controller@fd4c0000 {
853			compatible = "xlnx,zynqmp-dpdma";
854			status = "disabled";
855			reg = <0x0 0xfd4c0000 0x0 0x1000>;
856			interrupts = <0 122 4>;
857			interrupt-parent = <&gic>;
858			clock-names = "axi_clk";
859			power-domains = <&zynqmp_firmware PD_DP>;
860			#dma-cells = <1>;
861		};
862
863		zynqmp_dpsub: display@fd4a0000 {
864			compatible = "xlnx,zynqmp-dpsub-1.7";
865			status = "disabled";
866			reg = <0x0 0xfd4a0000 0x0 0x1000>,
867			      <0x0 0xfd4aa000 0x0 0x1000>,
868			      <0x0 0xfd4ab000 0x0 0x1000>,
869			      <0x0 0xfd4ac000 0x0 0x1000>;
870			reg-names = "dp", "blend", "av_buf", "aud";
871			interrupts = <0 119 4>;
872			interrupt-parent = <&gic>;
873			clock-names = "dp_apb_clk", "dp_aud_clk",
874				      "dp_vtc_pixel_clk_in";
875			power-domains = <&zynqmp_firmware PD_DP>;
876			resets = <&zynqmp_reset ZYNQMP_RESET_DP>;
877			dma-names = "vid0", "vid1", "vid2", "gfx0";
878			dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>,
879			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>,
880			       <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>,
881			       <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>;
882		};
883	};
884};
885