1/*
2 * dts file for Xilinx ZynqMP
3 *
4 * (C) Copyright 2014 - 2015, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14/ {
15	compatible = "xlnx,zynqmp";
16	#address-cells = <2>;
17	#size-cells = <1>;
18
19	cpus {
20		#address-cells = <1>;
21		#size-cells = <0>;
22
23		cpu@0 {
24			compatible = "arm,cortex-a53", "arm,armv8";
25			device_type = "cpu";
26			enable-method = "psci";
27			reg = <0x0>;
28		};
29
30		cpu@1 {
31			compatible = "arm,cortex-a53", "arm,armv8";
32			device_type = "cpu";
33			enable-method = "psci";
34			reg = <0x1>;
35		};
36
37		cpu@2 {
38			compatible = "arm,cortex-a53", "arm,armv8";
39			device_type = "cpu";
40			enable-method = "psci";
41			reg = <0x2>;
42		};
43
44		cpu@3 {
45			compatible = "arm,cortex-a53", "arm,armv8";
46			device_type = "cpu";
47			enable-method = "psci";
48			reg = <0x3>;
49		};
50	};
51
52	pmu {
53		compatible = "arm,armv8-pmuv3";
54		interrupts = <0 143 4>,
55			     <0 144 4>,
56			     <0 145 4>,
57			     <0 146 4>;
58	};
59
60	psci {
61		compatible = "arm,psci-0.2";
62		method = "smc";
63	};
64
65	timer {
66		compatible = "arm,armv8-timer";
67		interrupt-parent = <&gic>;
68		interrupts = <1 13 0xf01>,
69			     <1 14 0xf01>,
70			     <1 11 0xf01>,
71			     <1 10 0xf01>;
72	};
73
74	amba_apu {
75		compatible = "simple-bus";
76		#address-cells = <2>;
77		#size-cells = <1>;
78		ranges;
79
80		gic: interrupt-controller@f9010000 {
81			compatible = "arm,gic-400", "arm,cortex-a15-gic";
82			#interrupt-cells = <3>;
83			reg = <0x0 0xf9010000 0x10000>,
84			      <0x0 0xf902f000 0x2000>,
85			      <0x0 0xf9040000 0x20000>,
86			      <0x0 0xf906f000 0x2000>;
87			interrupt-controller;
88			interrupt-parent = <&gic>;
89			interrupts = <1 9 0xf04>;
90		};
91	};
92
93	amba {
94		compatible = "simple-bus";
95		#address-cells = <2>;
96		#size-cells = <1>;
97		ranges;
98
99		can0: can@ff060000 {
100			compatible = "xlnx,zynq-can-1.0";
101			status = "disabled";
102			clocks = <&misc_clk &misc_clk>;
103			clock-names = "can_clk", "pclk";
104			reg = <0x0 0xff060000 0x1000>;
105			interrupts = <0 23 4>;
106			interrupt-parent = <&gic>;
107			tx-fifo-depth = <0x40>;
108			rx-fifo-depth = <0x40>;
109		};
110
111		can1: can@ff070000 {
112			compatible = "xlnx,zynq-can-1.0";
113			status = "disabled";
114			clocks = <&misc_clk &misc_clk>;
115			clock-names = "can_clk", "pclk";
116			reg = <0x0 0xff070000 0x1000>;
117			interrupts = <0 24 4>;
118			interrupt-parent = <&gic>;
119			tx-fifo-depth = <0x40>;
120			rx-fifo-depth = <0x40>;
121		};
122
123		misc_clk: misc_clk {
124			compatible = "fixed-clock";
125			#clock-cells = <0>;
126			clock-frequency = <25000000>;
127		};
128
129		gpio: gpio@ff0a0000 {
130			compatible = "xlnx,zynqmp-gpio-1.0";
131			status = "disabled";
132			#gpio-cells = <0x2>;
133			clocks = <&misc_clk>;
134			interrupt-parent = <&gic>;
135			interrupts = <0 16 4>;
136			interrupt-controller;
137			#interrupt-cells = <2>;
138			reg = <0x0 0xff0a0000 0x1000>;
139		};
140
141		gem0: ethernet@ff0b0000 {
142			compatible = "cdns,gem";
143			status = "disabled";
144			interrupt-parent = <&gic>;
145			interrupts = <0 57 4>, <0 57 4>;
146			reg = <0x0 0xff0b0000 0x1000>;
147			clock-names = "pclk", "hclk", "tx_clk";
148			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
149			#address-cells = <1>;
150			#size-cells = <0>;
151		};
152
153		gem1: ethernet@ff0c0000 {
154			compatible = "cdns,gem";
155			status = "disabled";
156			interrupt-parent = <&gic>;
157			interrupts = <0 59 4>, <0 59 4>;
158			reg = <0x0 0xff0c0000 0x1000>;
159			clock-names = "pclk", "hclk", "tx_clk";
160			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
161			#address-cells = <1>;
162			#size-cells = <0>;
163		};
164
165		gem2: ethernet@ff0d0000 {
166			compatible = "cdns,gem";
167			status = "disabled";
168			interrupt-parent = <&gic>;
169			interrupts = <0 61 4>, <0 61 4>;
170			reg = <0x0 0xff0d0000 0x1000>;
171			clock-names = "pclk", "hclk", "tx_clk";
172			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
173			#address-cells = <1>;
174			#size-cells = <0>;
175		};
176
177		gem3: ethernet@ff0e0000 {
178			compatible = "cdns,gem";
179			status = "disabled";
180			interrupt-parent = <&gic>;
181			interrupts = <0 63 4>, <0 63 4>;
182			reg = <0x0 0xff0e0000 0x1000>;
183			clock-names = "pclk", "hclk", "tx_clk";
184			clocks = <&misc_clk>, <&misc_clk>, <&misc_clk>;
185			#address-cells = <1>;
186			#size-cells = <0>;
187		};
188
189		i2c_clk: i2c_clk {
190			compatible = "fixed-clock";
191			#clock-cells = <0x0>;
192			clock-frequency = <111111111>;
193		};
194
195		i2c0: i2c@ff020000 {
196			compatible = "cdns,i2c-r1p10";
197			status = "disabled";
198			interrupt-parent = <&gic>;
199			interrupts = <0 17 4>;
200			reg = <0x0 0xff020000 0x1000>;
201			clocks = <&i2c_clk>;
202			#address-cells = <1>;
203			#size-cells = <0>;
204		};
205
206		i2c1: i2c@ff030000 {
207			compatible = "cdns,i2c-r1p10";
208			status = "disabled";
209			interrupt-parent = <&gic>;
210			interrupts = <0 18 4>;
211			reg = <0x0 0xff030000 0x1000>;
212			clocks = <&i2c_clk>;
213			#address-cells = <1>;
214			#size-cells = <0>;
215		};
216
217		sata_clk: sata_clk {
218			compatible = "fixed-clock";
219			#clock-cells = <0>;
220			clock-frequency = <75000000>;
221		};
222
223		sata: ahci@fd0c0000 {
224			compatible = "ceva,ahci-1v84";
225			status = "disabled";
226			reg = <0x0 0xfd0c0000 0x2000>;
227			interrupt-parent = <&gic>;
228			interrupts = <0 133 4>;
229			clocks = <&sata_clk>;
230		};
231
232		sdhci0: sdhci@ff160000 {
233			compatible = "arasan,sdhci-8.9a";
234			status = "disabled";
235			interrupt-parent = <&gic>;
236			interrupts = <0 48 4>;
237			reg = <0x0 0xff160000 0x1000>;
238			clock-names = "clk_xin", "clk_ahb";
239			clocks = <&misc_clk>, <&misc_clk>;
240		};
241
242		sdhci1: sdhci@ff170000 {
243			compatible = "arasan,sdhci-8.9a";
244			status = "disabled";
245			interrupt-parent = <&gic>;
246			interrupts = <0 49 4>;
247			reg = <0x0 0xff170000 0x1000>;
248			clock-names = "clk_xin", "clk_ahb";
249			clocks = <&misc_clk>, <&misc_clk>;
250		};
251
252		smmu: smmu@fd800000 {
253			compatible = "arm,mmu-500";
254			reg = <0x0 0xfd800000 0x20000>;
255			#global-interrupts = <1>;
256			interrupt-parent = <&gic>;
257			interrupts = <0 157 4>,
258				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
259				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
260				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>,
261				<0 157 4>, <0 157 4>, <0 157 4>, <0 157 4>;
262		};
263
264		spi0: spi@ff040000 {
265			compatible = "cdns,spi-r1p6";
266			status = "disabled";
267			interrupt-parent = <&gic>;
268			interrupts = <0 19 4>;
269			reg = <0x0 0xff040000 0x1000>;
270			clock-names = "ref_clk", "pclk";
271			clocks = <&misc_clk &misc_clk>;
272			#address-cells = <1>;
273			#size-cells = <0>;
274		};
275
276		spi1: spi@ff050000 {
277			compatible = "cdns,spi-r1p6";
278			status = "disabled";
279			interrupt-parent = <&gic>;
280			interrupts = <0 20 4>;
281			reg = <0x0 0xff050000 0x1000>;
282			clock-names = "ref_clk", "pclk";
283			clocks = <&misc_clk &misc_clk>;
284			#address-cells = <1>;
285			#size-cells = <0>;
286		};
287
288		ttc0: timer@ff110000 {
289			compatible = "cdns,ttc";
290			status = "disabled";
291			interrupt-parent = <&gic>;
292			interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
293			reg = <0x0 0xff110000 0x1000>;
294			clocks = <&misc_clk>;
295			timer-width = <32>;
296		};
297
298		ttc1: timer@ff120000 {
299			compatible = "cdns,ttc";
300			status = "disabled";
301			interrupt-parent = <&gic>;
302			interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
303			reg = <0x0 0xff120000 0x1000>;
304			clocks = <&misc_clk>;
305			timer-width = <32>;
306		};
307
308		ttc2: timer@ff130000 {
309			compatible = "cdns,ttc";
310			status = "disabled";
311			interrupt-parent = <&gic>;
312			interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
313			reg = <0x0 0xff130000 0x1000>;
314			clocks = <&misc_clk>;
315			timer-width = <32>;
316		};
317
318		ttc3: timer@ff140000 {
319			compatible = "cdns,ttc";
320			status = "disabled";
321			interrupt-parent = <&gic>;
322			interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
323			reg = <0x0 0xff140000 0x1000>;
324			clocks = <&misc_clk>;
325			timer-width = <32>;
326		};
327
328		uart0: serial@ff000000 {
329			compatible = "cdns,uart-r1p8";
330			status = "disabled";
331			interrupt-parent = <&gic>;
332			interrupts = <0 21 4>;
333			reg = <0x0 0xff000000 0x1000>;
334			clock-names = "uart_clk", "pclk";
335			clocks = <&misc_clk &misc_clk>;
336		};
337
338		uart1: serial@ff010000 {
339			compatible = "cdns,uart-r1p8";
340			status = "disabled";
341			interrupt-parent = <&gic>;
342			interrupts = <0 22 4>;
343			reg = <0x0 0xff010000 0x1000>;
344			clock-names = "uart_clk", "pclk";
345			clocks = <&misc_clk &misc_clk>;
346		};
347
348		usb0: usb@fe200000 {
349			compatible = "snps,dwc3";
350			status = "disabled";
351			interrupt-parent = <&gic>;
352			interrupts = <0 65 4>;
353			reg = <0x0 0xfe200000 0x40000>;
354			clock-names = "clk_xin", "clk_ahb";
355			clocks = <&misc_clk>, <&misc_clk>;
356		};
357
358		usb1: usb@fe300000 {
359			compatible = "snps,dwc3";
360			status = "disabled";
361			interrupt-parent = <&gic>;
362			interrupts = <0 70 4>;
363			reg = <0x0 0xfe300000 0x40000>;
364			clock-names = "clk_xin", "clk_ahb";
365			clocks = <&misc_clk>, <&misc_clk>;
366		};
367
368		watchdog0: watchdog@fd4d0000 {
369			compatible = "cdns,wdt-r1p2";
370			status = "disabled";
371			clocks= <&misc_clk>;
372			interrupt-parent = <&gic>;
373			interrupts = <0 52 1>;
374			reg = <0x0 0xfd4d0000 0x1000>;
375			timeout-sec = <10>;
376		};
377	};
378};
379