1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2019, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/power/xlnx-zynqmp-power.h> 16#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 17 18/ { 19 compatible = "xlnx,zynqmp"; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 27 cpu0: cpu@0 { 28 compatible = "arm,cortex-a53"; 29 device_type = "cpu"; 30 enable-method = "psci"; 31 operating-points-v2 = <&cpu_opp_table>; 32 reg = <0x0>; 33 cpu-idle-states = <&CPU_SLEEP_0>; 34 }; 35 36 cpu1: cpu@1 { 37 compatible = "arm,cortex-a53"; 38 device_type = "cpu"; 39 enable-method = "psci"; 40 reg = <0x1>; 41 operating-points-v2 = <&cpu_opp_table>; 42 cpu-idle-states = <&CPU_SLEEP_0>; 43 }; 44 45 cpu2: cpu@2 { 46 compatible = "arm,cortex-a53"; 47 device_type = "cpu"; 48 enable-method = "psci"; 49 reg = <0x2>; 50 operating-points-v2 = <&cpu_opp_table>; 51 cpu-idle-states = <&CPU_SLEEP_0>; 52 }; 53 54 cpu3: cpu@3 { 55 compatible = "arm,cortex-a53"; 56 device_type = "cpu"; 57 enable-method = "psci"; 58 reg = <0x3>; 59 operating-points-v2 = <&cpu_opp_table>; 60 cpu-idle-states = <&CPU_SLEEP_0>; 61 }; 62 63 idle-states { 64 entry-method = "psci"; 65 66 CPU_SLEEP_0: cpu-sleep-0 { 67 compatible = "arm,idle-state"; 68 arm,psci-suspend-param = <0x40000000>; 69 local-timer-stop; 70 entry-latency-us = <300>; 71 exit-latency-us = <600>; 72 min-residency-us = <10000>; 73 }; 74 }; 75 }; 76 77 cpu_opp_table: cpu-opp-table { 78 compatible = "operating-points-v2"; 79 opp-shared; 80 opp00 { 81 opp-hz = /bits/ 64 <1199999988>; 82 opp-microvolt = <1000000>; 83 clock-latency-ns = <500000>; 84 }; 85 opp01 { 86 opp-hz = /bits/ 64 <599999994>; 87 opp-microvolt = <1000000>; 88 clock-latency-ns = <500000>; 89 }; 90 opp02 { 91 opp-hz = /bits/ 64 <399999996>; 92 opp-microvolt = <1000000>; 93 clock-latency-ns = <500000>; 94 }; 95 opp03 { 96 opp-hz = /bits/ 64 <299999997>; 97 opp-microvolt = <1000000>; 98 clock-latency-ns = <500000>; 99 }; 100 }; 101 102 dcc: dcc { 103 compatible = "arm,dcc"; 104 status = "disabled"; 105 }; 106 107 pmu { 108 compatible = "arm,armv8-pmuv3"; 109 interrupt-parent = <&gic>; 110 interrupts = <0 143 4>, 111 <0 144 4>, 112 <0 145 4>, 113 <0 146 4>; 114 }; 115 116 psci { 117 compatible = "arm,psci-0.2"; 118 method = "smc"; 119 }; 120 121 firmware { 122 zynqmp_firmware: zynqmp-firmware { 123 compatible = "xlnx,zynqmp-firmware"; 124 #power-domain-cells = <1>; 125 method = "smc"; 126 127 zynqmp_power: zynqmp-power { 128 compatible = "xlnx,zynqmp-power"; 129 interrupt-parent = <&gic>; 130 interrupts = <0 35 4>; 131 }; 132 133 zynqmp_clk: clock-controller { 134 u-boot,dm-pre-reloc; 135 #clock-cells = <1>; 136 compatible = "xlnx,zynqmp-clk"; 137 clocks = <&pss_ref_clk>, 138 <&video_clk>, 139 <&pss_alt_ref_clk>, 140 <&aux_ref_clk>, 141 <>_crx_ref_clk>; 142 clock-names = "pss_ref_clk", 143 "video_clk", 144 "pss_alt_ref_clk", 145 "aux_ref_clk", 146 "gt_crx_ref_clk"; 147 }; 148 149 nvmem_firmware { 150 compatible = "xlnx,zynqmp-nvmem-fw"; 151 #address-cells = <1>; 152 #size-cells = <1>; 153 154 soc_revision: soc_revision@0 { 155 reg = <0x0 0x4>; 156 }; 157 }; 158 159 zynqmp_pcap: pcap { 160 compatible = "xlnx,zynqmp-pcap-fpga"; 161 }; 162 163 xlnx_aes: zynqmp-aes { 164 compatible = "xlnx,zynqmp-aes"; 165 }; 166 }; 167 }; 168 169 timer { 170 compatible = "arm,armv8-timer"; 171 interrupt-parent = <&gic>; 172 interrupts = <1 13 0xf08>, 173 <1 14 0xf08>, 174 <1 11 0xf08>, 175 <1 10 0xf08>; 176 }; 177 178 fpga_full: fpga-full { 179 compatible = "fpga-region"; 180 fpga-mgr = <&zynqmp_pcap>; 181 #address-cells = <2>; 182 #size-cells = <2>; 183 ranges; 184 }; 185 186 amba_apu: amba-apu@0 { 187 compatible = "simple-bus"; 188 #address-cells = <2>; 189 #size-cells = <1>; 190 ranges = <0 0 0 0 0xffffffff>; 191 192 gic: interrupt-controller@f9010000 { 193 compatible = "arm,gic-400"; 194 #interrupt-cells = <3>; 195 reg = <0x0 0xf9010000 0x10000>, 196 <0x0 0xf9020000 0x20000>, 197 <0x0 0xf9040000 0x20000>, 198 <0x0 0xf9060000 0x20000>; 199 interrupt-controller; 200 interrupt-parent = <&gic>; 201 interrupts = <1 9 0xf04>; 202 }; 203 }; 204 205 amba: amba { 206 compatible = "simple-bus"; 207 #address-cells = <2>; 208 #size-cells = <2>; 209 ranges; 210 211 can0: can@ff060000 { 212 compatible = "xlnx,zynq-can-1.0"; 213 status = "disabled"; 214 clock-names = "can_clk", "pclk"; 215 reg = <0x0 0xff060000 0x0 0x1000>; 216 interrupts = <0 23 4>; 217 interrupt-parent = <&gic>; 218 tx-fifo-depth = <0x40>; 219 rx-fifo-depth = <0x40>; 220 power-domains = <&zynqmp_firmware PD_CAN_0>; 221 }; 222 223 can1: can@ff070000 { 224 compatible = "xlnx,zynq-can-1.0"; 225 status = "disabled"; 226 clock-names = "can_clk", "pclk"; 227 reg = <0x0 0xff070000 0x0 0x1000>; 228 interrupts = <0 24 4>; 229 interrupt-parent = <&gic>; 230 tx-fifo-depth = <0x40>; 231 rx-fifo-depth = <0x40>; 232 power-domains = <&zynqmp_firmware PD_CAN_1>; 233 }; 234 235 cci: cci@fd6e0000 { 236 compatible = "arm,cci-400"; 237 reg = <0x0 0xfd6e0000 0x0 0x9000>; 238 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 239 #address-cells = <1>; 240 #size-cells = <1>; 241 242 pmu@9000 { 243 compatible = "arm,cci-400-pmu,r1"; 244 reg = <0x9000 0x5000>; 245 interrupt-parent = <&gic>; 246 interrupts = <0 123 4>, 247 <0 123 4>, 248 <0 123 4>, 249 <0 123 4>, 250 <0 123 4>; 251 }; 252 }; 253 254 /* GDMA */ 255 fpd_dma_chan1: dma@fd500000 { 256 status = "disabled"; 257 compatible = "xlnx,zynqmp-dma-1.0"; 258 reg = <0x0 0xfd500000 0x0 0x1000>; 259 interrupt-parent = <&gic>; 260 interrupts = <0 124 4>; 261 clock-names = "clk_main", "clk_apb"; 262 xlnx,bus-width = <128>; 263 power-domains = <&zynqmp_firmware PD_GDMA>; 264 }; 265 266 fpd_dma_chan2: dma@fd510000 { 267 status = "disabled"; 268 compatible = "xlnx,zynqmp-dma-1.0"; 269 reg = <0x0 0xfd510000 0x0 0x1000>; 270 interrupt-parent = <&gic>; 271 interrupts = <0 125 4>; 272 clock-names = "clk_main", "clk_apb"; 273 xlnx,bus-width = <128>; 274 power-domains = <&zynqmp_firmware PD_GDMA>; 275 }; 276 277 fpd_dma_chan3: dma@fd520000 { 278 status = "disabled"; 279 compatible = "xlnx,zynqmp-dma-1.0"; 280 reg = <0x0 0xfd520000 0x0 0x1000>; 281 interrupt-parent = <&gic>; 282 interrupts = <0 126 4>; 283 clock-names = "clk_main", "clk_apb"; 284 xlnx,bus-width = <128>; 285 power-domains = <&zynqmp_firmware PD_GDMA>; 286 }; 287 288 fpd_dma_chan4: dma@fd530000 { 289 status = "disabled"; 290 compatible = "xlnx,zynqmp-dma-1.0"; 291 reg = <0x0 0xfd530000 0x0 0x1000>; 292 interrupt-parent = <&gic>; 293 interrupts = <0 127 4>; 294 clock-names = "clk_main", "clk_apb"; 295 xlnx,bus-width = <128>; 296 power-domains = <&zynqmp_firmware PD_GDMA>; 297 }; 298 299 fpd_dma_chan5: dma@fd540000 { 300 status = "disabled"; 301 compatible = "xlnx,zynqmp-dma-1.0"; 302 reg = <0x0 0xfd540000 0x0 0x1000>; 303 interrupt-parent = <&gic>; 304 interrupts = <0 128 4>; 305 clock-names = "clk_main", "clk_apb"; 306 xlnx,bus-width = <128>; 307 power-domains = <&zynqmp_firmware PD_GDMA>; 308 }; 309 310 fpd_dma_chan6: dma@fd550000 { 311 status = "disabled"; 312 compatible = "xlnx,zynqmp-dma-1.0"; 313 reg = <0x0 0xfd550000 0x0 0x1000>; 314 interrupt-parent = <&gic>; 315 interrupts = <0 129 4>; 316 clock-names = "clk_main", "clk_apb"; 317 xlnx,bus-width = <128>; 318 power-domains = <&zynqmp_firmware PD_GDMA>; 319 }; 320 321 fpd_dma_chan7: dma@fd560000 { 322 status = "disabled"; 323 compatible = "xlnx,zynqmp-dma-1.0"; 324 reg = <0x0 0xfd560000 0x0 0x1000>; 325 interrupt-parent = <&gic>; 326 interrupts = <0 130 4>; 327 clock-names = "clk_main", "clk_apb"; 328 xlnx,bus-width = <128>; 329 power-domains = <&zynqmp_firmware PD_GDMA>; 330 }; 331 332 fpd_dma_chan8: dma@fd570000 { 333 status = "disabled"; 334 compatible = "xlnx,zynqmp-dma-1.0"; 335 reg = <0x0 0xfd570000 0x0 0x1000>; 336 interrupt-parent = <&gic>; 337 interrupts = <0 131 4>; 338 clock-names = "clk_main", "clk_apb"; 339 xlnx,bus-width = <128>; 340 power-domains = <&zynqmp_firmware PD_GDMA>; 341 }; 342 343 /* LPDDMA default allows only secured access. inorder to enable 344 * These dma channels, Users should ensure that these dma 345 * Channels are allowed for non secure access. 346 */ 347 lpd_dma_chan1: dma@ffa80000 { 348 status = "disabled"; 349 compatible = "xlnx,zynqmp-dma-1.0"; 350 reg = <0x0 0xffa80000 0x0 0x1000>; 351 interrupt-parent = <&gic>; 352 interrupts = <0 77 4>; 353 clock-names = "clk_main", "clk_apb"; 354 xlnx,bus-width = <64>; 355 power-domains = <&zynqmp_firmware PD_ADMA>; 356 }; 357 358 lpd_dma_chan2: dma@ffa90000 { 359 status = "disabled"; 360 compatible = "xlnx,zynqmp-dma-1.0"; 361 reg = <0x0 0xffa90000 0x0 0x1000>; 362 interrupt-parent = <&gic>; 363 interrupts = <0 78 4>; 364 clock-names = "clk_main", "clk_apb"; 365 xlnx,bus-width = <64>; 366 power-domains = <&zynqmp_firmware PD_ADMA>; 367 }; 368 369 lpd_dma_chan3: dma@ffaa0000 { 370 status = "disabled"; 371 compatible = "xlnx,zynqmp-dma-1.0"; 372 reg = <0x0 0xffaa0000 0x0 0x1000>; 373 interrupt-parent = <&gic>; 374 interrupts = <0 79 4>; 375 clock-names = "clk_main", "clk_apb"; 376 xlnx,bus-width = <64>; 377 power-domains = <&zynqmp_firmware PD_ADMA>; 378 }; 379 380 lpd_dma_chan4: dma@ffab0000 { 381 status = "disabled"; 382 compatible = "xlnx,zynqmp-dma-1.0"; 383 reg = <0x0 0xffab0000 0x0 0x1000>; 384 interrupt-parent = <&gic>; 385 interrupts = <0 80 4>; 386 clock-names = "clk_main", "clk_apb"; 387 xlnx,bus-width = <64>; 388 power-domains = <&zynqmp_firmware PD_ADMA>; 389 }; 390 391 lpd_dma_chan5: dma@ffac0000 { 392 status = "disabled"; 393 compatible = "xlnx,zynqmp-dma-1.0"; 394 reg = <0x0 0xffac0000 0x0 0x1000>; 395 interrupt-parent = <&gic>; 396 interrupts = <0 81 4>; 397 clock-names = "clk_main", "clk_apb"; 398 xlnx,bus-width = <64>; 399 power-domains = <&zynqmp_firmware PD_ADMA>; 400 }; 401 402 lpd_dma_chan6: dma@ffad0000 { 403 status = "disabled"; 404 compatible = "xlnx,zynqmp-dma-1.0"; 405 reg = <0x0 0xffad0000 0x0 0x1000>; 406 interrupt-parent = <&gic>; 407 interrupts = <0 82 4>; 408 clock-names = "clk_main", "clk_apb"; 409 xlnx,bus-width = <64>; 410 power-domains = <&zynqmp_firmware PD_ADMA>; 411 }; 412 413 lpd_dma_chan7: dma@ffae0000 { 414 status = "disabled"; 415 compatible = "xlnx,zynqmp-dma-1.0"; 416 reg = <0x0 0xffae0000 0x0 0x1000>; 417 interrupt-parent = <&gic>; 418 interrupts = <0 83 4>; 419 clock-names = "clk_main", "clk_apb"; 420 xlnx,bus-width = <64>; 421 power-domains = <&zynqmp_firmware PD_ADMA>; 422 }; 423 424 lpd_dma_chan8: dma@ffaf0000 { 425 status = "disabled"; 426 compatible = "xlnx,zynqmp-dma-1.0"; 427 reg = <0x0 0xffaf0000 0x0 0x1000>; 428 interrupt-parent = <&gic>; 429 interrupts = <0 84 4>; 430 clock-names = "clk_main", "clk_apb"; 431 xlnx,bus-width = <64>; 432 power-domains = <&zynqmp_firmware PD_ADMA>; 433 }; 434 435 mc: memory-controller@fd070000 { 436 compatible = "xlnx,zynqmp-ddrc-2.40a"; 437 reg = <0x0 0xfd070000 0x0 0x30000>; 438 interrupt-parent = <&gic>; 439 interrupts = <0 112 4>; 440 }; 441 442 gem0: ethernet@ff0b0000 { 443 compatible = "cdns,zynqmp-gem", "cdns,gem"; 444 status = "disabled"; 445 interrupt-parent = <&gic>; 446 interrupts = <0 57 4>, <0 57 4>; 447 reg = <0x0 0xff0b0000 0x0 0x1000>; 448 clock-names = "pclk", "hclk", "tx_clk"; 449 #address-cells = <1>; 450 #size-cells = <0>; 451 power-domains = <&zynqmp_firmware PD_ETH_0>; 452 }; 453 454 gem1: ethernet@ff0c0000 { 455 compatible = "cdns,zynqmp-gem", "cdns,gem"; 456 status = "disabled"; 457 interrupt-parent = <&gic>; 458 interrupts = <0 59 4>, <0 59 4>; 459 reg = <0x0 0xff0c0000 0x0 0x1000>; 460 clock-names = "pclk", "hclk", "tx_clk"; 461 #address-cells = <1>; 462 #size-cells = <0>; 463 power-domains = <&zynqmp_firmware PD_ETH_1>; 464 }; 465 466 gem2: ethernet@ff0d0000 { 467 compatible = "cdns,zynqmp-gem", "cdns,gem"; 468 status = "disabled"; 469 interrupt-parent = <&gic>; 470 interrupts = <0 61 4>, <0 61 4>; 471 reg = <0x0 0xff0d0000 0x0 0x1000>; 472 clock-names = "pclk", "hclk", "tx_clk"; 473 #address-cells = <1>; 474 #size-cells = <0>; 475 power-domains = <&zynqmp_firmware PD_ETH_2>; 476 }; 477 478 gem3: ethernet@ff0e0000 { 479 compatible = "cdns,zynqmp-gem", "cdns,gem"; 480 status = "disabled"; 481 interrupt-parent = <&gic>; 482 interrupts = <0 63 4>, <0 63 4>; 483 reg = <0x0 0xff0e0000 0x0 0x1000>; 484 clock-names = "pclk", "hclk", "tx_clk"; 485 #address-cells = <1>; 486 #size-cells = <0>; 487 power-domains = <&zynqmp_firmware PD_ETH_3>; 488 }; 489 490 gpio: gpio@ff0a0000 { 491 compatible = "xlnx,zynqmp-gpio-1.0"; 492 status = "disabled"; 493 #gpio-cells = <0x2>; 494 gpio-controller; 495 interrupt-parent = <&gic>; 496 interrupts = <0 16 4>; 497 interrupt-controller; 498 #interrupt-cells = <2>; 499 reg = <0x0 0xff0a0000 0x0 0x1000>; 500 power-domains = <&zynqmp_firmware PD_GPIO>; 501 }; 502 503 i2c0: i2c@ff020000 { 504 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 505 status = "disabled"; 506 interrupt-parent = <&gic>; 507 interrupts = <0 17 4>; 508 reg = <0x0 0xff020000 0x0 0x1000>; 509 #address-cells = <1>; 510 #size-cells = <0>; 511 power-domains = <&zynqmp_firmware PD_I2C_0>; 512 }; 513 514 i2c1: i2c@ff030000 { 515 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 516 status = "disabled"; 517 interrupt-parent = <&gic>; 518 interrupts = <0 18 4>; 519 reg = <0x0 0xff030000 0x0 0x1000>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 power-domains = <&zynqmp_firmware PD_I2C_1>; 523 }; 524 525 pcie: pcie@fd0e0000 { 526 compatible = "xlnx,nwl-pcie-2.11"; 527 status = "disabled"; 528 #address-cells = <3>; 529 #size-cells = <2>; 530 #interrupt-cells = <1>; 531 msi-controller; 532 device_type = "pci"; 533 interrupt-parent = <&gic>; 534 interrupts = <0 118 4>, 535 <0 117 4>, 536 <0 116 4>, 537 <0 115 4>, /* MSI_1 [63...32] */ 538 <0 114 4>; /* MSI_0 [31...0] */ 539 interrupt-names = "misc", "dummy", "intx", 540 "msi1", "msi0"; 541 msi-parent = <&pcie>; 542 reg = <0x0 0xfd0e0000 0x0 0x1000>, 543 <0x0 0xfd480000 0x0 0x1000>, 544 <0x80 0x00000000 0x0 0x1000000>; 545 reg-names = "breg", "pcireg", "cfg"; 546 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 547 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 548 bus-range = <0x00 0xff>; 549 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 550 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 551 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 552 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 553 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 554 power-domains = <&zynqmp_firmware PD_PCIE>; 555 pcie_intc: legacy-interrupt-controller { 556 interrupt-controller; 557 #address-cells = <0>; 558 #interrupt-cells = <1>; 559 }; 560 }; 561 562 psgtr: phy@fd400000 { 563 compatible = "xlnx,zynqmp-psgtr-v1.1"; 564 status = "disabled"; 565 reg = <0x0 0xfd400000 0x0 0x40000>, 566 <0x0 0xfd3d0000 0x0 0x1000>; 567 reg-names = "serdes", "siou"; 568 #phy-cells = <4>; 569 }; 570 571 rtc: rtc@ffa60000 { 572 compatible = "xlnx,zynqmp-rtc"; 573 status = "disabled"; 574 reg = <0x0 0xffa60000 0x0 0x100>; 575 interrupt-parent = <&gic>; 576 interrupts = <0 26 4>, <0 27 4>; 577 interrupt-names = "alarm", "sec"; 578 calibration = <0x8000>; 579 }; 580 581 sata: ahci@fd0c0000 { 582 compatible = "ceva,ahci-1v84"; 583 status = "disabled"; 584 reg = <0x0 0xfd0c0000 0x0 0x2000>; 585 interrupt-parent = <&gic>; 586 interrupts = <0 133 4>; 587 power-domains = <&zynqmp_firmware PD_SATA>; 588 }; 589 590 sdhci0: mmc@ff160000 { 591 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 592 status = "disabled"; 593 interrupt-parent = <&gic>; 594 interrupts = <0 48 4>; 595 reg = <0x0 0xff160000 0x0 0x1000>; 596 clock-names = "clk_xin", "clk_ahb"; 597 #clock-cells = <1>; 598 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 599 power-domains = <&zynqmp_firmware PD_SD_0>; 600 }; 601 602 sdhci1: mmc@ff170000 { 603 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 604 status = "disabled"; 605 interrupt-parent = <&gic>; 606 interrupts = <0 49 4>; 607 reg = <0x0 0xff170000 0x0 0x1000>; 608 clock-names = "clk_xin", "clk_ahb"; 609 #clock-cells = <1>; 610 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 611 power-domains = <&zynqmp_firmware PD_SD_1>; 612 }; 613 614 smmu: iommu@fd800000 { 615 compatible = "arm,mmu-500"; 616 reg = <0x0 0xfd800000 0x0 0x20000>; 617 status = "disabled"; 618 #global-interrupts = <1>; 619 interrupt-parent = <&gic>; 620 interrupts = <0 155 4>, 621 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 622 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 623 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 624 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 625 }; 626 627 spi0: spi@ff040000 { 628 compatible = "cdns,spi-r1p6"; 629 status = "disabled"; 630 interrupt-parent = <&gic>; 631 interrupts = <0 19 4>; 632 reg = <0x0 0xff040000 0x0 0x1000>; 633 clock-names = "ref_clk", "pclk"; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 power-domains = <&zynqmp_firmware PD_SPI_0>; 637 }; 638 639 spi1: spi@ff050000 { 640 compatible = "cdns,spi-r1p6"; 641 status = "disabled"; 642 interrupt-parent = <&gic>; 643 interrupts = <0 20 4>; 644 reg = <0x0 0xff050000 0x0 0x1000>; 645 clock-names = "ref_clk", "pclk"; 646 #address-cells = <1>; 647 #size-cells = <0>; 648 power-domains = <&zynqmp_firmware PD_SPI_1>; 649 }; 650 651 ttc0: timer@ff110000 { 652 compatible = "cdns,ttc"; 653 status = "disabled"; 654 interrupt-parent = <&gic>; 655 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 656 reg = <0x0 0xff110000 0x0 0x1000>; 657 timer-width = <32>; 658 power-domains = <&zynqmp_firmware PD_TTC_0>; 659 }; 660 661 ttc1: timer@ff120000 { 662 compatible = "cdns,ttc"; 663 status = "disabled"; 664 interrupt-parent = <&gic>; 665 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 666 reg = <0x0 0xff120000 0x0 0x1000>; 667 timer-width = <32>; 668 power-domains = <&zynqmp_firmware PD_TTC_1>; 669 }; 670 671 ttc2: timer@ff130000 { 672 compatible = "cdns,ttc"; 673 status = "disabled"; 674 interrupt-parent = <&gic>; 675 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 676 reg = <0x0 0xff130000 0x0 0x1000>; 677 timer-width = <32>; 678 power-domains = <&zynqmp_firmware PD_TTC_2>; 679 }; 680 681 ttc3: timer@ff140000 { 682 compatible = "cdns,ttc"; 683 status = "disabled"; 684 interrupt-parent = <&gic>; 685 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 686 reg = <0x0 0xff140000 0x0 0x1000>; 687 timer-width = <32>; 688 power-domains = <&zynqmp_firmware PD_TTC_3>; 689 }; 690 691 uart0: serial@ff000000 { 692 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 693 status = "disabled"; 694 interrupt-parent = <&gic>; 695 interrupts = <0 21 4>; 696 reg = <0x0 0xff000000 0x0 0x1000>; 697 clock-names = "uart_clk", "pclk"; 698 power-domains = <&zynqmp_firmware PD_UART_0>; 699 }; 700 701 uart1: serial@ff010000 { 702 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 703 status = "disabled"; 704 interrupt-parent = <&gic>; 705 interrupts = <0 22 4>; 706 reg = <0x0 0xff010000 0x0 0x1000>; 707 clock-names = "uart_clk", "pclk"; 708 power-domains = <&zynqmp_firmware PD_UART_1>; 709 }; 710 711 usb0: usb@fe200000 { 712 compatible = "snps,dwc3"; 713 status = "disabled"; 714 interrupt-parent = <&gic>; 715 interrupts = <0 65 4>; 716 reg = <0x0 0xfe200000 0x0 0x40000>; 717 clock-names = "clk_xin", "clk_ahb"; 718 power-domains = <&zynqmp_firmware PD_USB_0>; 719 }; 720 721 usb1: usb@fe300000 { 722 compatible = "snps,dwc3"; 723 status = "disabled"; 724 interrupt-parent = <&gic>; 725 interrupts = <0 70 4>; 726 reg = <0x0 0xfe300000 0x0 0x40000>; 727 clock-names = "clk_xin", "clk_ahb"; 728 power-domains = <&zynqmp_firmware PD_USB_1>; 729 }; 730 731 watchdog0: watchdog@fd4d0000 { 732 compatible = "cdns,wdt-r1p2"; 733 status = "disabled"; 734 interrupt-parent = <&gic>; 735 interrupts = <0 113 1>; 736 reg = <0x0 0xfd4d0000 0x0 0x1000>; 737 timeout-sec = <10>; 738 }; 739 }; 740}; 741