1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/power/xlnx-zynqmp-power.h> 18#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 19 20/ { 21 compatible = "xlnx,zynqmp"; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-a53"; 31 device_type = "cpu"; 32 enable-method = "psci"; 33 operating-points-v2 = <&cpu_opp_table>; 34 reg = <0x0>; 35 cpu-idle-states = <&CPU_SLEEP_0>; 36 }; 37 38 cpu1: cpu@1 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 enable-method = "psci"; 42 reg = <0x1>; 43 operating-points-v2 = <&cpu_opp_table>; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 }; 46 47 cpu2: cpu@2 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 operating-points-v2 = <&cpu_opp_table>; 53 cpu-idle-states = <&CPU_SLEEP_0>; 54 }; 55 56 cpu3: cpu@3 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 enable-method = "psci"; 60 reg = <0x3>; 61 operating-points-v2 = <&cpu_opp_table>; 62 cpu-idle-states = <&CPU_SLEEP_0>; 63 }; 64 65 idle-states { 66 entry-method = "psci"; 67 68 CPU_SLEEP_0: cpu-sleep-0 { 69 compatible = "arm,idle-state"; 70 arm,psci-suspend-param = <0x40000000>; 71 local-timer-stop; 72 entry-latency-us = <300>; 73 exit-latency-us = <600>; 74 min-residency-us = <10000>; 75 }; 76 }; 77 }; 78 79 cpu_opp_table: opp-table-cpu { 80 compatible = "operating-points-v2"; 81 opp-shared; 82 opp00 { 83 opp-hz = /bits/ 64 <1199999988>; 84 opp-microvolt = <1000000>; 85 clock-latency-ns = <500000>; 86 }; 87 opp01 { 88 opp-hz = /bits/ 64 <599999994>; 89 opp-microvolt = <1000000>; 90 clock-latency-ns = <500000>; 91 }; 92 opp02 { 93 opp-hz = /bits/ 64 <399999996>; 94 opp-microvolt = <1000000>; 95 clock-latency-ns = <500000>; 96 }; 97 opp03 { 98 opp-hz = /bits/ 64 <299999997>; 99 opp-microvolt = <1000000>; 100 clock-latency-ns = <500000>; 101 }; 102 }; 103 104 reserved-memory { 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 rproc_0_fw_image: memory@3ed00000 { 110 no-map; 111 reg = <0x0 0x3ed00000 0x0 0x40000>; 112 }; 113 114 rproc_1_fw_image: memory@3ef00000 { 115 no-map; 116 reg = <0x0 0x3ef00000 0x0 0x40000>; 117 }; 118 }; 119 120 zynqmp_ipi: zynqmp_ipi { 121 compatible = "xlnx,zynqmp-ipi-mailbox"; 122 interrupt-parent = <&gic>; 123 interrupts = <0 35 4>; 124 xlnx,ipi-id = <0>; 125 #address-cells = <2>; 126 #size-cells = <2>; 127 ranges; 128 129 ipi_mailbox_pmu1: mailbox@ff990400 { 130 reg = <0x0 0xff9905c0 0x0 0x20>, 131 <0x0 0xff9905e0 0x0 0x20>, 132 <0x0 0xff990e80 0x0 0x20>, 133 <0x0 0xff990ea0 0x0 0x20>; 134 reg-names = "local_request_region", 135 "local_response_region", 136 "remote_request_region", 137 "remote_response_region"; 138 #mbox-cells = <1>; 139 xlnx,ipi-id = <4>; 140 }; 141 }; 142 143 dcc: dcc { 144 compatible = "arm,dcc"; 145 status = "disabled"; 146 }; 147 148 pmu { 149 compatible = "arm,armv8-pmuv3"; 150 interrupt-parent = <&gic>; 151 interrupts = <0 143 4>, 152 <0 144 4>, 153 <0 145 4>, 154 <0 146 4>; 155 }; 156 157 psci { 158 compatible = "arm,psci-0.2"; 159 method = "smc"; 160 }; 161 162 firmware { 163 zynqmp_firmware: zynqmp-firmware { 164 compatible = "xlnx,zynqmp-firmware"; 165 #power-domain-cells = <1>; 166 method = "smc"; 167 168 zynqmp_power: zynqmp-power { 169 compatible = "xlnx,zynqmp-power"; 170 interrupt-parent = <&gic>; 171 interrupts = <0 35 4>; 172 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 173 mbox-names = "tx", "rx"; 174 }; 175 176 nvmem_firmware { 177 compatible = "xlnx,zynqmp-nvmem-fw"; 178 #address-cells = <1>; 179 #size-cells = <1>; 180 181 soc_revision: soc_revision@0 { 182 reg = <0x0 0x4>; 183 }; 184 }; 185 186 zynqmp_pcap: pcap { 187 compatible = "xlnx,zynqmp-pcap-fpga"; 188 }; 189 190 xlnx_aes: zynqmp-aes { 191 compatible = "xlnx,zynqmp-aes"; 192 }; 193 194 zynqmp_reset: reset-controller { 195 compatible = "xlnx,zynqmp-reset"; 196 #reset-cells = <1>; 197 }; 198 199 pinctrl0: pinctrl { 200 compatible = "xlnx,zynqmp-pinctrl"; 201 status = "disabled"; 202 }; 203 204 modepin_gpio: gpio { 205 compatible = "xlnx,zynqmp-gpio-modepin"; 206 gpio-controller; 207 #gpio-cells = <2>; 208 }; 209 }; 210 }; 211 212 timer { 213 compatible = "arm,armv8-timer"; 214 interrupt-parent = <&gic>; 215 interrupts = <1 13 0xf08>, 216 <1 14 0xf08>, 217 <1 11 0xf08>, 218 <1 10 0xf08>; 219 }; 220 221 fpga_full: fpga-full { 222 compatible = "fpga-region"; 223 fpga-mgr = <&zynqmp_pcap>; 224 #address-cells = <2>; 225 #size-cells = <2>; 226 ranges; 227 }; 228 229 remoteproc { 230 compatible = "xlnx,zynqmp-r5fss"; 231 xlnx,cluster-mode = <1>; 232 233 r5f-0 { 234 compatible = "xlnx,zynqmp-r5f"; 235 power-domains = <&zynqmp_firmware PD_RPU_0>; 236 memory-region = <&rproc_0_fw_image>; 237 }; 238 239 r5f-1 { 240 compatible = "xlnx,zynqmp-r5f"; 241 power-domains = <&zynqmp_firmware PD_RPU_1>; 242 memory-region = <&rproc_1_fw_image>; 243 }; 244 }; 245 246 amba: axi { 247 compatible = "simple-bus"; 248 #address-cells = <2>; 249 #size-cells = <2>; 250 ranges; 251 252 can0: can@ff060000 { 253 compatible = "xlnx,zynq-can-1.0"; 254 status = "disabled"; 255 clock-names = "can_clk", "pclk"; 256 reg = <0x0 0xff060000 0x0 0x1000>; 257 interrupts = <0 23 4>; 258 interrupt-parent = <&gic>; 259 tx-fifo-depth = <0x40>; 260 rx-fifo-depth = <0x40>; 261 power-domains = <&zynqmp_firmware PD_CAN_0>; 262 }; 263 264 can1: can@ff070000 { 265 compatible = "xlnx,zynq-can-1.0"; 266 status = "disabled"; 267 clock-names = "can_clk", "pclk"; 268 reg = <0x0 0xff070000 0x0 0x1000>; 269 interrupts = <0 24 4>; 270 interrupt-parent = <&gic>; 271 tx-fifo-depth = <0x40>; 272 rx-fifo-depth = <0x40>; 273 power-domains = <&zynqmp_firmware PD_CAN_1>; 274 }; 275 276 cci: cci@fd6e0000 { 277 compatible = "arm,cci-400"; 278 status = "disabled"; 279 reg = <0x0 0xfd6e0000 0x0 0x9000>; 280 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 281 #address-cells = <1>; 282 #size-cells = <1>; 283 284 pmu@9000 { 285 compatible = "arm,cci-400-pmu,r1"; 286 reg = <0x9000 0x5000>; 287 interrupt-parent = <&gic>; 288 interrupts = <0 123 4>, 289 <0 123 4>, 290 <0 123 4>, 291 <0 123 4>, 292 <0 123 4>; 293 }; 294 }; 295 296 /* GDMA */ 297 fpd_dma_chan1: dma-controller@fd500000 { 298 status = "disabled"; 299 compatible = "xlnx,zynqmp-dma-1.0"; 300 reg = <0x0 0xfd500000 0x0 0x1000>; 301 interrupt-parent = <&gic>; 302 interrupts = <0 124 4>; 303 clock-names = "clk_main", "clk_apb"; 304 #dma-cells = <1>; 305 xlnx,bus-width = <128>; 306 iommus = <&smmu 0x14e8>; 307 power-domains = <&zynqmp_firmware PD_GDMA>; 308 }; 309 310 fpd_dma_chan2: dma-controller@fd510000 { 311 status = "disabled"; 312 compatible = "xlnx,zynqmp-dma-1.0"; 313 reg = <0x0 0xfd510000 0x0 0x1000>; 314 interrupt-parent = <&gic>; 315 interrupts = <0 125 4>; 316 clock-names = "clk_main", "clk_apb"; 317 #dma-cells = <1>; 318 xlnx,bus-width = <128>; 319 iommus = <&smmu 0x14e9>; 320 power-domains = <&zynqmp_firmware PD_GDMA>; 321 }; 322 323 fpd_dma_chan3: dma-controller@fd520000 { 324 status = "disabled"; 325 compatible = "xlnx,zynqmp-dma-1.0"; 326 reg = <0x0 0xfd520000 0x0 0x1000>; 327 interrupt-parent = <&gic>; 328 interrupts = <0 126 4>; 329 clock-names = "clk_main", "clk_apb"; 330 #dma-cells = <1>; 331 xlnx,bus-width = <128>; 332 iommus = <&smmu 0x14ea>; 333 power-domains = <&zynqmp_firmware PD_GDMA>; 334 }; 335 336 fpd_dma_chan4: dma-controller@fd530000 { 337 status = "disabled"; 338 compatible = "xlnx,zynqmp-dma-1.0"; 339 reg = <0x0 0xfd530000 0x0 0x1000>; 340 interrupt-parent = <&gic>; 341 interrupts = <0 127 4>; 342 clock-names = "clk_main", "clk_apb"; 343 #dma-cells = <1>; 344 xlnx,bus-width = <128>; 345 iommus = <&smmu 0x14eb>; 346 power-domains = <&zynqmp_firmware PD_GDMA>; 347 }; 348 349 fpd_dma_chan5: dma-controller@fd540000 { 350 status = "disabled"; 351 compatible = "xlnx,zynqmp-dma-1.0"; 352 reg = <0x0 0xfd540000 0x0 0x1000>; 353 interrupt-parent = <&gic>; 354 interrupts = <0 128 4>; 355 clock-names = "clk_main", "clk_apb"; 356 #dma-cells = <1>; 357 xlnx,bus-width = <128>; 358 iommus = <&smmu 0x14ec>; 359 power-domains = <&zynqmp_firmware PD_GDMA>; 360 }; 361 362 fpd_dma_chan6: dma-controller@fd550000 { 363 status = "disabled"; 364 compatible = "xlnx,zynqmp-dma-1.0"; 365 reg = <0x0 0xfd550000 0x0 0x1000>; 366 interrupt-parent = <&gic>; 367 interrupts = <0 129 4>; 368 clock-names = "clk_main", "clk_apb"; 369 #dma-cells = <1>; 370 xlnx,bus-width = <128>; 371 iommus = <&smmu 0x14ed>; 372 power-domains = <&zynqmp_firmware PD_GDMA>; 373 }; 374 375 fpd_dma_chan7: dma-controller@fd560000 { 376 status = "disabled"; 377 compatible = "xlnx,zynqmp-dma-1.0"; 378 reg = <0x0 0xfd560000 0x0 0x1000>; 379 interrupt-parent = <&gic>; 380 interrupts = <0 130 4>; 381 clock-names = "clk_main", "clk_apb"; 382 #dma-cells = <1>; 383 xlnx,bus-width = <128>; 384 iommus = <&smmu 0x14ee>; 385 power-domains = <&zynqmp_firmware PD_GDMA>; 386 }; 387 388 fpd_dma_chan8: dma-controller@fd570000 { 389 status = "disabled"; 390 compatible = "xlnx,zynqmp-dma-1.0"; 391 reg = <0x0 0xfd570000 0x0 0x1000>; 392 interrupt-parent = <&gic>; 393 interrupts = <0 131 4>; 394 clock-names = "clk_main", "clk_apb"; 395 #dma-cells = <1>; 396 xlnx,bus-width = <128>; 397 iommus = <&smmu 0x14ef>; 398 power-domains = <&zynqmp_firmware PD_GDMA>; 399 }; 400 401 gic: interrupt-controller@f9010000 { 402 compatible = "arm,gic-400"; 403 #address-cells = <0>; 404 #interrupt-cells = <3>; 405 reg = <0x0 0xf9010000 0x0 0x10000>, 406 <0x0 0xf9020000 0x0 0x20000>, 407 <0x0 0xf9040000 0x0 0x20000>, 408 <0x0 0xf9060000 0x0 0x20000>; 409 interrupt-controller; 410 interrupt-parent = <&gic>; 411 interrupts = <1 9 0xf04>; 412 }; 413 414 /* LPDDMA default allows only secured access. inorder to enable 415 * These dma channels, Users should ensure that these dma 416 * Channels are allowed for non secure access. 417 */ 418 lpd_dma_chan1: dma-controller@ffa80000 { 419 status = "disabled"; 420 compatible = "xlnx,zynqmp-dma-1.0"; 421 reg = <0x0 0xffa80000 0x0 0x1000>; 422 interrupt-parent = <&gic>; 423 interrupts = <0 77 4>; 424 clock-names = "clk_main", "clk_apb"; 425 #dma-cells = <1>; 426 xlnx,bus-width = <64>; 427 iommus = <&smmu 0x868>; 428 power-domains = <&zynqmp_firmware PD_ADMA>; 429 }; 430 431 lpd_dma_chan2: dma-controller@ffa90000 { 432 status = "disabled"; 433 compatible = "xlnx,zynqmp-dma-1.0"; 434 reg = <0x0 0xffa90000 0x0 0x1000>; 435 interrupt-parent = <&gic>; 436 interrupts = <0 78 4>; 437 clock-names = "clk_main", "clk_apb"; 438 #dma-cells = <1>; 439 xlnx,bus-width = <64>; 440 iommus = <&smmu 0x869>; 441 power-domains = <&zynqmp_firmware PD_ADMA>; 442 }; 443 444 lpd_dma_chan3: dma-controller@ffaa0000 { 445 status = "disabled"; 446 compatible = "xlnx,zynqmp-dma-1.0"; 447 reg = <0x0 0xffaa0000 0x0 0x1000>; 448 interrupt-parent = <&gic>; 449 interrupts = <0 79 4>; 450 clock-names = "clk_main", "clk_apb"; 451 #dma-cells = <1>; 452 xlnx,bus-width = <64>; 453 iommus = <&smmu 0x86a>; 454 power-domains = <&zynqmp_firmware PD_ADMA>; 455 }; 456 457 lpd_dma_chan4: dma-controller@ffab0000 { 458 status = "disabled"; 459 compatible = "xlnx,zynqmp-dma-1.0"; 460 reg = <0x0 0xffab0000 0x0 0x1000>; 461 interrupt-parent = <&gic>; 462 interrupts = <0 80 4>; 463 clock-names = "clk_main", "clk_apb"; 464 #dma-cells = <1>; 465 xlnx,bus-width = <64>; 466 iommus = <&smmu 0x86b>; 467 power-domains = <&zynqmp_firmware PD_ADMA>; 468 }; 469 470 lpd_dma_chan5: dma-controller@ffac0000 { 471 status = "disabled"; 472 compatible = "xlnx,zynqmp-dma-1.0"; 473 reg = <0x0 0xffac0000 0x0 0x1000>; 474 interrupt-parent = <&gic>; 475 interrupts = <0 81 4>; 476 clock-names = "clk_main", "clk_apb"; 477 #dma-cells = <1>; 478 xlnx,bus-width = <64>; 479 iommus = <&smmu 0x86c>; 480 power-domains = <&zynqmp_firmware PD_ADMA>; 481 }; 482 483 lpd_dma_chan6: dma-controller@ffad0000 { 484 status = "disabled"; 485 compatible = "xlnx,zynqmp-dma-1.0"; 486 reg = <0x0 0xffad0000 0x0 0x1000>; 487 interrupt-parent = <&gic>; 488 interrupts = <0 82 4>; 489 clock-names = "clk_main", "clk_apb"; 490 #dma-cells = <1>; 491 xlnx,bus-width = <64>; 492 iommus = <&smmu 0x86d>; 493 power-domains = <&zynqmp_firmware PD_ADMA>; 494 }; 495 496 lpd_dma_chan7: dma-controller@ffae0000 { 497 status = "disabled"; 498 compatible = "xlnx,zynqmp-dma-1.0"; 499 reg = <0x0 0xffae0000 0x0 0x1000>; 500 interrupt-parent = <&gic>; 501 interrupts = <0 83 4>; 502 clock-names = "clk_main", "clk_apb"; 503 #dma-cells = <1>; 504 xlnx,bus-width = <64>; 505 iommus = <&smmu 0x86e>; 506 power-domains = <&zynqmp_firmware PD_ADMA>; 507 }; 508 509 lpd_dma_chan8: dma-controller@ffaf0000 { 510 status = "disabled"; 511 compatible = "xlnx,zynqmp-dma-1.0"; 512 reg = <0x0 0xffaf0000 0x0 0x1000>; 513 interrupt-parent = <&gic>; 514 interrupts = <0 84 4>; 515 clock-names = "clk_main", "clk_apb"; 516 #dma-cells = <1>; 517 xlnx,bus-width = <64>; 518 iommus = <&smmu 0x86f>; 519 power-domains = <&zynqmp_firmware PD_ADMA>; 520 }; 521 522 mc: memory-controller@fd070000 { 523 compatible = "xlnx,zynqmp-ddrc-2.40a"; 524 reg = <0x0 0xfd070000 0x0 0x30000>; 525 interrupt-parent = <&gic>; 526 interrupts = <0 112 4>; 527 }; 528 529 nand0: nand-controller@ff100000 { 530 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 531 status = "disabled"; 532 reg = <0x0 0xff100000 0x0 0x1000>; 533 clock-names = "controller", "bus"; 534 interrupt-parent = <&gic>; 535 interrupts = <0 14 4>; 536 #address-cells = <1>; 537 #size-cells = <0>; 538 iommus = <&smmu 0x872>; 539 power-domains = <&zynqmp_firmware PD_NAND>; 540 }; 541 542 gem0: ethernet@ff0b0000 { 543 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 544 status = "disabled"; 545 interrupt-parent = <&gic>; 546 interrupts = <0 57 4>, <0 57 4>; 547 reg = <0x0 0xff0b0000 0x0 0x1000>; 548 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 549 #address-cells = <1>; 550 #size-cells = <0>; 551 iommus = <&smmu 0x874>; 552 power-domains = <&zynqmp_firmware PD_ETH_0>; 553 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; 554 reset-names = "gem0_rst"; 555 }; 556 557 gem1: ethernet@ff0c0000 { 558 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 559 status = "disabled"; 560 interrupt-parent = <&gic>; 561 interrupts = <0 59 4>, <0 59 4>; 562 reg = <0x0 0xff0c0000 0x0 0x1000>; 563 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 iommus = <&smmu 0x875>; 567 power-domains = <&zynqmp_firmware PD_ETH_1>; 568 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 569 reset-names = "gem1_rst"; 570 }; 571 572 gem2: ethernet@ff0d0000 { 573 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 574 status = "disabled"; 575 interrupt-parent = <&gic>; 576 interrupts = <0 61 4>, <0 61 4>; 577 reg = <0x0 0xff0d0000 0x0 0x1000>; 578 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 579 #address-cells = <1>; 580 #size-cells = <0>; 581 iommus = <&smmu 0x876>; 582 power-domains = <&zynqmp_firmware PD_ETH_2>; 583 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; 584 reset-names = "gem2_rst"; 585 }; 586 587 gem3: ethernet@ff0e0000 { 588 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 589 status = "disabled"; 590 interrupt-parent = <&gic>; 591 interrupts = <0 63 4>, <0 63 4>; 592 reg = <0x0 0xff0e0000 0x0 0x1000>; 593 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 iommus = <&smmu 0x877>; 597 power-domains = <&zynqmp_firmware PD_ETH_3>; 598 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; 599 reset-names = "gem3_rst"; 600 }; 601 602 gpio: gpio@ff0a0000 { 603 compatible = "xlnx,zynqmp-gpio-1.0"; 604 status = "disabled"; 605 #address-cells = <0>; 606 #gpio-cells = <0x2>; 607 gpio-controller; 608 interrupt-parent = <&gic>; 609 interrupts = <0 16 4>; 610 interrupt-controller; 611 #interrupt-cells = <2>; 612 reg = <0x0 0xff0a0000 0x0 0x1000>; 613 power-domains = <&zynqmp_firmware PD_GPIO>; 614 }; 615 616 i2c0: i2c@ff020000 { 617 compatible = "cdns,i2c-r1p14"; 618 status = "disabled"; 619 interrupt-parent = <&gic>; 620 interrupts = <0 17 4>; 621 reg = <0x0 0xff020000 0x0 0x1000>; 622 #address-cells = <1>; 623 #size-cells = <0>; 624 power-domains = <&zynqmp_firmware PD_I2C_0>; 625 }; 626 627 i2c1: i2c@ff030000 { 628 compatible = "cdns,i2c-r1p14"; 629 status = "disabled"; 630 interrupt-parent = <&gic>; 631 interrupts = <0 18 4>; 632 reg = <0x0 0xff030000 0x0 0x1000>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 power-domains = <&zynqmp_firmware PD_I2C_1>; 636 }; 637 638 pcie: pcie@fd0e0000 { 639 compatible = "xlnx,nwl-pcie-2.11"; 640 status = "disabled"; 641 #address-cells = <3>; 642 #size-cells = <2>; 643 #interrupt-cells = <1>; 644 msi-controller; 645 device_type = "pci"; 646 interrupt-parent = <&gic>; 647 interrupts = <0 118 4>, 648 <0 117 4>, 649 <0 116 4>, 650 <0 115 4>, /* MSI_1 [63...32] */ 651 <0 114 4>; /* MSI_0 [31...0] */ 652 interrupt-names = "misc", "dummy", "intx", 653 "msi1", "msi0"; 654 msi-parent = <&pcie>; 655 reg = <0x0 0xfd0e0000 0x0 0x1000>, 656 <0x0 0xfd480000 0x0 0x1000>, 657 <0x80 0x00000000 0x0 0x1000000>; 658 reg-names = "breg", "pcireg", "cfg"; 659 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 660 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 661 bus-range = <0x00 0xff>; 662 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 663 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 664 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 665 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 666 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 667 iommus = <&smmu 0x4d0>; 668 power-domains = <&zynqmp_firmware PD_PCIE>; 669 pcie_intc: legacy-interrupt-controller { 670 interrupt-controller; 671 #address-cells = <0>; 672 #interrupt-cells = <1>; 673 }; 674 }; 675 676 qspi: spi@ff0f0000 { 677 compatible = "xlnx,zynqmp-qspi-1.0"; 678 status = "disabled"; 679 clock-names = "ref_clk", "pclk"; 680 interrupts = <0 15 4>; 681 interrupt-parent = <&gic>; 682 num-cs = <1>; 683 reg = <0x0 0xff0f0000 0x0 0x1000>, 684 <0x0 0xc0000000 0x0 0x8000000>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 iommus = <&smmu 0x873>; 688 power-domains = <&zynqmp_firmware PD_QSPI>; 689 }; 690 691 psgtr: phy@fd400000 { 692 compatible = "xlnx,zynqmp-psgtr-v1.1"; 693 status = "disabled"; 694 reg = <0x0 0xfd400000 0x0 0x40000>, 695 <0x0 0xfd3d0000 0x0 0x1000>; 696 reg-names = "serdes", "siou"; 697 #phy-cells = <4>; 698 }; 699 700 rtc: rtc@ffa60000 { 701 compatible = "xlnx,zynqmp-rtc"; 702 status = "disabled"; 703 reg = <0x0 0xffa60000 0x0 0x100>; 704 interrupt-parent = <&gic>; 705 interrupts = <0 26 4>, <0 27 4>; 706 interrupt-names = "alarm", "sec"; 707 calibration = <0x7FFF>; 708 }; 709 710 sata: ahci@fd0c0000 { 711 compatible = "ceva,ahci-1v84"; 712 status = "disabled"; 713 reg = <0x0 0xfd0c0000 0x0 0x2000>; 714 interrupt-parent = <&gic>; 715 interrupts = <0 133 4>; 716 power-domains = <&zynqmp_firmware PD_SATA>; 717 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 718 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, 719 <&smmu 0x4c2>, <&smmu 0x4c3>; 720 }; 721 722 sdhci0: mmc@ff160000 { 723 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 724 status = "disabled"; 725 interrupt-parent = <&gic>; 726 interrupts = <0 48 4>; 727 reg = <0x0 0xff160000 0x0 0x1000>; 728 clock-names = "clk_xin", "clk_ahb"; 729 iommus = <&smmu 0x870>; 730 #clock-cells = <1>; 731 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 732 power-domains = <&zynqmp_firmware PD_SD_0>; 733 }; 734 735 sdhci1: mmc@ff170000 { 736 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 737 status = "disabled"; 738 interrupt-parent = <&gic>; 739 interrupts = <0 49 4>; 740 reg = <0x0 0xff170000 0x0 0x1000>; 741 clock-names = "clk_xin", "clk_ahb"; 742 iommus = <&smmu 0x871>; 743 #clock-cells = <1>; 744 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 745 power-domains = <&zynqmp_firmware PD_SD_1>; 746 }; 747 748 smmu: iommu@fd800000 { 749 compatible = "arm,mmu-500"; 750 reg = <0x0 0xfd800000 0x0 0x20000>; 751 #iommu-cells = <1>; 752 status = "disabled"; 753 #global-interrupts = <1>; 754 interrupt-parent = <&gic>; 755 interrupts = <0 155 4>, 756 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 757 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 758 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 759 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 760 }; 761 762 spi0: spi@ff040000 { 763 compatible = "cdns,spi-r1p6"; 764 status = "disabled"; 765 interrupt-parent = <&gic>; 766 interrupts = <0 19 4>; 767 reg = <0x0 0xff040000 0x0 0x1000>; 768 clock-names = "ref_clk", "pclk"; 769 #address-cells = <1>; 770 #size-cells = <0>; 771 power-domains = <&zynqmp_firmware PD_SPI_0>; 772 }; 773 774 spi1: spi@ff050000 { 775 compatible = "cdns,spi-r1p6"; 776 status = "disabled"; 777 interrupt-parent = <&gic>; 778 interrupts = <0 20 4>; 779 reg = <0x0 0xff050000 0x0 0x1000>; 780 clock-names = "ref_clk", "pclk"; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 power-domains = <&zynqmp_firmware PD_SPI_1>; 784 }; 785 786 ttc0: timer@ff110000 { 787 compatible = "cdns,ttc"; 788 status = "disabled"; 789 interrupt-parent = <&gic>; 790 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 791 reg = <0x0 0xff110000 0x0 0x1000>; 792 timer-width = <32>; 793 power-domains = <&zynqmp_firmware PD_TTC_0>; 794 }; 795 796 ttc1: timer@ff120000 { 797 compatible = "cdns,ttc"; 798 status = "disabled"; 799 interrupt-parent = <&gic>; 800 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 801 reg = <0x0 0xff120000 0x0 0x1000>; 802 timer-width = <32>; 803 power-domains = <&zynqmp_firmware PD_TTC_1>; 804 }; 805 806 ttc2: timer@ff130000 { 807 compatible = "cdns,ttc"; 808 status = "disabled"; 809 interrupt-parent = <&gic>; 810 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 811 reg = <0x0 0xff130000 0x0 0x1000>; 812 timer-width = <32>; 813 power-domains = <&zynqmp_firmware PD_TTC_2>; 814 }; 815 816 ttc3: timer@ff140000 { 817 compatible = "cdns,ttc"; 818 status = "disabled"; 819 interrupt-parent = <&gic>; 820 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 821 reg = <0x0 0xff140000 0x0 0x1000>; 822 timer-width = <32>; 823 power-domains = <&zynqmp_firmware PD_TTC_3>; 824 }; 825 826 uart0: serial@ff000000 { 827 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 828 status = "disabled"; 829 interrupt-parent = <&gic>; 830 interrupts = <0 21 4>; 831 reg = <0x0 0xff000000 0x0 0x1000>; 832 clock-names = "uart_clk", "pclk"; 833 power-domains = <&zynqmp_firmware PD_UART_0>; 834 }; 835 836 uart1: serial@ff010000 { 837 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 838 status = "disabled"; 839 interrupt-parent = <&gic>; 840 interrupts = <0 22 4>; 841 reg = <0x0 0xff010000 0x0 0x1000>; 842 clock-names = "uart_clk", "pclk"; 843 power-domains = <&zynqmp_firmware PD_UART_1>; 844 }; 845 846 usb0: usb@ff9d0000 { 847 #address-cells = <2>; 848 #size-cells = <2>; 849 status = "disabled"; 850 compatible = "xlnx,zynqmp-dwc3"; 851 reg = <0x0 0xff9d0000 0x0 0x100>; 852 power-domains = <&zynqmp_firmware PD_USB_0>; 853 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 854 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 855 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 856 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 857 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; 858 ranges; 859 860 dwc3_0: usb@fe200000 { 861 compatible = "snps,dwc3"; 862 reg = <0x0 0xfe200000 0x0 0x40000>; 863 interrupt-parent = <&gic>; 864 interrupt-names = "dwc_usb3", "otg"; 865 interrupts = <0 65 4>, <0 69 4>; 866 clock-names = "bus_early", "ref"; 867 iommus = <&smmu 0x860>; 868 snps,quirk-frame-length-adjustment = <0x20>; 869 snps,resume-hs-terminations; 870 /* dma-coherent; */ 871 }; 872 }; 873 874 usb1: usb@ff9e0000 { 875 #address-cells = <2>; 876 #size-cells = <2>; 877 status = "disabled"; 878 compatible = "xlnx,zynqmp-dwc3"; 879 reg = <0x0 0xff9e0000 0x0 0x100>; 880 power-domains = <&zynqmp_firmware PD_USB_1>; 881 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 882 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 883 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 884 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 885 ranges; 886 887 dwc3_1: usb@fe300000 { 888 compatible = "snps,dwc3"; 889 reg = <0x0 0xfe300000 0x0 0x40000>; 890 interrupt-parent = <&gic>; 891 interrupt-names = "dwc_usb3", "otg"; 892 interrupts = <0 70 4>, <0 74 4>; 893 clock-names = "bus_early", "ref"; 894 iommus = <&smmu 0x861>; 895 snps,quirk-frame-length-adjustment = <0x20>; 896 snps,resume-hs-terminations; 897 /* dma-coherent; */ 898 }; 899 }; 900 901 watchdog0: watchdog@fd4d0000 { 902 compatible = "cdns,wdt-r1p2"; 903 status = "disabled"; 904 interrupt-parent = <&gic>; 905 interrupts = <0 113 1>; 906 reg = <0x0 0xfd4d0000 0x0 0x1000>; 907 timeout-sec = <60>; 908 reset-on-timeout; 909 }; 910 911 lpd_watchdog: watchdog@ff150000 { 912 compatible = "cdns,wdt-r1p2"; 913 status = "disabled"; 914 interrupt-parent = <&gic>; 915 interrupts = <0 52 1>; 916 reg = <0x0 0xff150000 0x0 0x1000>; 917 timeout-sec = <10>; 918 }; 919 920 xilinx_ams: ams@ffa50000 { 921 compatible = "xlnx,zynqmp-ams"; 922 status = "disabled"; 923 interrupt-parent = <&gic>; 924 interrupts = <0 56 4>; 925 reg = <0x0 0xffa50000 0x0 0x800>; 926 #address-cells = <1>; 927 #size-cells = <1>; 928 #io-channel-cells = <1>; 929 ranges = <0 0 0xffa50800 0x800>; 930 931 ams_ps: ams_ps@0 { 932 compatible = "xlnx,zynqmp-ams-ps"; 933 status = "disabled"; 934 reg = <0x0 0x400>; 935 }; 936 937 ams_pl: ams_pl@400 { 938 compatible = "xlnx,zynqmp-ams-pl"; 939 status = "disabled"; 940 reg = <0x400 0x400>; 941 #address-cells = <1>; 942 #size-cells = <0>; 943 }; 944 }; 945 946 zynqmp_dpdma: dma-controller@fd4c0000 { 947 compatible = "xlnx,zynqmp-dpdma"; 948 status = "disabled"; 949 reg = <0x0 0xfd4c0000 0x0 0x1000>; 950 interrupts = <0 122 4>; 951 interrupt-parent = <&gic>; 952 clock-names = "axi_clk"; 953 power-domains = <&zynqmp_firmware PD_DP>; 954 #dma-cells = <1>; 955 }; 956 957 zynqmp_dpsub: display@fd4a0000 { 958 compatible = "xlnx,zynqmp-dpsub-1.7"; 959 status = "disabled"; 960 reg = <0x0 0xfd4a0000 0x0 0x1000>, 961 <0x0 0xfd4aa000 0x0 0x1000>, 962 <0x0 0xfd4ab000 0x0 0x1000>, 963 <0x0 0xfd4ac000 0x0 0x1000>; 964 reg-names = "dp", "blend", "av_buf", "aud"; 965 interrupts = <0 119 4>; 966 interrupt-parent = <&gic>; 967 clock-names = "dp_apb_clk", "dp_aud_clk", 968 "dp_vtc_pixel_clk_in"; 969 power-domains = <&zynqmp_firmware PD_DP>; 970 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 971 dma-names = "vid0", "vid1", "vid2", "gfx0"; 972 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 973 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 974 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 975 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; 976 977 ports { 978 #address-cells = <1>; 979 #size-cells = <0>; 980 981 port@0 { 982 reg = <0>; 983 }; 984 port@1 { 985 reg = <1>; 986 }; 987 port@2 { 988 reg = <2>; 989 }; 990 port@3 { 991 reg = <3>; 992 }; 993 port@4 { 994 reg = <4>; 995 }; 996 port@5 { 997 reg = <5>; 998 }; 999 }; 1000 }; 1001 }; 1002}; 1003