1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2021, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@amd.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/power/xlnx-zynqmp-power.h> 18#include <dt-bindings/reset/xlnx-zynqmp-resets.h> 19 20/ { 21 compatible = "xlnx,zynqmp"; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu0: cpu@0 { 30 compatible = "arm,cortex-a53"; 31 device_type = "cpu"; 32 enable-method = "psci"; 33 operating-points-v2 = <&cpu_opp_table>; 34 reg = <0x0>; 35 cpu-idle-states = <&CPU_SLEEP_0>; 36 }; 37 38 cpu1: cpu@1 { 39 compatible = "arm,cortex-a53"; 40 device_type = "cpu"; 41 enable-method = "psci"; 42 reg = <0x1>; 43 operating-points-v2 = <&cpu_opp_table>; 44 cpu-idle-states = <&CPU_SLEEP_0>; 45 }; 46 47 cpu2: cpu@2 { 48 compatible = "arm,cortex-a53"; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 reg = <0x2>; 52 operating-points-v2 = <&cpu_opp_table>; 53 cpu-idle-states = <&CPU_SLEEP_0>; 54 }; 55 56 cpu3: cpu@3 { 57 compatible = "arm,cortex-a53"; 58 device_type = "cpu"; 59 enable-method = "psci"; 60 reg = <0x3>; 61 operating-points-v2 = <&cpu_opp_table>; 62 cpu-idle-states = <&CPU_SLEEP_0>; 63 }; 64 65 idle-states { 66 entry-method = "psci"; 67 68 CPU_SLEEP_0: cpu-sleep-0 { 69 compatible = "arm,idle-state"; 70 arm,psci-suspend-param = <0x40000000>; 71 local-timer-stop; 72 entry-latency-us = <300>; 73 exit-latency-us = <600>; 74 min-residency-us = <10000>; 75 }; 76 }; 77 }; 78 79 cpu_opp_table: opp-table-cpu { 80 compatible = "operating-points-v2"; 81 opp-shared; 82 opp00 { 83 opp-hz = /bits/ 64 <1199999988>; 84 opp-microvolt = <1000000>; 85 clock-latency-ns = <500000>; 86 }; 87 opp01 { 88 opp-hz = /bits/ 64 <599999994>; 89 opp-microvolt = <1000000>; 90 clock-latency-ns = <500000>; 91 }; 92 opp02 { 93 opp-hz = /bits/ 64 <399999996>; 94 opp-microvolt = <1000000>; 95 clock-latency-ns = <500000>; 96 }; 97 opp03 { 98 opp-hz = /bits/ 64 <299999997>; 99 opp-microvolt = <1000000>; 100 clock-latency-ns = <500000>; 101 }; 102 }; 103 104 reserved-memory { 105 #address-cells = <2>; 106 #size-cells = <2>; 107 ranges; 108 109 rproc_0_fw_image: memory@3ed00000 { 110 no-map; 111 reg = <0x0 0x3ed00000 0x0 0x40000>; 112 }; 113 114 rproc_1_fw_image: memory@3ef00000 { 115 no-map; 116 reg = <0x0 0x3ef00000 0x0 0x40000>; 117 }; 118 }; 119 120 zynqmp_ipi: zynqmp_ipi { 121 bootph-all; 122 compatible = "xlnx,zynqmp-ipi-mailbox"; 123 interrupt-parent = <&gic>; 124 interrupts = <0 35 4>; 125 xlnx,ipi-id = <0>; 126 #address-cells = <2>; 127 #size-cells = <2>; 128 ranges; 129 130 ipi_mailbox_pmu1: mailbox@ff9905c0 { 131 bootph-all; 132 reg = <0x0 0xff9905c0 0x0 0x20>, 133 <0x0 0xff9905e0 0x0 0x20>, 134 <0x0 0xff990e80 0x0 0x20>, 135 <0x0 0xff990ea0 0x0 0x20>; 136 reg-names = "local_request_region", 137 "local_response_region", 138 "remote_request_region", 139 "remote_response_region"; 140 #mbox-cells = <1>; 141 xlnx,ipi-id = <4>; 142 }; 143 }; 144 145 dcc: dcc { 146 compatible = "arm,dcc"; 147 status = "disabled"; 148 bootph-all; 149 }; 150 151 pmu { 152 compatible = "arm,armv8-pmuv3"; 153 interrupt-parent = <&gic>; 154 interrupts = <0 143 4>, 155 <0 144 4>, 156 <0 145 4>, 157 <0 146 4>; 158 interrupt-affinity = <&cpu0>, 159 <&cpu1>, 160 <&cpu2>, 161 <&cpu3>; 162 }; 163 164 psci { 165 compatible = "arm,psci-0.2"; 166 method = "smc"; 167 }; 168 169 firmware { 170 zynqmp_firmware: zynqmp-firmware { 171 compatible = "xlnx,zynqmp-firmware"; 172 #power-domain-cells = <1>; 173 method = "smc"; 174 bootph-all; 175 176 zynqmp_power: zynqmp-power { 177 bootph-all; 178 compatible = "xlnx,zynqmp-power"; 179 interrupt-parent = <&gic>; 180 interrupts = <0 35 4>; 181 mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; 182 mbox-names = "tx", "rx"; 183 }; 184 185 nvmem_firmware { 186 compatible = "xlnx,zynqmp-nvmem-fw"; 187 #address-cells = <1>; 188 #size-cells = <1>; 189 190 soc_revision: soc_revision@0 { 191 reg = <0x0 0x4>; 192 }; 193 }; 194 195 zynqmp_pcap: pcap { 196 compatible = "xlnx,zynqmp-pcap-fpga"; 197 }; 198 199 xlnx_aes: zynqmp-aes { 200 compatible = "xlnx,zynqmp-aes"; 201 }; 202 203 zynqmp_reset: reset-controller { 204 compatible = "xlnx,zynqmp-reset"; 205 #reset-cells = <1>; 206 }; 207 208 pinctrl0: pinctrl { 209 compatible = "xlnx,zynqmp-pinctrl"; 210 status = "disabled"; 211 }; 212 213 modepin_gpio: gpio { 214 compatible = "xlnx,zynqmp-gpio-modepin"; 215 gpio-controller; 216 #gpio-cells = <2>; 217 }; 218 }; 219 }; 220 221 timer { 222 compatible = "arm,armv8-timer"; 223 interrupt-parent = <&gic>; 224 interrupts = <1 13 0xf08>, 225 <1 14 0xf08>, 226 <1 11 0xf08>, 227 <1 10 0xf08>; 228 }; 229 230 fpga_full: fpga-full { 231 compatible = "fpga-region"; 232 fpga-mgr = <&zynqmp_pcap>; 233 #address-cells = <2>; 234 #size-cells = <2>; 235 ranges; 236 }; 237 238 remoteproc { 239 compatible = "xlnx,zynqmp-r5fss"; 240 xlnx,cluster-mode = <1>; 241 242 r5f-0 { 243 compatible = "xlnx,zynqmp-r5f"; 244 power-domains = <&zynqmp_firmware PD_RPU_0>; 245 memory-region = <&rproc_0_fw_image>; 246 }; 247 248 r5f-1 { 249 compatible = "xlnx,zynqmp-r5f"; 250 power-domains = <&zynqmp_firmware PD_RPU_1>; 251 memory-region = <&rproc_1_fw_image>; 252 }; 253 }; 254 255 amba: axi { 256 compatible = "simple-bus"; 257 bootph-all; 258 #address-cells = <2>; 259 #size-cells = <2>; 260 ranges; 261 262 can0: can@ff060000 { 263 compatible = "xlnx,zynq-can-1.0"; 264 status = "disabled"; 265 clock-names = "can_clk", "pclk"; 266 reg = <0x0 0xff060000 0x0 0x1000>; 267 interrupts = <0 23 4>; 268 interrupt-parent = <&gic>; 269 tx-fifo-depth = <0x40>; 270 rx-fifo-depth = <0x40>; 271 power-domains = <&zynqmp_firmware PD_CAN_0>; 272 }; 273 274 can1: can@ff070000 { 275 compatible = "xlnx,zynq-can-1.0"; 276 status = "disabled"; 277 clock-names = "can_clk", "pclk"; 278 reg = <0x0 0xff070000 0x0 0x1000>; 279 interrupts = <0 24 4>; 280 interrupt-parent = <&gic>; 281 tx-fifo-depth = <0x40>; 282 rx-fifo-depth = <0x40>; 283 power-domains = <&zynqmp_firmware PD_CAN_1>; 284 }; 285 286 cci: cci@fd6e0000 { 287 compatible = "arm,cci-400"; 288 status = "disabled"; 289 reg = <0x0 0xfd6e0000 0x0 0x9000>; 290 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 291 #address-cells = <1>; 292 #size-cells = <1>; 293 294 pmu@9000 { 295 compatible = "arm,cci-400-pmu,r1"; 296 reg = <0x9000 0x5000>; 297 interrupt-parent = <&gic>; 298 interrupts = <0 123 4>, 299 <0 123 4>, 300 <0 123 4>, 301 <0 123 4>, 302 <0 123 4>; 303 }; 304 }; 305 306 /* GDMA */ 307 fpd_dma_chan1: dma-controller@fd500000 { 308 status = "disabled"; 309 compatible = "xlnx,zynqmp-dma-1.0"; 310 reg = <0x0 0xfd500000 0x0 0x1000>; 311 interrupt-parent = <&gic>; 312 interrupts = <0 124 4>; 313 clock-names = "clk_main", "clk_apb"; 314 #dma-cells = <1>; 315 xlnx,bus-width = <128>; 316 iommus = <&smmu 0x14e8>; 317 power-domains = <&zynqmp_firmware PD_GDMA>; 318 }; 319 320 fpd_dma_chan2: dma-controller@fd510000 { 321 status = "disabled"; 322 compatible = "xlnx,zynqmp-dma-1.0"; 323 reg = <0x0 0xfd510000 0x0 0x1000>; 324 interrupt-parent = <&gic>; 325 interrupts = <0 125 4>; 326 clock-names = "clk_main", "clk_apb"; 327 #dma-cells = <1>; 328 xlnx,bus-width = <128>; 329 iommus = <&smmu 0x14e9>; 330 power-domains = <&zynqmp_firmware PD_GDMA>; 331 }; 332 333 fpd_dma_chan3: dma-controller@fd520000 { 334 status = "disabled"; 335 compatible = "xlnx,zynqmp-dma-1.0"; 336 reg = <0x0 0xfd520000 0x0 0x1000>; 337 interrupt-parent = <&gic>; 338 interrupts = <0 126 4>; 339 clock-names = "clk_main", "clk_apb"; 340 #dma-cells = <1>; 341 xlnx,bus-width = <128>; 342 iommus = <&smmu 0x14ea>; 343 power-domains = <&zynqmp_firmware PD_GDMA>; 344 }; 345 346 fpd_dma_chan4: dma-controller@fd530000 { 347 status = "disabled"; 348 compatible = "xlnx,zynqmp-dma-1.0"; 349 reg = <0x0 0xfd530000 0x0 0x1000>; 350 interrupt-parent = <&gic>; 351 interrupts = <0 127 4>; 352 clock-names = "clk_main", "clk_apb"; 353 #dma-cells = <1>; 354 xlnx,bus-width = <128>; 355 iommus = <&smmu 0x14eb>; 356 power-domains = <&zynqmp_firmware PD_GDMA>; 357 }; 358 359 fpd_dma_chan5: dma-controller@fd540000 { 360 status = "disabled"; 361 compatible = "xlnx,zynqmp-dma-1.0"; 362 reg = <0x0 0xfd540000 0x0 0x1000>; 363 interrupt-parent = <&gic>; 364 interrupts = <0 128 4>; 365 clock-names = "clk_main", "clk_apb"; 366 #dma-cells = <1>; 367 xlnx,bus-width = <128>; 368 iommus = <&smmu 0x14ec>; 369 power-domains = <&zynqmp_firmware PD_GDMA>; 370 }; 371 372 fpd_dma_chan6: dma-controller@fd550000 { 373 status = "disabled"; 374 compatible = "xlnx,zynqmp-dma-1.0"; 375 reg = <0x0 0xfd550000 0x0 0x1000>; 376 interrupt-parent = <&gic>; 377 interrupts = <0 129 4>; 378 clock-names = "clk_main", "clk_apb"; 379 #dma-cells = <1>; 380 xlnx,bus-width = <128>; 381 iommus = <&smmu 0x14ed>; 382 power-domains = <&zynqmp_firmware PD_GDMA>; 383 }; 384 385 fpd_dma_chan7: dma-controller@fd560000 { 386 status = "disabled"; 387 compatible = "xlnx,zynqmp-dma-1.0"; 388 reg = <0x0 0xfd560000 0x0 0x1000>; 389 interrupt-parent = <&gic>; 390 interrupts = <0 130 4>; 391 clock-names = "clk_main", "clk_apb"; 392 #dma-cells = <1>; 393 xlnx,bus-width = <128>; 394 iommus = <&smmu 0x14ee>; 395 power-domains = <&zynqmp_firmware PD_GDMA>; 396 }; 397 398 fpd_dma_chan8: dma-controller@fd570000 { 399 status = "disabled"; 400 compatible = "xlnx,zynqmp-dma-1.0"; 401 reg = <0x0 0xfd570000 0x0 0x1000>; 402 interrupt-parent = <&gic>; 403 interrupts = <0 131 4>; 404 clock-names = "clk_main", "clk_apb"; 405 #dma-cells = <1>; 406 xlnx,bus-width = <128>; 407 iommus = <&smmu 0x14ef>; 408 power-domains = <&zynqmp_firmware PD_GDMA>; 409 }; 410 411 gic: interrupt-controller@f9010000 { 412 compatible = "arm,gic-400"; 413 #interrupt-cells = <3>; 414 reg = <0x0 0xf9010000 0x0 0x10000>, 415 <0x0 0xf9020000 0x0 0x20000>, 416 <0x0 0xf9040000 0x0 0x20000>, 417 <0x0 0xf9060000 0x0 0x20000>; 418 interrupt-controller; 419 interrupt-parent = <&gic>; 420 interrupts = <1 9 0xf04>; 421 }; 422 423 gpu: gpu@fd4b0000 { 424 status = "disabled"; 425 compatible = "xlnx,zynqmp-mali", "arm,mali-400"; 426 reg = <0x0 0xfd4b0000 0x0 0x10000>; 427 interrupt-parent = <&gic>; 428 interrupts = <0 132 4>, <0 132 4>, <0 132 4>, 429 <0 132 4>, <0 132 4>, <0 132 4>; 430 interrupt-names = "gp", "gpmmu", "pp0", "ppmmu0", "pp1", "ppmmu1"; 431 clock-names = "bus", "core"; 432 power-domains = <&zynqmp_firmware PD_GPU>; 433 }; 434 435 /* LPDDMA default allows only secured access. inorder to enable 436 * These dma channels, Users should ensure that these dma 437 * Channels are allowed for non secure access. 438 */ 439 lpd_dma_chan1: dma-controller@ffa80000 { 440 status = "disabled"; 441 compatible = "xlnx,zynqmp-dma-1.0"; 442 reg = <0x0 0xffa80000 0x0 0x1000>; 443 interrupt-parent = <&gic>; 444 interrupts = <0 77 4>; 445 clock-names = "clk_main", "clk_apb"; 446 #dma-cells = <1>; 447 xlnx,bus-width = <64>; 448 iommus = <&smmu 0x868>; 449 power-domains = <&zynqmp_firmware PD_ADMA>; 450 }; 451 452 lpd_dma_chan2: dma-controller@ffa90000 { 453 status = "disabled"; 454 compatible = "xlnx,zynqmp-dma-1.0"; 455 reg = <0x0 0xffa90000 0x0 0x1000>; 456 interrupt-parent = <&gic>; 457 interrupts = <0 78 4>; 458 clock-names = "clk_main", "clk_apb"; 459 #dma-cells = <1>; 460 xlnx,bus-width = <64>; 461 iommus = <&smmu 0x869>; 462 power-domains = <&zynqmp_firmware PD_ADMA>; 463 }; 464 465 lpd_dma_chan3: dma-controller@ffaa0000 { 466 status = "disabled"; 467 compatible = "xlnx,zynqmp-dma-1.0"; 468 reg = <0x0 0xffaa0000 0x0 0x1000>; 469 interrupt-parent = <&gic>; 470 interrupts = <0 79 4>; 471 clock-names = "clk_main", "clk_apb"; 472 #dma-cells = <1>; 473 xlnx,bus-width = <64>; 474 iommus = <&smmu 0x86a>; 475 power-domains = <&zynqmp_firmware PD_ADMA>; 476 }; 477 478 lpd_dma_chan4: dma-controller@ffab0000 { 479 status = "disabled"; 480 compatible = "xlnx,zynqmp-dma-1.0"; 481 reg = <0x0 0xffab0000 0x0 0x1000>; 482 interrupt-parent = <&gic>; 483 interrupts = <0 80 4>; 484 clock-names = "clk_main", "clk_apb"; 485 #dma-cells = <1>; 486 xlnx,bus-width = <64>; 487 iommus = <&smmu 0x86b>; 488 power-domains = <&zynqmp_firmware PD_ADMA>; 489 }; 490 491 lpd_dma_chan5: dma-controller@ffac0000 { 492 status = "disabled"; 493 compatible = "xlnx,zynqmp-dma-1.0"; 494 reg = <0x0 0xffac0000 0x0 0x1000>; 495 interrupt-parent = <&gic>; 496 interrupts = <0 81 4>; 497 clock-names = "clk_main", "clk_apb"; 498 #dma-cells = <1>; 499 xlnx,bus-width = <64>; 500 iommus = <&smmu 0x86c>; 501 power-domains = <&zynqmp_firmware PD_ADMA>; 502 }; 503 504 lpd_dma_chan6: dma-controller@ffad0000 { 505 status = "disabled"; 506 compatible = "xlnx,zynqmp-dma-1.0"; 507 reg = <0x0 0xffad0000 0x0 0x1000>; 508 interrupt-parent = <&gic>; 509 interrupts = <0 82 4>; 510 clock-names = "clk_main", "clk_apb"; 511 #dma-cells = <1>; 512 xlnx,bus-width = <64>; 513 iommus = <&smmu 0x86d>; 514 power-domains = <&zynqmp_firmware PD_ADMA>; 515 }; 516 517 lpd_dma_chan7: dma-controller@ffae0000 { 518 status = "disabled"; 519 compatible = "xlnx,zynqmp-dma-1.0"; 520 reg = <0x0 0xffae0000 0x0 0x1000>; 521 interrupt-parent = <&gic>; 522 interrupts = <0 83 4>; 523 clock-names = "clk_main", "clk_apb"; 524 #dma-cells = <1>; 525 xlnx,bus-width = <64>; 526 iommus = <&smmu 0x86e>; 527 power-domains = <&zynqmp_firmware PD_ADMA>; 528 }; 529 530 lpd_dma_chan8: dma-controller@ffaf0000 { 531 status = "disabled"; 532 compatible = "xlnx,zynqmp-dma-1.0"; 533 reg = <0x0 0xffaf0000 0x0 0x1000>; 534 interrupt-parent = <&gic>; 535 interrupts = <0 84 4>; 536 clock-names = "clk_main", "clk_apb"; 537 #dma-cells = <1>; 538 xlnx,bus-width = <64>; 539 iommus = <&smmu 0x86f>; 540 power-domains = <&zynqmp_firmware PD_ADMA>; 541 }; 542 543 mc: memory-controller@fd070000 { 544 compatible = "xlnx,zynqmp-ddrc-2.40a"; 545 reg = <0x0 0xfd070000 0x0 0x30000>; 546 interrupt-parent = <&gic>; 547 interrupts = <0 112 4>; 548 }; 549 550 nand0: nand-controller@ff100000 { 551 compatible = "xlnx,zynqmp-nand-controller", "arasan,nfc-v3p10"; 552 status = "disabled"; 553 reg = <0x0 0xff100000 0x0 0x1000>; 554 clock-names = "controller", "bus"; 555 interrupt-parent = <&gic>; 556 interrupts = <0 14 4>; 557 #address-cells = <1>; 558 #size-cells = <0>; 559 iommus = <&smmu 0x872>; 560 power-domains = <&zynqmp_firmware PD_NAND>; 561 }; 562 563 gem0: ethernet@ff0b0000 { 564 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 565 status = "disabled"; 566 interrupt-parent = <&gic>; 567 interrupts = <0 57 4>, <0 57 4>; 568 reg = <0x0 0xff0b0000 0x0 0x1000>; 569 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 570 #address-cells = <1>; 571 #size-cells = <0>; 572 iommus = <&smmu 0x874>; 573 power-domains = <&zynqmp_firmware PD_ETH_0>; 574 resets = <&zynqmp_reset ZYNQMP_RESET_GEM0>; 575 reset-names = "gem0_rst"; 576 }; 577 578 gem1: ethernet@ff0c0000 { 579 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 580 status = "disabled"; 581 interrupt-parent = <&gic>; 582 interrupts = <0 59 4>, <0 59 4>; 583 reg = <0x0 0xff0c0000 0x0 0x1000>; 584 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 iommus = <&smmu 0x875>; 588 power-domains = <&zynqmp_firmware PD_ETH_1>; 589 resets = <&zynqmp_reset ZYNQMP_RESET_GEM1>; 590 reset-names = "gem1_rst"; 591 }; 592 593 gem2: ethernet@ff0d0000 { 594 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 595 status = "disabled"; 596 interrupt-parent = <&gic>; 597 interrupts = <0 61 4>, <0 61 4>; 598 reg = <0x0 0xff0d0000 0x0 0x1000>; 599 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 iommus = <&smmu 0x876>; 603 power-domains = <&zynqmp_firmware PD_ETH_2>; 604 resets = <&zynqmp_reset ZYNQMP_RESET_GEM2>; 605 reset-names = "gem2_rst"; 606 }; 607 608 gem3: ethernet@ff0e0000 { 609 compatible = "xlnx,zynqmp-gem", "cdns,gem"; 610 status = "disabled"; 611 interrupt-parent = <&gic>; 612 interrupts = <0 63 4>, <0 63 4>; 613 reg = <0x0 0xff0e0000 0x0 0x1000>; 614 clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk"; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 iommus = <&smmu 0x877>; 618 power-domains = <&zynqmp_firmware PD_ETH_3>; 619 resets = <&zynqmp_reset ZYNQMP_RESET_GEM3>; 620 reset-names = "gem3_rst"; 621 }; 622 623 gpio: gpio@ff0a0000 { 624 compatible = "xlnx,zynqmp-gpio-1.0"; 625 status = "disabled"; 626 #gpio-cells = <0x2>; 627 gpio-controller; 628 interrupt-parent = <&gic>; 629 interrupts = <0 16 4>; 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 reg = <0x0 0xff0a0000 0x0 0x1000>; 633 power-domains = <&zynqmp_firmware PD_GPIO>; 634 }; 635 636 i2c0: i2c@ff020000 { 637 compatible = "cdns,i2c-r1p14"; 638 status = "disabled"; 639 interrupt-parent = <&gic>; 640 interrupts = <0 17 4>; 641 reg = <0x0 0xff020000 0x0 0x1000>; 642 #address-cells = <1>; 643 #size-cells = <0>; 644 power-domains = <&zynqmp_firmware PD_I2C_0>; 645 }; 646 647 i2c1: i2c@ff030000 { 648 compatible = "cdns,i2c-r1p14"; 649 status = "disabled"; 650 interrupt-parent = <&gic>; 651 interrupts = <0 18 4>; 652 reg = <0x0 0xff030000 0x0 0x1000>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 power-domains = <&zynqmp_firmware PD_I2C_1>; 656 }; 657 658 pcie: pcie@fd0e0000 { 659 compatible = "xlnx,nwl-pcie-2.11"; 660 status = "disabled"; 661 #address-cells = <3>; 662 #size-cells = <2>; 663 #interrupt-cells = <1>; 664 msi-controller; 665 device_type = "pci"; 666 interrupt-parent = <&gic>; 667 interrupts = <0 118 4>, 668 <0 117 4>, 669 <0 116 4>, 670 <0 115 4>, /* MSI_1 [63...32] */ 671 <0 114 4>; /* MSI_0 [31...0] */ 672 interrupt-names = "misc", "dummy", "intx", 673 "msi1", "msi0"; 674 msi-parent = <&pcie>; 675 reg = <0x0 0xfd0e0000 0x0 0x1000>, 676 <0x0 0xfd480000 0x0 0x1000>, 677 <0x80 0x00000000 0x0 0x1000000>; 678 reg-names = "breg", "pcireg", "cfg"; 679 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */ 680 <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 681 bus-range = <0x00 0xff>; 682 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 683 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 684 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 685 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 686 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 687 iommus = <&smmu 0x4d0>; 688 power-domains = <&zynqmp_firmware PD_PCIE>; 689 pcie_intc: legacy-interrupt-controller { 690 interrupt-controller; 691 #address-cells = <0>; 692 #interrupt-cells = <1>; 693 }; 694 }; 695 696 qspi: spi@ff0f0000 { 697 bootph-all; 698 compatible = "xlnx,zynqmp-qspi-1.0"; 699 status = "disabled"; 700 clock-names = "ref_clk", "pclk"; 701 interrupts = <0 15 4>; 702 interrupt-parent = <&gic>; 703 num-cs = <1>; 704 reg = <0x0 0xff0f0000 0x0 0x1000>, 705 <0x0 0xc0000000 0x0 0x8000000>; 706 #address-cells = <1>; 707 #size-cells = <0>; 708 iommus = <&smmu 0x873>; 709 power-domains = <&zynqmp_firmware PD_QSPI>; 710 }; 711 712 psgtr: phy@fd400000 { 713 compatible = "xlnx,zynqmp-psgtr-v1.1"; 714 status = "disabled"; 715 reg = <0x0 0xfd400000 0x0 0x40000>, 716 <0x0 0xfd3d0000 0x0 0x1000>; 717 reg-names = "serdes", "siou"; 718 #phy-cells = <4>; 719 }; 720 721 rtc: rtc@ffa60000 { 722 compatible = "xlnx,zynqmp-rtc"; 723 status = "disabled"; 724 reg = <0x0 0xffa60000 0x0 0x100>; 725 interrupt-parent = <&gic>; 726 interrupts = <0 26 4>, <0 27 4>; 727 interrupt-names = "alarm", "sec"; 728 calibration = <0x7FFF>; 729 }; 730 731 sata: ahci@fd0c0000 { 732 compatible = "ceva,ahci-1v84"; 733 status = "disabled"; 734 reg = <0x0 0xfd0c0000 0x0 0x2000>; 735 interrupt-parent = <&gic>; 736 interrupts = <0 133 4>; 737 power-domains = <&zynqmp_firmware PD_SATA>; 738 resets = <&zynqmp_reset ZYNQMP_RESET_SATA>; 739 iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, 740 <&smmu 0x4c2>, <&smmu 0x4c3>; 741 }; 742 743 sdhci0: mmc@ff160000 { 744 bootph-all; 745 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 746 status = "disabled"; 747 interrupt-parent = <&gic>; 748 interrupts = <0 48 4>; 749 reg = <0x0 0xff160000 0x0 0x1000>; 750 clock-names = "clk_xin", "clk_ahb"; 751 iommus = <&smmu 0x870>; 752 #clock-cells = <1>; 753 clock-output-names = "clk_out_sd0", "clk_in_sd0"; 754 power-domains = <&zynqmp_firmware PD_SD_0>; 755 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO0>; 756 }; 757 758 sdhci1: mmc@ff170000 { 759 bootph-all; 760 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; 761 status = "disabled"; 762 interrupt-parent = <&gic>; 763 interrupts = <0 49 4>; 764 reg = <0x0 0xff170000 0x0 0x1000>; 765 clock-names = "clk_xin", "clk_ahb"; 766 iommus = <&smmu 0x871>; 767 #clock-cells = <1>; 768 clock-output-names = "clk_out_sd1", "clk_in_sd1"; 769 power-domains = <&zynqmp_firmware PD_SD_1>; 770 resets = <&zynqmp_reset ZYNQMP_RESET_SDIO1>; 771 }; 772 773 smmu: iommu@fd800000 { 774 compatible = "arm,mmu-500"; 775 reg = <0x0 0xfd800000 0x0 0x20000>; 776 #iommu-cells = <1>; 777 status = "disabled"; 778 #global-interrupts = <1>; 779 interrupt-parent = <&gic>; 780 interrupts = <0 155 4>, 781 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 782 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 783 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 784 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 785 }; 786 787 spi0: spi@ff040000 { 788 compatible = "cdns,spi-r1p6"; 789 status = "disabled"; 790 interrupt-parent = <&gic>; 791 interrupts = <0 19 4>; 792 reg = <0x0 0xff040000 0x0 0x1000>; 793 clock-names = "ref_clk", "pclk"; 794 #address-cells = <1>; 795 #size-cells = <0>; 796 power-domains = <&zynqmp_firmware PD_SPI_0>; 797 }; 798 799 spi1: spi@ff050000 { 800 compatible = "cdns,spi-r1p6"; 801 status = "disabled"; 802 interrupt-parent = <&gic>; 803 interrupts = <0 20 4>; 804 reg = <0x0 0xff050000 0x0 0x1000>; 805 clock-names = "ref_clk", "pclk"; 806 #address-cells = <1>; 807 #size-cells = <0>; 808 power-domains = <&zynqmp_firmware PD_SPI_1>; 809 }; 810 811 ttc0: timer@ff110000 { 812 compatible = "cdns,ttc"; 813 status = "disabled"; 814 interrupt-parent = <&gic>; 815 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 816 reg = <0x0 0xff110000 0x0 0x1000>; 817 timer-width = <32>; 818 power-domains = <&zynqmp_firmware PD_TTC_0>; 819 }; 820 821 ttc1: timer@ff120000 { 822 compatible = "cdns,ttc"; 823 status = "disabled"; 824 interrupt-parent = <&gic>; 825 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 826 reg = <0x0 0xff120000 0x0 0x1000>; 827 timer-width = <32>; 828 power-domains = <&zynqmp_firmware PD_TTC_1>; 829 }; 830 831 ttc2: timer@ff130000 { 832 compatible = "cdns,ttc"; 833 status = "disabled"; 834 interrupt-parent = <&gic>; 835 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 836 reg = <0x0 0xff130000 0x0 0x1000>; 837 timer-width = <32>; 838 power-domains = <&zynqmp_firmware PD_TTC_2>; 839 }; 840 841 ttc3: timer@ff140000 { 842 compatible = "cdns,ttc"; 843 status = "disabled"; 844 interrupt-parent = <&gic>; 845 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 846 reg = <0x0 0xff140000 0x0 0x1000>; 847 timer-width = <32>; 848 power-domains = <&zynqmp_firmware PD_TTC_3>; 849 }; 850 851 uart0: serial@ff000000 { 852 bootph-all; 853 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 854 status = "disabled"; 855 interrupt-parent = <&gic>; 856 interrupts = <0 21 4>; 857 reg = <0x0 0xff000000 0x0 0x1000>; 858 clock-names = "uart_clk", "pclk"; 859 power-domains = <&zynqmp_firmware PD_UART_0>; 860 }; 861 862 uart1: serial@ff010000 { 863 bootph-all; 864 compatible = "xlnx,zynqmp-uart", "cdns,uart-r1p12"; 865 status = "disabled"; 866 interrupt-parent = <&gic>; 867 interrupts = <0 22 4>; 868 reg = <0x0 0xff010000 0x0 0x1000>; 869 clock-names = "uart_clk", "pclk"; 870 power-domains = <&zynqmp_firmware PD_UART_1>; 871 }; 872 873 usb0: usb@ff9d0000 { 874 #address-cells = <2>; 875 #size-cells = <2>; 876 status = "disabled"; 877 compatible = "xlnx,zynqmp-dwc3"; 878 reg = <0x0 0xff9d0000 0x0 0x100>; 879 power-domains = <&zynqmp_firmware PD_USB_0>; 880 resets = <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, 881 <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, 882 <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; 883 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 884 reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; 885 ranges; 886 887 dwc3_0: usb@fe200000 { 888 compatible = "snps,dwc3"; 889 reg = <0x0 0xfe200000 0x0 0x40000>; 890 interrupt-parent = <&gic>; 891 interrupt-names = "dwc_usb3", "otg"; 892 interrupts = <0 65 4>, <0 69 4>; 893 clock-names = "bus_early", "ref"; 894 iommus = <&smmu 0x860>; 895 snps,quirk-frame-length-adjustment = <0x20>; 896 snps,resume-hs-terminations; 897 /* dma-coherent; */ 898 }; 899 }; 900 901 usb1: usb@ff9e0000 { 902 #address-cells = <2>; 903 #size-cells = <2>; 904 status = "disabled"; 905 compatible = "xlnx,zynqmp-dwc3"; 906 reg = <0x0 0xff9e0000 0x0 0x100>; 907 power-domains = <&zynqmp_firmware PD_USB_1>; 908 resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, 909 <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, 910 <&zynqmp_reset ZYNQMP_RESET_USB1_APB>; 911 reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; 912 ranges; 913 914 dwc3_1: usb@fe300000 { 915 compatible = "snps,dwc3"; 916 reg = <0x0 0xfe300000 0x0 0x40000>; 917 interrupt-parent = <&gic>; 918 interrupt-names = "dwc_usb3", "otg"; 919 interrupts = <0 70 4>, <0 74 4>; 920 clock-names = "bus_early", "ref"; 921 iommus = <&smmu 0x861>; 922 snps,quirk-frame-length-adjustment = <0x20>; 923 snps,resume-hs-terminations; 924 /* dma-coherent; */ 925 }; 926 }; 927 928 watchdog0: watchdog@fd4d0000 { 929 compatible = "cdns,wdt-r1p2"; 930 status = "disabled"; 931 interrupt-parent = <&gic>; 932 interrupts = <0 113 1>; 933 reg = <0x0 0xfd4d0000 0x0 0x1000>; 934 timeout-sec = <60>; 935 reset-on-timeout; 936 }; 937 938 lpd_watchdog: watchdog@ff150000 { 939 compatible = "cdns,wdt-r1p2"; 940 status = "disabled"; 941 interrupt-parent = <&gic>; 942 interrupts = <0 52 1>; 943 reg = <0x0 0xff150000 0x0 0x1000>; 944 timeout-sec = <10>; 945 }; 946 947 xilinx_ams: ams@ffa50000 { 948 compatible = "xlnx,zynqmp-ams"; 949 status = "disabled"; 950 interrupt-parent = <&gic>; 951 interrupts = <0 56 4>; 952 reg = <0x0 0xffa50000 0x0 0x800>; 953 #address-cells = <1>; 954 #size-cells = <1>; 955 #io-channel-cells = <1>; 956 ranges = <0 0 0xffa50800 0x800>; 957 958 ams_ps: ams-ps@0 { 959 compatible = "xlnx,zynqmp-ams-ps"; 960 status = "disabled"; 961 reg = <0x0 0x400>; 962 }; 963 964 ams_pl: ams-pl@400 { 965 compatible = "xlnx,zynqmp-ams-pl"; 966 status = "disabled"; 967 reg = <0x400 0x400>; 968 #address-cells = <1>; 969 #size-cells = <0>; 970 }; 971 }; 972 973 zynqmp_dpdma: dma-controller@fd4c0000 { 974 compatible = "xlnx,zynqmp-dpdma"; 975 status = "disabled"; 976 reg = <0x0 0xfd4c0000 0x0 0x1000>; 977 interrupts = <0 122 4>; 978 interrupt-parent = <&gic>; 979 clock-names = "axi_clk"; 980 power-domains = <&zynqmp_firmware PD_DP>; 981 #dma-cells = <1>; 982 }; 983 984 zynqmp_dpsub: display@fd4a0000 { 985 bootph-all; 986 compatible = "xlnx,zynqmp-dpsub-1.7"; 987 status = "disabled"; 988 reg = <0x0 0xfd4a0000 0x0 0x1000>, 989 <0x0 0xfd4aa000 0x0 0x1000>, 990 <0x0 0xfd4ab000 0x0 0x1000>, 991 <0x0 0xfd4ac000 0x0 0x1000>; 992 reg-names = "dp", "blend", "av_buf", "aud"; 993 interrupts = <0 119 4>; 994 interrupt-parent = <&gic>; 995 clock-names = "dp_apb_clk", "dp_aud_clk", 996 "dp_vtc_pixel_clk_in"; 997 power-domains = <&zynqmp_firmware PD_DP>; 998 resets = <&zynqmp_reset ZYNQMP_RESET_DP>; 999 dma-names = "vid0", "vid1", "vid2", "gfx0"; 1000 dmas = <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO0>, 1001 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO1>, 1002 <&zynqmp_dpdma ZYNQMP_DPDMA_VIDEO2>, 1003 <&zynqmp_dpdma ZYNQMP_DPDMA_GRAPHICS>; 1004 1005 ports { 1006 #address-cells = <1>; 1007 #size-cells = <0>; 1008 1009 port@0 { 1010 reg = <0>; 1011 }; 1012 port@1 { 1013 reg = <1>; 1014 }; 1015 port@2 { 1016 reg = <2>; 1017 }; 1018 port@3 { 1019 reg = <3>; 1020 }; 1021 port@4 { 1022 reg = <4>; 1023 }; 1024 port@5 { 1025 reg = <5>; 1026 }; 1027 }; 1028 }; 1029 }; 1030}; 1031