1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * dts file for Xilinx ZynqMP 4 * 5 * (C) Copyright 2014 - 2015, Xilinx, Inc. 6 * 7 * Michal Simek <michal.simek@xilinx.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15/ { 16 compatible = "xlnx,zynqmp"; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 compatible = "arm,cortex-a53"; 26 device_type = "cpu"; 27 enable-method = "psci"; 28 operating-points-v2 = <&cpu_opp_table>; 29 reg = <0x0>; 30 cpu-idle-states = <&CPU_SLEEP_0>; 31 }; 32 33 cpu1: cpu@1 { 34 compatible = "arm,cortex-a53"; 35 device_type = "cpu"; 36 enable-method = "psci"; 37 reg = <0x1>; 38 operating-points-v2 = <&cpu_opp_table>; 39 cpu-idle-states = <&CPU_SLEEP_0>; 40 }; 41 42 cpu2: cpu@2 { 43 compatible = "arm,cortex-a53"; 44 device_type = "cpu"; 45 enable-method = "psci"; 46 reg = <0x2>; 47 operating-points-v2 = <&cpu_opp_table>; 48 cpu-idle-states = <&CPU_SLEEP_0>; 49 }; 50 51 cpu3: cpu@3 { 52 compatible = "arm,cortex-a53"; 53 device_type = "cpu"; 54 enable-method = "psci"; 55 reg = <0x3>; 56 operating-points-v2 = <&cpu_opp_table>; 57 cpu-idle-states = <&CPU_SLEEP_0>; 58 }; 59 60 idle-states { 61 entry-method = "psci"; 62 63 CPU_SLEEP_0: cpu-sleep-0 { 64 compatible = "arm,idle-state"; 65 arm,psci-suspend-param = <0x40000000>; 66 local-timer-stop; 67 entry-latency-us = <300>; 68 exit-latency-us = <600>; 69 min-residency-us = <10000>; 70 }; 71 }; 72 }; 73 74 cpu_opp_table: cpu-opp-table { 75 compatible = "operating-points-v2"; 76 opp-shared; 77 opp00 { 78 opp-hz = /bits/ 64 <1199999988>; 79 opp-microvolt = <1000000>; 80 clock-latency-ns = <500000>; 81 }; 82 opp01 { 83 opp-hz = /bits/ 64 <599999994>; 84 opp-microvolt = <1000000>; 85 clock-latency-ns = <500000>; 86 }; 87 opp02 { 88 opp-hz = /bits/ 64 <399999996>; 89 opp-microvolt = <1000000>; 90 clock-latency-ns = <500000>; 91 }; 92 opp03 { 93 opp-hz = /bits/ 64 <299999997>; 94 opp-microvolt = <1000000>; 95 clock-latency-ns = <500000>; 96 }; 97 }; 98 99 dcc: dcc { 100 compatible = "arm,dcc"; 101 status = "disabled"; 102 }; 103 104 pmu { 105 compatible = "arm,armv8-pmuv3"; 106 interrupt-parent = <&gic>; 107 interrupts = <0 143 4>, 108 <0 144 4>, 109 <0 145 4>, 110 <0 146 4>; 111 }; 112 113 psci { 114 compatible = "arm,psci-0.2"; 115 method = "smc"; 116 }; 117 118 firmware { 119 zynqmp_firmware: zynqmp-firmware { 120 compatible = "xlnx,zynqmp-firmware"; 121 method = "smc"; 122 123 nvmem_firmware { 124 compatible = "xlnx,zynqmp-nvmem-fw"; 125 #address-cells = <1>; 126 #size-cells = <1>; 127 128 soc_revision: soc_revision@0 { 129 reg = <0x0 0x4>; 130 }; 131 }; 132 133 zynqmp_pcap: pcap { 134 compatible = "xlnx,zynqmp-pcap-fpga"; 135 }; 136 }; 137 }; 138 139 timer { 140 compatible = "arm,armv8-timer"; 141 interrupt-parent = <&gic>; 142 interrupts = <1 13 0xf08>, 143 <1 14 0xf08>, 144 <1 11 0xf08>, 145 <1 10 0xf08>; 146 }; 147 148 fpga_full: fpga-full { 149 compatible = "fpga-region"; 150 fpga-mgr = <&zynqmp_pcap>; 151 #address-cells = <2>; 152 #size-cells = <2>; 153 ranges; 154 }; 155 156 amba_apu: amba-apu@0 { 157 compatible = "simple-bus"; 158 #address-cells = <2>; 159 #size-cells = <1>; 160 ranges = <0 0 0 0 0xffffffff>; 161 162 gic: interrupt-controller@f9010000 { 163 compatible = "arm,gic-400", "arm,cortex-a15-gic"; 164 #interrupt-cells = <3>; 165 reg = <0x0 0xf9010000 0x10000>, 166 <0x0 0xf9020000 0x20000>, 167 <0x0 0xf9040000 0x20000>, 168 <0x0 0xf9060000 0x20000>; 169 interrupt-controller; 170 interrupt-parent = <&gic>; 171 interrupts = <1 9 0xf04>; 172 }; 173 }; 174 175 amba: amba { 176 compatible = "simple-bus"; 177 #address-cells = <2>; 178 #size-cells = <2>; 179 ranges; 180 181 can0: can@ff060000 { 182 compatible = "xlnx,zynq-can-1.0"; 183 status = "disabled"; 184 clock-names = "can_clk", "pclk"; 185 reg = <0x0 0xff060000 0x0 0x1000>; 186 interrupts = <0 23 4>; 187 interrupt-parent = <&gic>; 188 tx-fifo-depth = <0x40>; 189 rx-fifo-depth = <0x40>; 190 }; 191 192 can1: can@ff070000 { 193 compatible = "xlnx,zynq-can-1.0"; 194 status = "disabled"; 195 clock-names = "can_clk", "pclk"; 196 reg = <0x0 0xff070000 0x0 0x1000>; 197 interrupts = <0 24 4>; 198 interrupt-parent = <&gic>; 199 tx-fifo-depth = <0x40>; 200 rx-fifo-depth = <0x40>; 201 }; 202 203 cci: cci@fd6e0000 { 204 compatible = "arm,cci-400"; 205 reg = <0x0 0xfd6e0000 0x0 0x9000>; 206 ranges = <0x0 0x0 0xfd6e0000 0x10000>; 207 #address-cells = <1>; 208 #size-cells = <1>; 209 210 pmu@9000 { 211 compatible = "arm,cci-400-pmu,r1"; 212 reg = <0x9000 0x5000>; 213 interrupt-parent = <&gic>; 214 interrupts = <0 123 4>, 215 <0 123 4>, 216 <0 123 4>, 217 <0 123 4>, 218 <0 123 4>; 219 }; 220 }; 221 222 /* GDMA */ 223 fpd_dma_chan1: dma@fd500000 { 224 status = "disabled"; 225 compatible = "xlnx,zynqmp-dma-1.0"; 226 reg = <0x0 0xfd500000 0x0 0x1000>; 227 interrupt-parent = <&gic>; 228 interrupts = <0 124 4>; 229 clock-names = "clk_main", "clk_apb"; 230 xlnx,bus-width = <128>; 231 }; 232 233 fpd_dma_chan2: dma@fd510000 { 234 status = "disabled"; 235 compatible = "xlnx,zynqmp-dma-1.0"; 236 reg = <0x0 0xfd510000 0x0 0x1000>; 237 interrupt-parent = <&gic>; 238 interrupts = <0 125 4>; 239 clock-names = "clk_main", "clk_apb"; 240 xlnx,bus-width = <128>; 241 }; 242 243 fpd_dma_chan3: dma@fd520000 { 244 status = "disabled"; 245 compatible = "xlnx,zynqmp-dma-1.0"; 246 reg = <0x0 0xfd520000 0x0 0x1000>; 247 interrupt-parent = <&gic>; 248 interrupts = <0 126 4>; 249 clock-names = "clk_main", "clk_apb"; 250 xlnx,bus-width = <128>; 251 }; 252 253 fpd_dma_chan4: dma@fd530000 { 254 status = "disabled"; 255 compatible = "xlnx,zynqmp-dma-1.0"; 256 reg = <0x0 0xfd530000 0x0 0x1000>; 257 interrupt-parent = <&gic>; 258 interrupts = <0 127 4>; 259 clock-names = "clk_main", "clk_apb"; 260 xlnx,bus-width = <128>; 261 }; 262 263 fpd_dma_chan5: dma@fd540000 { 264 status = "disabled"; 265 compatible = "xlnx,zynqmp-dma-1.0"; 266 reg = <0x0 0xfd540000 0x0 0x1000>; 267 interrupt-parent = <&gic>; 268 interrupts = <0 128 4>; 269 clock-names = "clk_main", "clk_apb"; 270 xlnx,bus-width = <128>; 271 }; 272 273 fpd_dma_chan6: dma@fd550000 { 274 status = "disabled"; 275 compatible = "xlnx,zynqmp-dma-1.0"; 276 reg = <0x0 0xfd550000 0x0 0x1000>; 277 interrupt-parent = <&gic>; 278 interrupts = <0 129 4>; 279 clock-names = "clk_main", "clk_apb"; 280 xlnx,bus-width = <128>; 281 }; 282 283 fpd_dma_chan7: dma@fd560000 { 284 status = "disabled"; 285 compatible = "xlnx,zynqmp-dma-1.0"; 286 reg = <0x0 0xfd560000 0x0 0x1000>; 287 interrupt-parent = <&gic>; 288 interrupts = <0 130 4>; 289 clock-names = "clk_main", "clk_apb"; 290 xlnx,bus-width = <128>; 291 }; 292 293 fpd_dma_chan8: dma@fd570000 { 294 status = "disabled"; 295 compatible = "xlnx,zynqmp-dma-1.0"; 296 reg = <0x0 0xfd570000 0x0 0x1000>; 297 interrupt-parent = <&gic>; 298 interrupts = <0 131 4>; 299 clock-names = "clk_main", "clk_apb"; 300 xlnx,bus-width = <128>; 301 }; 302 303 /* LPDDMA default allows only secured access. inorder to enable 304 * These dma channels, Users should ensure that these dma 305 * Channels are allowed for non secure access. 306 */ 307 lpd_dma_chan1: dma@ffa80000 { 308 status = "disabled"; 309 compatible = "xlnx,zynqmp-dma-1.0"; 310 reg = <0x0 0xffa80000 0x0 0x1000>; 311 interrupt-parent = <&gic>; 312 interrupts = <0 77 4>; 313 clock-names = "clk_main", "clk_apb"; 314 xlnx,bus-width = <64>; 315 }; 316 317 lpd_dma_chan2: dma@ffa90000 { 318 status = "disabled"; 319 compatible = "xlnx,zynqmp-dma-1.0"; 320 reg = <0x0 0xffa90000 0x0 0x1000>; 321 interrupt-parent = <&gic>; 322 interrupts = <0 78 4>; 323 clock-names = "clk_main", "clk_apb"; 324 xlnx,bus-width = <64>; 325 }; 326 327 lpd_dma_chan3: dma@ffaa0000 { 328 status = "disabled"; 329 compatible = "xlnx,zynqmp-dma-1.0"; 330 reg = <0x0 0xffaa0000 0x0 0x1000>; 331 interrupt-parent = <&gic>; 332 interrupts = <0 79 4>; 333 clock-names = "clk_main", "clk_apb"; 334 xlnx,bus-width = <64>; 335 }; 336 337 lpd_dma_chan4: dma@ffab0000 { 338 status = "disabled"; 339 compatible = "xlnx,zynqmp-dma-1.0"; 340 reg = <0x0 0xffab0000 0x0 0x1000>; 341 interrupt-parent = <&gic>; 342 interrupts = <0 80 4>; 343 clock-names = "clk_main", "clk_apb"; 344 xlnx,bus-width = <64>; 345 }; 346 347 lpd_dma_chan5: dma@ffac0000 { 348 status = "disabled"; 349 compatible = "xlnx,zynqmp-dma-1.0"; 350 reg = <0x0 0xffac0000 0x0 0x1000>; 351 interrupt-parent = <&gic>; 352 interrupts = <0 81 4>; 353 clock-names = "clk_main", "clk_apb"; 354 xlnx,bus-width = <64>; 355 }; 356 357 lpd_dma_chan6: dma@ffad0000 { 358 status = "disabled"; 359 compatible = "xlnx,zynqmp-dma-1.0"; 360 reg = <0x0 0xffad0000 0x0 0x1000>; 361 interrupt-parent = <&gic>; 362 interrupts = <0 82 4>; 363 clock-names = "clk_main", "clk_apb"; 364 xlnx,bus-width = <64>; 365 }; 366 367 lpd_dma_chan7: dma@ffae0000 { 368 status = "disabled"; 369 compatible = "xlnx,zynqmp-dma-1.0"; 370 reg = <0x0 0xffae0000 0x0 0x1000>; 371 interrupt-parent = <&gic>; 372 interrupts = <0 83 4>; 373 clock-names = "clk_main", "clk_apb"; 374 xlnx,bus-width = <64>; 375 }; 376 377 lpd_dma_chan8: dma@ffaf0000 { 378 status = "disabled"; 379 compatible = "xlnx,zynqmp-dma-1.0"; 380 reg = <0x0 0xffaf0000 0x0 0x1000>; 381 interrupt-parent = <&gic>; 382 interrupts = <0 84 4>; 383 clock-names = "clk_main", "clk_apb"; 384 xlnx,bus-width = <64>; 385 }; 386 387 mc: memory-controller@fd070000 { 388 compatible = "xlnx,zynqmp-ddrc-2.40a"; 389 reg = <0x0 0xfd070000 0x0 0x30000>; 390 interrupt-parent = <&gic>; 391 interrupts = <0 112 4>; 392 }; 393 394 gem0: ethernet@ff0b0000 { 395 compatible = "cdns,zynqmp-gem", "cdns,gem"; 396 status = "disabled"; 397 interrupt-parent = <&gic>; 398 interrupts = <0 57 4>, <0 57 4>; 399 reg = <0x0 0xff0b0000 0x0 0x1000>; 400 clock-names = "pclk", "hclk", "tx_clk"; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 }; 404 405 gem1: ethernet@ff0c0000 { 406 compatible = "cdns,zynqmp-gem", "cdns,gem"; 407 status = "disabled"; 408 interrupt-parent = <&gic>; 409 interrupts = <0 59 4>, <0 59 4>; 410 reg = <0x0 0xff0c0000 0x0 0x1000>; 411 clock-names = "pclk", "hclk", "tx_clk"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 }; 415 416 gem2: ethernet@ff0d0000 { 417 compatible = "cdns,zynqmp-gem", "cdns,gem"; 418 status = "disabled"; 419 interrupt-parent = <&gic>; 420 interrupts = <0 61 4>, <0 61 4>; 421 reg = <0x0 0xff0d0000 0x0 0x1000>; 422 clock-names = "pclk", "hclk", "tx_clk"; 423 #address-cells = <1>; 424 #size-cells = <0>; 425 }; 426 427 gem3: ethernet@ff0e0000 { 428 compatible = "cdns,zynqmp-gem", "cdns,gem"; 429 status = "disabled"; 430 interrupt-parent = <&gic>; 431 interrupts = <0 63 4>, <0 63 4>; 432 reg = <0x0 0xff0e0000 0x0 0x1000>; 433 clock-names = "pclk", "hclk", "tx_clk"; 434 #address-cells = <1>; 435 #size-cells = <0>; 436 }; 437 438 gpio: gpio@ff0a0000 { 439 compatible = "xlnx,zynqmp-gpio-1.0"; 440 status = "disabled"; 441 #gpio-cells = <0x2>; 442 gpio-controller; 443 interrupt-parent = <&gic>; 444 interrupts = <0 16 4>; 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 reg = <0x0 0xff0a0000 0x0 0x1000>; 448 }; 449 450 i2c0: i2c@ff020000 { 451 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 452 status = "disabled"; 453 interrupt-parent = <&gic>; 454 interrupts = <0 17 4>; 455 reg = <0x0 0xff020000 0x0 0x1000>; 456 #address-cells = <1>; 457 #size-cells = <0>; 458 }; 459 460 i2c1: i2c@ff030000 { 461 compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10"; 462 status = "disabled"; 463 interrupt-parent = <&gic>; 464 interrupts = <0 18 4>; 465 reg = <0x0 0xff030000 0x0 0x1000>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 }; 469 470 pcie: pcie@fd0e0000 { 471 compatible = "xlnx,nwl-pcie-2.11"; 472 status = "disabled"; 473 #address-cells = <3>; 474 #size-cells = <2>; 475 #interrupt-cells = <1>; 476 msi-controller; 477 device_type = "pci"; 478 interrupt-parent = <&gic>; 479 interrupts = <0 118 4>, 480 <0 117 4>, 481 <0 116 4>, 482 <0 115 4>, /* MSI_1 [63...32] */ 483 <0 114 4>; /* MSI_0 [31...0] */ 484 interrupt-names = "misc", "dummy", "intx", 485 "msi1", "msi0"; 486 msi-parent = <&pcie>; 487 reg = <0x0 0xfd0e0000 0x0 0x1000>, 488 <0x0 0xfd480000 0x0 0x1000>, 489 <0x80 0x00000000 0x0 0x1000000>; 490 reg-names = "breg", "pcireg", "cfg"; 491 ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-prefetchable memory */ 492 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */ 493 bus-range = <0x00 0xff>; 494 interrupt-map-mask = <0x0 0x0 0x0 0x7>; 495 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>, 496 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, 497 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, 498 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; 499 pcie_intc: legacy-interrupt-controller { 500 interrupt-controller; 501 #address-cells = <0>; 502 #interrupt-cells = <1>; 503 }; 504 }; 505 506 rtc: rtc@ffa60000 { 507 compatible = "xlnx,zynqmp-rtc"; 508 status = "disabled"; 509 reg = <0x0 0xffa60000 0x0 0x100>; 510 interrupt-parent = <&gic>; 511 interrupts = <0 26 4>, <0 27 4>; 512 interrupt-names = "alarm", "sec"; 513 calibration = <0x8000>; 514 }; 515 516 sata: ahci@fd0c0000 { 517 compatible = "ceva,ahci-1v84"; 518 status = "disabled"; 519 reg = <0x0 0xfd0c0000 0x0 0x2000>; 520 interrupt-parent = <&gic>; 521 interrupts = <0 133 4>; 522 }; 523 524 sdhci0: mmc@ff160000 { 525 compatible = "arasan,sdhci-8.9a"; 526 status = "disabled"; 527 interrupt-parent = <&gic>; 528 interrupts = <0 48 4>; 529 reg = <0x0 0xff160000 0x0 0x1000>; 530 clock-names = "clk_xin", "clk_ahb"; 531 }; 532 533 sdhci1: mmc@ff170000 { 534 compatible = "arasan,sdhci-8.9a"; 535 status = "disabled"; 536 interrupt-parent = <&gic>; 537 interrupts = <0 49 4>; 538 reg = <0x0 0xff170000 0x0 0x1000>; 539 clock-names = "clk_xin", "clk_ahb"; 540 }; 541 542 smmu: smmu@fd800000 { 543 compatible = "arm,mmu-500"; 544 reg = <0x0 0xfd800000 0x0 0x20000>; 545 status = "disabled"; 546 #global-interrupts = <1>; 547 interrupt-parent = <&gic>; 548 interrupts = <0 155 4>, 549 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 550 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 551 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>, 552 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>; 553 }; 554 555 spi0: spi@ff040000 { 556 compatible = "cdns,spi-r1p6"; 557 status = "disabled"; 558 interrupt-parent = <&gic>; 559 interrupts = <0 19 4>; 560 reg = <0x0 0xff040000 0x0 0x1000>; 561 clock-names = "ref_clk", "pclk"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 }; 565 566 spi1: spi@ff050000 { 567 compatible = "cdns,spi-r1p6"; 568 status = "disabled"; 569 interrupt-parent = <&gic>; 570 interrupts = <0 20 4>; 571 reg = <0x0 0xff050000 0x0 0x1000>; 572 clock-names = "ref_clk", "pclk"; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 }; 576 577 ttc0: timer@ff110000 { 578 compatible = "cdns,ttc"; 579 status = "disabled"; 580 interrupt-parent = <&gic>; 581 interrupts = <0 36 4>, <0 37 4>, <0 38 4>; 582 reg = <0x0 0xff110000 0x0 0x1000>; 583 timer-width = <32>; 584 }; 585 586 ttc1: timer@ff120000 { 587 compatible = "cdns,ttc"; 588 status = "disabled"; 589 interrupt-parent = <&gic>; 590 interrupts = <0 39 4>, <0 40 4>, <0 41 4>; 591 reg = <0x0 0xff120000 0x0 0x1000>; 592 timer-width = <32>; 593 }; 594 595 ttc2: timer@ff130000 { 596 compatible = "cdns,ttc"; 597 status = "disabled"; 598 interrupt-parent = <&gic>; 599 interrupts = <0 42 4>, <0 43 4>, <0 44 4>; 600 reg = <0x0 0xff130000 0x0 0x1000>; 601 timer-width = <32>; 602 }; 603 604 ttc3: timer@ff140000 { 605 compatible = "cdns,ttc"; 606 status = "disabled"; 607 interrupt-parent = <&gic>; 608 interrupts = <0 45 4>, <0 46 4>, <0 47 4>; 609 reg = <0x0 0xff140000 0x0 0x1000>; 610 timer-width = <32>; 611 }; 612 613 uart0: serial@ff000000 { 614 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 615 status = "disabled"; 616 interrupt-parent = <&gic>; 617 interrupts = <0 21 4>; 618 reg = <0x0 0xff000000 0x0 0x1000>; 619 clock-names = "uart_clk", "pclk"; 620 }; 621 622 uart1: serial@ff010000 { 623 compatible = "cdns,uart-r1p12", "xlnx,xuartps"; 624 status = "disabled"; 625 interrupt-parent = <&gic>; 626 interrupts = <0 22 4>; 627 reg = <0x0 0xff010000 0x0 0x1000>; 628 clock-names = "uart_clk", "pclk"; 629 }; 630 631 usb0: usb@fe200000 { 632 compatible = "snps,dwc3"; 633 status = "disabled"; 634 interrupt-parent = <&gic>; 635 interrupts = <0 65 4>; 636 reg = <0x0 0xfe200000 0x0 0x40000>; 637 clock-names = "clk_xin", "clk_ahb"; 638 }; 639 640 usb1: usb@fe300000 { 641 compatible = "snps,dwc3"; 642 status = "disabled"; 643 interrupt-parent = <&gic>; 644 interrupts = <0 70 4>; 645 reg = <0x0 0xfe300000 0x0 0x40000>; 646 clock-names = "clk_xin", "clk_ahb"; 647 }; 648 649 watchdog0: watchdog@fd4d0000 { 650 compatible = "cdns,wdt-r1p2"; 651 status = "disabled"; 652 interrupt-parent = <&gic>; 653 interrupts = <0 113 1>; 654 reg = <0x0 0xfd4d0000 0x0 0x1000>; 655 timeout-sec = <10>; 656 }; 657 }; 658}; 659