1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU111
4 *
5 * (C) Copyright 2017 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16
17/ {
18	model = "ZynqMP ZCU111 RevA";
19	compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
20
21	aliases {
22		ethernet0 = &gem3;
23		i2c0 = &i2c0;
24		i2c1 = &i2c1;
25		mmc0 = &sdhci1;
26		rtc0 = &rtc;
27		serial0 = &uart0;
28		serial1 = &dcc;
29	};
30
31	chosen {
32		bootargs = "earlycon";
33		stdout-path = "serial0:115200n8";
34	};
35
36	memory@0 {
37		device_type = "memory";
38		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
39		/* Another 4GB connected to PL */
40	};
41
42	gpio-keys {
43		compatible = "gpio-keys";
44		autorepeat;
45		sw19 {
46			label = "sw19";
47			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
48			linux,code = <KEY_DOWN>;
49			wakeup-source;
50			autorepeat;
51		};
52	};
53
54	leds {
55		compatible = "gpio-leds";
56		heartbeat-led {
57			label = "heartbeat";
58			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
59			linux,default-trigger = "heartbeat";
60		};
61	};
62};
63
64&dcc {
65	status = "okay";
66};
67
68&fpd_dma_chan1 {
69	status = "okay";
70};
71
72&fpd_dma_chan2 {
73	status = "okay";
74};
75
76&fpd_dma_chan3 {
77	status = "okay";
78};
79
80&fpd_dma_chan4 {
81	status = "okay";
82};
83
84&fpd_dma_chan5 {
85	status = "okay";
86};
87
88&fpd_dma_chan6 {
89	status = "okay";
90};
91
92&fpd_dma_chan7 {
93	status = "okay";
94};
95
96&fpd_dma_chan8 {
97	status = "okay";
98};
99
100&gem3 {
101	status = "okay";
102	phy-handle = <&phy0>;
103	phy-mode = "rgmii-id";
104	phy0: phy@c {
105		reg = <0xc>;
106		ti,rx-internal-delay = <0x8>;
107		ti,tx-internal-delay = <0xa>;
108		ti,fifo-depth = <0x1>;
109		ti,dp83867-rxctrl-strap-quirk;
110	};
111};
112
113&gpio {
114	status = "okay";
115};
116
117&i2c0 {
118	status = "okay";
119	clock-frequency = <400000>;
120
121	tca6416_u22: gpio@20 {
122		compatible = "ti,tca6416";
123		reg = <0x20>;
124		gpio-controller; /* interrupt not connected */
125		#gpio-cells = <2>;
126		/*
127		 * IRQ not connected
128		 * Lines:
129		 * 0 - MAX6643_OT_B
130		 * 1 - MAX6643_FANFAIL_B
131		 * 2 - MIO26_PMU_INPUT_LS
132		 * 4 - SFP_SI5382_INT_ALM
133		 * 5 - IIC_MUX_RESET_B
134		 * 6 - GEM3_EXP_RESET_B
135		 * 10 - FMCP_HSPC_PRSNT_M2C_B
136		 * 11 - CLK_SPI_MUX_SEL0
137		 * 12 - CLK_SPI_MUX_SEL1
138		 * 16 - IRPS5401_ALERT_B
139		 * 17 - INA226_PMBUS_ALERT
140		 * 3, 7, 13-15 - not connected
141		 */
142	};
143
144	i2c-mux@75 { /* u23 */
145		compatible = "nxp,pca9544";
146		#address-cells = <1>;
147		#size-cells = <0>;
148		reg = <0x75>;
149		i2c@0 {
150			#address-cells = <1>;
151			#size-cells = <0>;
152			reg = <0>;
153			/* PS_PMBUS */
154			/* PMBUS_ALERT done via pca9544 */
155			ina226@40 { /* u67 */
156				compatible = "ti,ina226";
157				reg = <0x40>;
158				shunt-resistor = <2000>;
159			};
160			ina226@41 { /* u59 */
161				compatible = "ti,ina226";
162				reg = <0x41>;
163				shunt-resistor = <5000>;
164			};
165			ina226@42 { /* u61 */
166				compatible = "ti,ina226";
167				reg = <0x42>;
168				shunt-resistor = <5000>;
169			};
170			ina226@43 { /* u60 */
171				compatible = "ti,ina226";
172				reg = <0x43>;
173				shunt-resistor = <5000>;
174			};
175			ina226@45 { /* u64 */
176				compatible = "ti,ina226";
177				reg = <0x45>;
178				shunt-resistor = <5000>;
179			};
180			ina226@46 { /* u69 */
181				compatible = "ti,ina226";
182				reg = <0x46>;
183				shunt-resistor = <2000>;
184			};
185			ina226@47 { /* u66 */
186				compatible = "ti,ina226";
187				reg = <0x47>;
188				shunt-resistor = <5000>;
189			};
190			ina226@48 { /* u65 */
191				compatible = "ti,ina226";
192				reg = <0x48>;
193				shunt-resistor = <5000>;
194			};
195			ina226@49 { /* u63 */
196				compatible = "ti,ina226";
197				reg = <0x49>;
198				shunt-resistor = <5000>;
199			};
200			ina226@4a { /* u3 */
201				compatible = "ti,ina226";
202				reg = <0x4a>;
203				shunt-resistor = <5000>;
204			};
205			ina226@4b { /* u71 */
206				compatible = "ti,ina226";
207				reg = <0x4b>;
208				shunt-resistor = <5000>;
209			};
210			ina226@4c { /* u77 */
211				compatible = "ti,ina226";
212				reg = <0x4c>;
213				shunt-resistor = <5000>;
214			};
215			ina226@4d { /* u73 */
216				compatible = "ti,ina226";
217				reg = <0x4d>;
218				shunt-resistor = <5000>;
219			};
220			ina226@4e { /* u79 */
221				compatible = "ti,ina226";
222				reg = <0x4e>;
223				shunt-resistor = <5000>;
224			};
225		};
226		i2c@1 {
227			#address-cells = <1>;
228			#size-cells = <0>;
229			reg = <1>;
230			/* NC */
231		};
232		i2c@2 {
233			#address-cells = <1>;
234			#size-cells = <0>;
235			reg = <2>;
236			irps5401_43: irps54012@43 { /* IRPS5401 - u53 check these */
237				reg = <0x43>;
238			};
239			irps5401_44: irps54012@44 { /* IRPS5401 - u55 */
240				reg = <0x44>;
241			};
242			irps5401_45: irps54012@45 { /* IRPS5401 - u57 */
243				reg = <0x45>;
244			};
245			/* u68 IR38064 +0 */
246			/* u70 IR38060 +1 */
247			/* u74 IR38060 +2 */
248			/* u75 IR38060 +6 */
249			/* J19 header too */
250
251		};
252		i2c@3 {
253			#address-cells = <1>;
254			#size-cells = <0>;
255			reg = <3>;
256			/* SYSMON */
257		};
258	};
259};
260
261&i2c1 {
262	status = "okay";
263	clock-frequency = <400000>;
264
265	i2c-mux@74 { /* u26 */
266		compatible = "nxp,pca9548";
267		#address-cells = <1>;
268		#size-cells = <0>;
269		reg = <0x74>;
270		i2c@0 {
271			#address-cells = <1>;
272			#size-cells = <0>;
273			reg = <0>;
274			/*
275			 * IIC_EEPROM 1kB memory which uses 256B blocks
276			 * where every block has different address.
277			 *    0 - 256B address 0x54
278			 * 256B - 512B address 0x55
279			 * 512B - 768B address 0x56
280			 * 768B - 1024B address 0x57
281			 */
282			eeprom: eeprom@54 { /* u88 */
283				compatible = "atmel,24c08";
284				reg = <0x54>;
285			};
286		};
287		i2c@1 {
288			#address-cells = <1>;
289			#size-cells = <0>;
290			reg = <1>;
291			si5341: clock-generator@36 { /* SI5341 - u46 */
292				reg = <0x36>;
293			};
294
295		};
296		i2c@2 {
297			#address-cells = <1>;
298			#size-cells = <0>;
299			reg = <2>;
300			si570_1: clock-generator@5d { /* USER SI570 - u47 */
301				#clock-cells = <0>;
302				compatible = "silabs,si570";
303				reg = <0x5d>;
304				temperature-stability = <50>;
305				factory-fout = <300000000>;
306				clock-frequency = <300000000>;
307			};
308		};
309		i2c@3 {
310			#address-cells = <1>;
311			#size-cells = <0>;
312			reg = <3>;
313			si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
314				#clock-cells = <0>;
315				compatible = "silabs,si570";
316				reg = <0x5d>;
317				temperature-stability = <50>;
318				factory-fout = <156250000>;
319				clock-frequency = <148500000>;
320			};
321		};
322		i2c@4 {
323			#address-cells = <1>;
324			#size-cells = <0>;
325			reg = <4>;
326			si5328: clock-generator@69 { /* SI5328 - u48 */
327				reg = <0x69>;
328			};
329		};
330		i2c@5 {
331			#address-cells = <1>;
332			#size-cells = <0>;
333			reg = <5>;
334				sc18is603@2f { /* sc18is602 - u93 */
335					compatible = "nxp,sc18is603";
336					reg = <0x2f>;
337					/* 4 gpios for CS not handled by driver */
338					/*
339					 * USB2ANY cable or
340					 * LMK04208 - u90 or
341					 * LMX2594 - u102 or
342					 * LMX2594 - u103 or
343					 * LMX2594 - u104
344					 */
345				};
346		};
347		i2c@6 {
348			#address-cells = <1>;
349			#size-cells = <0>;
350			reg = <6>;
351			/* FMC connector */
352		};
353		/* 7 NC */
354	};
355
356	i2c-mux@75 {
357		compatible = "nxp,pca9548"; /* u27 */
358		#address-cells = <1>;
359		#size-cells = <0>;
360		reg = <0x75>;
361
362		i2c@0 {
363			#address-cells = <1>;
364			#size-cells = <0>;
365			reg = <0>;
366			/* FMCP_HSPC_IIC */
367		};
368		i2c@1 {
369			#address-cells = <1>;
370			#size-cells = <0>;
371			reg = <1>;
372			/* NC */
373		};
374		i2c@2 {
375			#address-cells = <1>;
376			#size-cells = <0>;
377			reg = <2>;
378			/* SYSMON */
379		};
380		i2c@3 {
381			#address-cells = <1>;
382			#size-cells = <0>;
383			reg = <3>;
384			/* DDR4 SODIMM */
385		};
386		i2c@4 {
387			#address-cells = <1>;
388			#size-cells = <0>;
389			reg = <4>;
390			/* SFP3 */
391		};
392		i2c@5 {
393			#address-cells = <1>;
394			#size-cells = <0>;
395			reg = <5>;
396			/* SFP2 */
397		};
398		i2c@6 {
399			#address-cells = <1>;
400			#size-cells = <0>;
401			reg = <6>;
402			/* SFP1 */
403		};
404		i2c@7 {
405			#address-cells = <1>;
406			#size-cells = <0>;
407			reg = <7>;
408			/* SFP0 */
409		};
410	};
411};
412
413&rtc {
414	status = "okay";
415};
416
417&sata {
418	status = "okay";
419	/* SATA OOB timing settings */
420	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
421	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
422	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
423	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
424	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
425	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
426	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
427	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
428};
429
430/* SD1 with level shifter */
431&sdhci1 {
432	status = "okay";
433	no-1-8-v;
434};
435
436&uart0 {
437	status = "okay";
438};
439
440/* ULPI SMSC USB3320 */
441&usb0 {
442	status = "okay";
443};
444