1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU111
4 *
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/input/input.h>
15#include <dt-bindings/gpio/gpio.h>
16#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17#include <dt-bindings/phy/phy.h>
18
19/ {
20	model = "ZynqMP ZCU111 RevA";
21	compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
22
23	aliases {
24		ethernet0 = &gem3;
25		i2c0 = &i2c0;
26		i2c1 = &i2c1;
27		mmc0 = &sdhci1;
28		nvmem0 = &eeprom;
29		rtc0 = &rtc;
30		serial0 = &uart0;
31		serial1 = &dcc;
32		spi0 = &qspi;
33		usb0 = &usb0;
34	};
35
36	chosen {
37		bootargs = "earlycon";
38		stdout-path = "serial0:115200n8";
39	};
40
41	memory@0 {
42		device_type = "memory";
43		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44		/* Another 4GB connected to PL */
45	};
46
47	gpio-keys {
48		compatible = "gpio-keys";
49		autorepeat;
50		sw19 {
51			label = "sw19";
52			gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
53			linux,code = <KEY_DOWN>;
54			wakeup-source;
55			autorepeat;
56		};
57	};
58
59	leds {
60		compatible = "gpio-leds";
61		heartbeat-led {
62			label = "heartbeat";
63			gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
64			linux,default-trigger = "heartbeat";
65		};
66	};
67
68	ina226-u67 {
69		compatible = "iio-hwmon";
70		io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
71	};
72	ina226-u59 {
73		compatible = "iio-hwmon";
74		io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
75	};
76	ina226-u61 {
77		compatible = "iio-hwmon";
78		io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
79	};
80	ina226-u60 {
81		compatible = "iio-hwmon";
82		io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
83	};
84	ina226-u64 {
85		compatible = "iio-hwmon";
86		io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
87	};
88	ina226-u69 {
89		compatible = "iio-hwmon";
90		io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
91	};
92	ina226-u66 {
93		compatible = "iio-hwmon";
94		io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
95	};
96	ina226-u65 {
97		compatible = "iio-hwmon";
98		io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
99	};
100	ina226-u63 {
101		compatible = "iio-hwmon";
102		io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
103	};
104	ina226-u3 {
105		compatible = "iio-hwmon";
106		io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
107	};
108	ina226-u71 {
109		compatible = "iio-hwmon";
110		io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
111	};
112	ina226-u77 {
113		compatible = "iio-hwmon";
114		io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
115	};
116	ina226-u73 {
117		compatible = "iio-hwmon";
118		io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
119	};
120	ina226-u79 {
121		compatible = "iio-hwmon";
122		io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
123	};
124
125	/* 48MHz reference crystal */
126	ref48: ref48M {
127		compatible = "fixed-clock";
128		#clock-cells = <0>;
129		clock-frequency = <48000000>;
130	};
131};
132
133&dcc {
134	status = "okay";
135};
136
137&fpd_dma_chan1 {
138	status = "okay";
139};
140
141&fpd_dma_chan2 {
142	status = "okay";
143};
144
145&fpd_dma_chan3 {
146	status = "okay";
147};
148
149&fpd_dma_chan4 {
150	status = "okay";
151};
152
153&fpd_dma_chan5 {
154	status = "okay";
155};
156
157&fpd_dma_chan6 {
158	status = "okay";
159};
160
161&fpd_dma_chan7 {
162	status = "okay";
163};
164
165&fpd_dma_chan8 {
166	status = "okay";
167};
168
169&gem3 {
170	status = "okay";
171	phy-handle = <&phy0>;
172	phy-mode = "rgmii-id";
173	pinctrl-names = "default";
174	pinctrl-0 = <&pinctrl_gem3_default>;
175	phy0: ethernet-phy@c {
176		reg = <0xc>;
177		ti,rx-internal-delay = <0x8>;
178		ti,tx-internal-delay = <0xa>;
179		ti,fifo-depth = <0x1>;
180		ti,dp83867-rxctrl-strap-quirk;
181	};
182};
183
184&gpio {
185	status = "okay";
186	pinctrl-names = "default";
187	pinctrl-0 = <&pinctrl_gpio_default>;
188};
189
190&i2c0 {
191	status = "okay";
192	clock-frequency = <400000>;
193	pinctrl-names = "default", "gpio";
194	pinctrl-0 = <&pinctrl_i2c0_default>;
195	pinctrl-1 = <&pinctrl_i2c0_gpio>;
196	scl-gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
197	sda-gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
198
199	tca6416_u22: gpio@20 {
200		compatible = "ti,tca6416";
201		reg = <0x20>;
202		gpio-controller; /* interrupt not connected */
203		#gpio-cells = <2>;
204		/*
205		 * IRQ not connected
206		 * Lines:
207		 * 0 - MAX6643_OT_B
208		 * 1 - MAX6643_FANFAIL_B
209		 * 2 - MIO26_PMU_INPUT_LS
210		 * 4 - SFP_SI5382_INT_ALM
211		 * 5 - IIC_MUX_RESET_B
212		 * 6 - GEM3_EXP_RESET_B
213		 * 10 - FMCP_HSPC_PRSNT_M2C_B
214		 * 11 - CLK_SPI_MUX_SEL0
215		 * 12 - CLK_SPI_MUX_SEL1
216		 * 16 - IRPS5401_ALERT_B
217		 * 17 - INA226_PMBUS_ALERT
218		 * 3, 7, 13-15 - not connected
219		 */
220	};
221
222	i2c-mux@75 { /* u23 */
223		compatible = "nxp,pca9544";
224		#address-cells = <1>;
225		#size-cells = <0>;
226		reg = <0x75>;
227		i2c@0 {
228			#address-cells = <1>;
229			#size-cells = <0>;
230			reg = <0>;
231			/* PS_PMBUS */
232			/* PMBUS_ALERT done via pca9544 */
233			u67: ina226@40 { /* u67 */
234				compatible = "ti,ina226";
235				#io-channel-cells = <1>;
236				label = "ina226-u67";
237				reg = <0x40>;
238				shunt-resistor = <2000>;
239			};
240			u59: ina226@41 { /* u59 */
241				compatible = "ti,ina226";
242				#io-channel-cells = <1>;
243				label = "ina226-u59";
244				reg = <0x41>;
245				shunt-resistor = <5000>;
246			};
247			u61: ina226@42 { /* u61 */
248				compatible = "ti,ina226";
249				#io-channel-cells = <1>;
250				label = "ina226-u61";
251				reg = <0x42>;
252				shunt-resistor = <5000>;
253			};
254			u60: ina226@43 { /* u60 */
255				compatible = "ti,ina226";
256				#io-channel-cells = <1>;
257				label = "ina226-u60";
258				reg = <0x43>;
259				shunt-resistor = <5000>;
260			};
261			u64: ina226@45 { /* u64 */
262				compatible = "ti,ina226";
263				#io-channel-cells = <1>;
264				label = "ina226-u64";
265				reg = <0x45>;
266				shunt-resistor = <5000>;
267			};
268			u69: ina226@46 { /* u69 */
269				compatible = "ti,ina226";
270				#io-channel-cells = <1>;
271				label = "ina226-u69";
272				reg = <0x46>;
273				shunt-resistor = <2000>;
274			};
275			u66: ina226@47 { /* u66 */
276				compatible = "ti,ina226";
277				#io-channel-cells = <1>;
278				label = "ina226-u66";
279				reg = <0x47>;
280				shunt-resistor = <5000>;
281			};
282			u65: ina226@48 { /* u65 */
283				compatible = "ti,ina226";
284				#io-channel-cells = <1>;
285				label = "ina226-u65";
286				reg = <0x48>;
287				shunt-resistor = <5000>;
288			};
289			u63: ina226@49 { /* u63 */
290				compatible = "ti,ina226";
291				#io-channel-cells = <1>;
292				label = "ina226-u63";
293				reg = <0x49>;
294				shunt-resistor = <5000>;
295			};
296			u3: ina226@4a { /* u3 */
297				compatible = "ti,ina226";
298				#io-channel-cells = <1>;
299				label = "ina226-u3";
300				reg = <0x4a>;
301				shunt-resistor = <5000>;
302			};
303			u71: ina226@4b { /* u71 */
304				compatible = "ti,ina226";
305				#io-channel-cells = <1>;
306				label = "ina226-u71";
307				reg = <0x4b>;
308				shunt-resistor = <5000>;
309			};
310			u77: ina226@4c { /* u77 */
311				compatible = "ti,ina226";
312				#io-channel-cells = <1>;
313				label = "ina226-u77";
314				reg = <0x4c>;
315				shunt-resistor = <5000>;
316			};
317			u73: ina226@4d { /* u73 */
318				compatible = "ti,ina226";
319				#io-channel-cells = <1>;
320				label = "ina226-u73";
321				reg = <0x4d>;
322				shunt-resistor = <5000>;
323			};
324			u79: ina226@4e { /* u79 */
325				compatible = "ti,ina226";
326				#io-channel-cells = <1>;
327				label = "ina226-u79";
328				reg = <0x4e>;
329				shunt-resistor = <5000>;
330			};
331		};
332		i2c@1 {
333			#address-cells = <1>;
334			#size-cells = <0>;
335			reg = <1>;
336			/* NC */
337		};
338		i2c@2 {
339			#address-cells = <1>;
340			#size-cells = <0>;
341			reg = <2>;
342			irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
343				compatible = "infineon,irps5401";
344				reg = <0x43>;
345			};
346			irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
347				compatible = "infineon,irps5401";
348				reg = <0x44>;
349			};
350			irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
351				compatible = "infineon,irps5401";
352				reg = <0x45>;
353			};
354			/* u68 IR38064 +0 */
355			/* u70 IR38060 +1 */
356			/* u74 IR38060 +2 */
357			/* u75 IR38060 +6 */
358			/* J19 header too */
359
360		};
361		i2c@3 {
362			#address-cells = <1>;
363			#size-cells = <0>;
364			reg = <3>;
365			/* SYSMON */
366		};
367	};
368};
369
370&i2c1 {
371	status = "okay";
372	clock-frequency = <400000>;
373	pinctrl-names = "default", "gpio";
374	pinctrl-0 = <&pinctrl_i2c1_default>;
375	pinctrl-1 = <&pinctrl_i2c1_gpio>;
376	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
377	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
378
379	i2c-mux@74 { /* u26 */
380		compatible = "nxp,pca9548";
381		#address-cells = <1>;
382		#size-cells = <0>;
383		reg = <0x74>;
384		i2c@0 {
385			#address-cells = <1>;
386			#size-cells = <0>;
387			reg = <0>;
388			/*
389			 * IIC_EEPROM 1kB memory which uses 256B blocks
390			 * where every block has different address.
391			 *    0 - 256B address 0x54
392			 * 256B - 512B address 0x55
393			 * 512B - 768B address 0x56
394			 * 768B - 1024B address 0x57
395			 */
396			eeprom: eeprom@54 { /* u88 */
397				compatible = "atmel,24c08";
398				reg = <0x54>;
399			};
400		};
401		i2c@1 {
402			#address-cells = <1>;
403			#size-cells = <0>;
404			reg = <1>;
405			si5341: clock-generator@36 { /* SI5341 - u46 */
406				compatible = "silabs,si5341";
407				reg = <0x36>;
408				#clock-cells = <2>;
409				#address-cells = <1>;
410				#size-cells = <0>;
411				clocks = <&ref48>;
412				clock-names = "xtal";
413				clock-output-names = "si5341";
414
415				si5341_0: out@0 {
416					/* refclk0 for PS-GT, used for DP */
417					reg = <0>;
418					always-on;
419				};
420				si5341_2: out@2 {
421					/* refclk2 for PS-GT, used for USB3 */
422					reg = <2>;
423					always-on;
424				};
425				si5341_3: out@3 {
426					/* refclk3 for PS-GT, used for SATA */
427					reg = <3>;
428					always-on;
429				};
430				si5341_5: out@5 {
431					/* refclk5 PL CLK100 */
432					reg = <5>;
433					always-on;
434				};
435				si5341_6: out@6 {
436					/* refclk6 PL CLK125 */
437					reg = <6>;
438					always-on;
439				};
440				si5341_9: out@9 {
441					/* refclk9 used for PS_REF_CLK 33.3 MHz */
442					reg = <9>;
443					always-on;
444				};
445			};
446		};
447		i2c@2 {
448			#address-cells = <1>;
449			#size-cells = <0>;
450			reg = <2>;
451			si570_1: clock-generator@5d { /* USER SI570 - u47 */
452				#clock-cells = <0>;
453				compatible = "silabs,si570";
454				reg = <0x5d>;
455				temperature-stability = <50>;
456				factory-fout = <300000000>;
457				clock-frequency = <300000000>;
458				clock-output-names = "si570_user";
459			};
460		};
461		i2c@3 {
462			#address-cells = <1>;
463			#size-cells = <0>;
464			reg = <3>;
465			si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
466				#clock-cells = <0>;
467				compatible = "silabs,si570";
468				reg = <0x5d>;
469				temperature-stability = <50>;
470				factory-fout = <156250000>;
471				clock-frequency = <156250000>;
472				clock-output-names = "si570_mgt";
473			};
474		};
475		i2c@4 {
476			#address-cells = <1>;
477			#size-cells = <0>;
478			reg = <4>;
479			/* SI5382 - u48 */
480		};
481		i2c@5 {
482			#address-cells = <1>;
483			#size-cells = <0>;
484			reg = <5>;
485				sc18is603@2f { /* sc18is602 - u93 */
486					compatible = "nxp,sc18is603";
487					reg = <0x2f>;
488					/* 4 gpios for CS not handled by driver */
489					/*
490					 * USB2ANY cable or
491					 * LMK04208 - u90 or
492					 * LMX2594 - u102 or
493					 * LMX2594 - u103 or
494					 * LMX2594 - u104
495					 */
496				};
497		};
498		i2c@6 {
499			#address-cells = <1>;
500			#size-cells = <0>;
501			reg = <6>;
502			/* FMC connector */
503		};
504		/* 7 NC */
505	};
506
507	i2c-mux@75 {
508		compatible = "nxp,pca9548"; /* u27 */
509		#address-cells = <1>;
510		#size-cells = <0>;
511		reg = <0x75>;
512
513		i2c@0 {
514			#address-cells = <1>;
515			#size-cells = <0>;
516			reg = <0>;
517			/* FMCP_HSPC_IIC */
518		};
519		i2c@1 {
520			#address-cells = <1>;
521			#size-cells = <0>;
522			reg = <1>;
523			/* NC */
524		};
525		i2c@2 {
526			#address-cells = <1>;
527			#size-cells = <0>;
528			reg = <2>;
529			/* SYSMON */
530		};
531		i2c@3 {
532			#address-cells = <1>;
533			#size-cells = <0>;
534			reg = <3>;
535			/* DDR4 SODIMM */
536		};
537		i2c@4 {
538			#address-cells = <1>;
539			#size-cells = <0>;
540			reg = <4>;
541			/* SFP3 */
542		};
543		i2c@5 {
544			#address-cells = <1>;
545			#size-cells = <0>;
546			reg = <5>;
547			/* SFP2 */
548		};
549		i2c@6 {
550			#address-cells = <1>;
551			#size-cells = <0>;
552			reg = <6>;
553			/* SFP1 */
554		};
555		i2c@7 {
556			#address-cells = <1>;
557			#size-cells = <0>;
558			reg = <7>;
559			/* SFP0 */
560		};
561	};
562};
563
564&pinctrl0 {
565	status = "okay";
566	pinctrl_i2c0_default: i2c0-default {
567		mux {
568			groups = "i2c0_3_grp";
569			function = "i2c0";
570		};
571
572		conf {
573			groups = "i2c0_3_grp";
574			bias-pull-up;
575			slew-rate = <SLEW_RATE_SLOW>;
576			power-source = <IO_STANDARD_LVCMOS18>;
577		};
578	};
579
580	pinctrl_i2c0_gpio: i2c0-gpio {
581		mux {
582			groups = "gpio0_14_grp", "gpio0_15_grp";
583			function = "gpio0";
584		};
585
586		conf {
587			groups = "gpio0_14_grp", "gpio0_15_grp";
588			slew-rate = <SLEW_RATE_SLOW>;
589			power-source = <IO_STANDARD_LVCMOS18>;
590		};
591	};
592
593	pinctrl_i2c1_default: i2c1-default {
594		mux {
595			groups = "i2c1_4_grp";
596			function = "i2c1";
597		};
598
599		conf {
600			groups = "i2c1_4_grp";
601			bias-pull-up;
602			slew-rate = <SLEW_RATE_SLOW>;
603			power-source = <IO_STANDARD_LVCMOS18>;
604		};
605	};
606
607	pinctrl_i2c1_gpio: i2c1-gpio {
608		mux {
609			groups = "gpio0_16_grp", "gpio0_17_grp";
610			function = "gpio0";
611		};
612
613		conf {
614			groups = "gpio0_16_grp", "gpio0_17_grp";
615			slew-rate = <SLEW_RATE_SLOW>;
616			power-source = <IO_STANDARD_LVCMOS18>;
617		};
618	};
619
620	pinctrl_uart0_default: uart0-default {
621		mux {
622			groups = "uart0_4_grp";
623			function = "uart0";
624		};
625
626		conf {
627			groups = "uart0_4_grp";
628			slew-rate = <SLEW_RATE_SLOW>;
629			power-source = <IO_STANDARD_LVCMOS18>;
630		};
631
632		conf-rx {
633			pins = "MIO18";
634			bias-high-impedance;
635		};
636
637		conf-tx {
638			pins = "MIO19";
639			bias-disable;
640		};
641	};
642
643	pinctrl_usb0_default: usb0-default {
644		mux {
645			groups = "usb0_0_grp";
646			function = "usb0";
647		};
648
649		conf {
650			groups = "usb0_0_grp";
651			slew-rate = <SLEW_RATE_SLOW>;
652			power-source = <IO_STANDARD_LVCMOS18>;
653		};
654
655		conf-rx {
656			pins = "MIO52", "MIO53", "MIO55";
657			bias-high-impedance;
658		};
659
660		conf-tx {
661			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
662			       "MIO60", "MIO61", "MIO62", "MIO63";
663			bias-disable;
664		};
665	};
666
667	pinctrl_gem3_default: gem3-default {
668		mux {
669			function = "ethernet3";
670			groups = "ethernet3_0_grp";
671		};
672
673		conf {
674			groups = "ethernet3_0_grp";
675			slew-rate = <SLEW_RATE_SLOW>;
676			power-source = <IO_STANDARD_LVCMOS18>;
677		};
678
679		conf-rx {
680			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
681									"MIO75";
682			bias-high-impedance;
683			low-power-disable;
684		};
685
686		conf-tx {
687			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
688									"MIO69";
689			bias-disable;
690			low-power-enable;
691		};
692
693		mux-mdio {
694			function = "mdio3";
695			groups = "mdio3_0_grp";
696		};
697
698		conf-mdio {
699			groups = "mdio3_0_grp";
700			slew-rate = <SLEW_RATE_SLOW>;
701			power-source = <IO_STANDARD_LVCMOS18>;
702			bias-disable;
703		};
704	};
705
706	pinctrl_sdhci1_default: sdhci1-default {
707		mux {
708			groups = "sdio1_0_grp";
709			function = "sdio1";
710		};
711
712		conf {
713			groups = "sdio1_0_grp";
714			slew-rate = <SLEW_RATE_SLOW>;
715			power-source = <IO_STANDARD_LVCMOS18>;
716			bias-disable;
717		};
718
719		mux-cd {
720			groups = "sdio1_cd_0_grp";
721			function = "sdio1_cd";
722		};
723
724		conf-cd {
725			groups = "sdio1_cd_0_grp";
726			bias-high-impedance;
727			bias-pull-up;
728			slew-rate = <SLEW_RATE_SLOW>;
729			power-source = <IO_STANDARD_LVCMOS18>;
730		};
731	};
732
733	pinctrl_gpio_default: gpio-default {
734		mux {
735			function = "gpio0";
736			groups = "gpio0_22_grp", "gpio0_23_grp";
737		};
738
739		conf {
740			groups = "gpio0_22_grp", "gpio0_23_grp";
741			slew-rate = <SLEW_RATE_SLOW>;
742			power-source = <IO_STANDARD_LVCMOS18>;
743		};
744
745		mux-msp {
746			function = "gpio0";
747			groups = "gpio0_13_grp", "gpio0_38_grp";
748		};
749
750		conf-msp {
751			groups = "gpio0_13_grp", "gpio0_38_grp";
752			slew-rate = <SLEW_RATE_SLOW>;
753			power-source = <IO_STANDARD_LVCMOS18>;
754		};
755
756		conf-pull-up {
757			pins = "MIO22";
758			bias-pull-up;
759		};
760
761		conf-pull-none {
762			pins = "MIO13", "MIO23", "MIO38";
763			bias-disable;
764		};
765	};
766};
767
768&psgtr {
769	status = "okay";
770	/* nc, dp, usb3, sata */
771	clocks = <&si5341 0 0>, <&si5341 0 2>, <&si5341 0 3>;
772	clock-names = "ref1", "ref2", "ref3";
773};
774
775&qspi {
776	status = "okay";
777	flash@0 {
778		compatible = "m25p80", "jedec,spi-nor"; /* 16MB + 16MB */
779		#address-cells = <1>;
780		#size-cells = <1>;
781		reg = <0x0>;
782		spi-tx-bus-width = <1>;
783		spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
784		spi-max-frequency = <108000000>; /* Based on DC1 spec */
785	};
786};
787
788&rtc {
789	status = "okay";
790};
791
792&sata {
793	status = "okay";
794	/* SATA OOB timing settings */
795	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
796	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
797	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
798	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
799	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
800	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
801	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
802	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
803	phy-names = "sata-phy";
804	phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
805};
806
807/* SD1 with level shifter */
808&sdhci1 {
809	status = "okay";
810	pinctrl-names = "default";
811	pinctrl-0 = <&pinctrl_sdhci1_default>;
812	disable-wp;
813	/*
814	 * This property should be removed for supporting UHS mode
815	 */
816	no-1-8-v;
817	xlnx,mio-bank = <1>;
818};
819
820&uart0 {
821	status = "okay";
822	pinctrl-names = "default";
823	pinctrl-0 = <&pinctrl_uart0_default>;
824};
825
826/* ULPI SMSC USB3320 */
827&usb0 {
828	status = "okay";
829	pinctrl-names = "default";
830	pinctrl-0 = <&pinctrl_usb0_default>;
831	phy-names = "usb3-phy";
832	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
833};
834
835&dwc3_0 {
836	status = "okay";
837	dr_mode = "host";
838	snps,usb3_lpm_capable;
839	maximum-speed = "super-speed";
840};
841
842&zynqmp_dpdma {
843	status = "okay";
844};
845
846&zynqmp_dpsub {
847	status = "okay";
848	phy-names = "dp-phy0", "dp-phy1";
849	phys = <&psgtr 1 PHY_TYPE_DP 0 1>,
850	       <&psgtr 0 PHY_TYPE_DP 1 1>;
851};
852