1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP ZCU104
4 *
5 * (C) Copyright 2017 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16#include <dt-bindings/phy/phy.h>
17
18/ {
19	model = "ZynqMP ZCU104 RevA";
20	compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
21
22	aliases {
23		ethernet0 = &gem3;
24		i2c0 = &i2c1;
25		mmc0 = &sdhci1;
26		nvmem0 = &eeprom;
27		rtc0 = &rtc;
28		serial0 = &uart0;
29		serial1 = &uart1;
30		serial2 = &dcc;
31		spi0 = &qspi;
32		usb0 = &usb0;
33	};
34
35	chosen {
36		bootargs = "earlycon";
37		stdout-path = "serial0:115200n8";
38	};
39
40	memory@0 {
41		device_type = "memory";
42		reg = <0x0 0x0 0x0 0x80000000>;
43	};
44
45	clock_8t49n287_5: clk125 {
46		compatible = "fixed-clock";
47		#clock-cells = <0>;
48		clock-frequency = <125000000>;
49	};
50
51	clock_8t49n287_2: clk26 {
52		compatible = "fixed-clock";
53		#clock-cells = <0>;
54		clock-frequency = <26000000>;
55	};
56
57	clock_8t49n287_3: clk27 {
58		compatible = "fixed-clock";
59		#clock-cells = <0>;
60		clock-frequency = <27000000>;
61	};
62};
63
64&can1 {
65	status = "okay";
66	pinctrl-names = "default";
67	pinctrl-0 = <&pinctrl_can1_default>;
68};
69
70&dcc {
71	status = "okay";
72};
73
74&fpd_dma_chan1 {
75	status = "okay";
76};
77
78&fpd_dma_chan2 {
79	status = "okay";
80};
81
82&fpd_dma_chan3 {
83	status = "okay";
84};
85
86&fpd_dma_chan4 {
87	status = "okay";
88};
89
90&fpd_dma_chan5 {
91	status = "okay";
92};
93
94&fpd_dma_chan6 {
95	status = "okay";
96};
97
98&fpd_dma_chan7 {
99	status = "okay";
100};
101
102&fpd_dma_chan8 {
103	status = "okay";
104};
105
106&gem3 {
107	status = "okay";
108	phy-handle = <&phy0>;
109	phy-mode = "rgmii-id";
110	pinctrl-names = "default";
111	pinctrl-0 = <&pinctrl_gem3_default>;
112	phy0: ethernet-phy@c {
113		reg = <0xc>;
114		ti,rx-internal-delay = <0x8>;
115		ti,tx-internal-delay = <0xa>;
116		ti,fifo-depth = <0x1>;
117		ti,dp83867-rxctrl-strap-quirk;
118	};
119};
120
121&gpio {
122	status = "okay";
123};
124
125&i2c1 {
126	status = "okay";
127	clock-frequency = <400000>;
128	pinctrl-names = "default", "gpio";
129	pinctrl-0 = <&pinctrl_i2c1_default>;
130	pinctrl-1 = <&pinctrl_i2c1_gpio>;
131	scl-gpios = <&gpio 16 GPIO_ACTIVE_HIGH>;
132	sda-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>;
133
134	/* Another connection to this bus via PL i2c via PCA9306 - u45 */
135	i2c-mux@74 { /* u34 */
136		compatible = "nxp,pca9548";
137		#address-cells = <1>;
138		#size-cells = <0>;
139		reg = <0x74>;
140		i2c@0 {
141			#address-cells = <1>;
142			#size-cells = <0>;
143			reg = <0>;
144			/*
145			 * IIC_EEPROM 1kB memory which uses 256B blocks
146			 * where every block has different address.
147			 *    0 - 256B address 0x54
148			 * 256B - 512B address 0x55
149			 * 512B - 768B address 0x56
150			 * 768B - 1024B address 0x57
151			 */
152			eeprom: eeprom@54 { /* u23 */
153				compatible = "atmel,24c08";
154				reg = <0x54>;
155				#address-cells = <1>;
156				#size-cells = <1>;
157			};
158		};
159
160		i2c@1 {
161			#address-cells = <1>;
162			#size-cells = <0>;
163			reg = <1>;
164			/* 8T49N287 - u182 */
165		};
166
167		i2c@2 {
168			#address-cells = <1>;
169			#size-cells = <0>;
170			reg = <2>;
171			irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
172				compatible = "infineon,irps5401";
173				reg = <0x43>; /* pmbus / i2c 0x13 */
174			};
175			irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
176				compatible = "infineon,irps5401";
177				reg = <0x44>; /* pmbus / i2c 0x14 */
178			};
179		};
180
181		i2c@4 {
182			#address-cells = <1>;
183			#size-cells = <0>;
184			reg = <4>;
185			tca6416_u97: gpio@20 {
186				compatible = "ti,tca6416";
187				reg = <0x20>;
188				gpio-controller;
189				#gpio-cells = <2>;
190				/*
191				 * IRQ not connected
192				 * Lines:
193				 * 0 - IRPS5401_ALERT_B
194				 * 1 - HDMI_8T49N241_INT_ALM
195				 * 2 - MAX6643_OT_B
196				 * 3 - MAX6643_FANFAIL_B
197				 * 5 - IIC_MUX_RESET_B
198				 * 6 - GEM3_EXP_RESET_B
199				 * 7 - FMC_LPC_PRSNT_M2C_B
200				 * 4, 10 - 17 - not connected
201				 */
202			};
203		};
204
205		i2c@5 {
206			#address-cells = <1>;
207			#size-cells = <0>;
208			reg = <5>;
209		};
210
211		i2c@7 {
212			#address-cells = <1>;
213			#size-cells = <0>;
214			reg = <7>;
215		};
216
217		/* 3, 6 not connected */
218	};
219};
220
221&pinctrl0 {
222	status = "okay";
223
224	pinctrl_can1_default: can1-default {
225		mux {
226			function = "can1";
227			groups = "can1_6_grp";
228		};
229
230		conf {
231			groups = "can1_6_grp";
232			slew-rate = <SLEW_RATE_SLOW>;
233			power-source = <IO_STANDARD_LVCMOS18>;
234			drive-strength = <12>;
235		};
236
237		conf-rx {
238			pins = "MIO25";
239			bias-high-impedance;
240		};
241
242		conf-tx {
243			pins = "MIO24";
244			bias-disable;
245		};
246	};
247
248	pinctrl_i2c1_default: i2c1-default {
249		mux {
250			groups = "i2c1_4_grp";
251			function = "i2c1";
252		};
253
254		conf {
255			groups = "i2c1_4_grp";
256			bias-pull-up;
257			slew-rate = <SLEW_RATE_SLOW>;
258			power-source = <IO_STANDARD_LVCMOS18>;
259			drive-strength = <12>;
260		};
261	};
262
263	pinctrl_i2c1_gpio: i2c1-gpio {
264		mux {
265			groups = "gpio0_16_grp", "gpio0_17_grp";
266			function = "gpio0";
267		};
268
269		conf {
270			groups = "gpio0_16_grp", "gpio0_17_grp";
271			slew-rate = <SLEW_RATE_SLOW>;
272			power-source = <IO_STANDARD_LVCMOS18>;
273			drive-strength = <12>;
274		};
275	};
276
277	pinctrl_gem3_default: gem3-default {
278		mux {
279			function = "ethernet3";
280			groups = "ethernet3_0_grp";
281		};
282
283		conf {
284			groups = "ethernet3_0_grp";
285			slew-rate = <SLEW_RATE_SLOW>;
286			power-source = <IO_STANDARD_LVCMOS18>;
287			drive-strength = <12>;
288		};
289
290		conf-rx {
291			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
292									"MIO75";
293			bias-high-impedance;
294			low-power-disable;
295		};
296
297		conf-tx {
298			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
299									"MIO69";
300			bias-disable;
301			low-power-enable;
302		};
303
304		mux-mdio {
305			function = "mdio3";
306			groups = "mdio3_0_grp";
307		};
308
309		conf-mdio {
310			groups = "mdio3_0_grp";
311			slew-rate = <SLEW_RATE_SLOW>;
312			power-source = <IO_STANDARD_LVCMOS18>;
313			bias-disable;
314		};
315	};
316
317	pinctrl_sdhci1_default: sdhci1-default {
318		mux {
319			groups = "sdio1_0_grp";
320			function = "sdio1";
321		};
322
323		conf {
324			groups = "sdio1_0_grp";
325			slew-rate = <SLEW_RATE_SLOW>;
326			power-source = <IO_STANDARD_LVCMOS18>;
327			bias-disable;
328			drive-strength = <12>;
329		};
330
331		mux-cd {
332			groups = "sdio1_cd_0_grp";
333			function = "sdio1_cd";
334		};
335
336		conf-cd {
337			groups = "sdio1_cd_0_grp";
338			bias-high-impedance;
339			bias-pull-up;
340			slew-rate = <SLEW_RATE_SLOW>;
341			power-source = <IO_STANDARD_LVCMOS18>;
342		};
343	};
344
345	pinctrl_uart0_default: uart0-default {
346		mux {
347			groups = "uart0_4_grp";
348			function = "uart0";
349		};
350
351		conf {
352			groups = "uart0_4_grp";
353			slew-rate = <SLEW_RATE_SLOW>;
354			power-source = <IO_STANDARD_LVCMOS18>;
355			drive-strength = <12>;
356		};
357
358		conf-rx {
359			pins = "MIO18";
360			bias-high-impedance;
361		};
362
363		conf-tx {
364			pins = "MIO19";
365			bias-disable;
366		};
367	};
368
369	pinctrl_uart1_default: uart1-default {
370		mux {
371			groups = "uart1_5_grp";
372			function = "uart1";
373		};
374
375		conf {
376			groups = "uart1_5_grp";
377			slew-rate = <SLEW_RATE_SLOW>;
378			power-source = <IO_STANDARD_LVCMOS18>;
379			drive-strength = <12>;
380		};
381
382		conf-rx {
383			pins = "MIO21";
384			bias-high-impedance;
385		};
386
387		conf-tx {
388			pins = "MIO20";
389			bias-disable;
390		};
391	};
392
393	pinctrl_usb0_default: usb0-default {
394		mux {
395			groups = "usb0_0_grp";
396			function = "usb0";
397		};
398
399		conf {
400			groups = "usb0_0_grp";
401			slew-rate = <SLEW_RATE_SLOW>;
402			power-source = <IO_STANDARD_LVCMOS18>;
403			drive-strength = <12>;
404		};
405
406		conf-rx {
407			pins = "MIO52", "MIO53", "MIO55";
408			bias-high-impedance;
409		};
410
411		conf-tx {
412			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
413			       "MIO60", "MIO61", "MIO62", "MIO63";
414			bias-disable;
415		};
416	};
417};
418
419&psgtr {
420	status = "okay";
421	/* nc, sata, usb3, dp */
422	clocks = <&clock_8t49n287_5>, <&clock_8t49n287_2>, <&clock_8t49n287_3>;
423	clock-names = "ref1", "ref2", "ref3";
424};
425
426&qspi {
427	status = "okay";
428	flash@0 {
429		compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
430		#address-cells = <1>;
431		#size-cells = <1>;
432		reg = <0x0>;
433		spi-tx-bus-width = <1>;
434		spi-rx-bus-width = <4>;
435		spi-max-frequency = <108000000>; /* Based on DC1 spec */
436	};
437};
438
439&rtc {
440	status = "okay";
441};
442
443&sata {
444	status = "okay";
445	/* SATA OOB timing settings */
446	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
447	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
448	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
449	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
450	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
451	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
452	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
453	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
454	phy-names = "sata-phy";
455	phys = <&psgtr 3 PHY_TYPE_SATA 1 1>;
456};
457
458/* SD1 with level shifter */
459&sdhci1 {
460	status = "okay";
461	no-1-8-v;
462	pinctrl-names = "default";
463	pinctrl-0 = <&pinctrl_sdhci1_default>;
464	xlnx,mio-bank = <1>;
465	disable-wp;
466};
467
468&uart0 {
469	status = "okay";
470	pinctrl-names = "default";
471	pinctrl-0 = <&pinctrl_uart0_default>;
472};
473
474&uart1 {
475	status = "okay";
476	pinctrl-names = "default";
477	pinctrl-0 = <&pinctrl_uart1_default>;
478};
479
480/* ULPI SMSC USB3320 */
481&usb0 {
482	status = "okay";
483	pinctrl-names = "default";
484	pinctrl-0 = <&pinctrl_usb0_default>;
485	phy-names = "usb3-phy";
486	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
487};
488
489&dwc3_0 {
490	status = "okay";
491	dr_mode = "host";
492	snps,usb3_lpm_capable;
493	maximum-speed = "super-speed";
494};
495
496&watchdog0 {
497	status = "okay";
498};
499
500&zynqmp_dpdma {
501	status = "okay";
502};
503
504&zynqmp_dpsub {
505	status = "okay";
506	phy-names = "dp-phy0", "dp-phy1";
507	phys = <&psgtr 1 PHY_TYPE_DP 0 3>,
508	       <&psgtr 0 PHY_TYPE_DP 1 3>;
509};
510