1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
4 *
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
6 *
7 * Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
8 * Michal Simek <michal.simek@xilinx.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk.dtsi"
15#include <dt-bindings/gpio/gpio.h>
16
17/ {
18	model = "ZynqMP zc1751-xm019-dc5 RevA";
19	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
20
21	aliases {
22		ethernet0 = &gem1;
23		i2c0 = &i2c0;
24		i2c1 = &i2c1;
25		mmc0 = &sdhci0;
26		serial0 = &uart0;
27		serial1 = &uart1;
28	};
29
30	chosen {
31		bootargs = "earlycon";
32		stdout-path = "serial0:115200n8";
33	};
34
35	memory@0 {
36		device_type = "memory";
37		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
38	};
39};
40
41&fpd_dma_chan1 {
42	status = "okay";
43};
44
45&fpd_dma_chan2 {
46	status = "okay";
47};
48
49&fpd_dma_chan3 {
50	status = "okay";
51};
52
53&fpd_dma_chan4 {
54	status = "okay";
55};
56
57&fpd_dma_chan5 {
58	status = "okay";
59};
60
61&fpd_dma_chan6 {
62	status = "okay";
63};
64
65&fpd_dma_chan7 {
66	status = "okay";
67};
68
69&fpd_dma_chan8 {
70	status = "okay";
71};
72
73&gem1 {
74	status = "okay";
75	phy-handle = <&phy0>;
76	phy-mode = "rgmii-id";
77	phy0: phy@0 {
78		reg = <0>;
79	};
80};
81
82&gpio {
83	status = "okay";
84};
85
86&i2c0 {
87	status = "okay";
88};
89
90&i2c1 {
91	status = "okay";
92};
93
94&sdhci0 {
95	status = "okay";
96	no-1-8-v;
97};
98
99&ttc0 {
100	status = "okay";
101};
102
103&ttc1 {
104	status = "okay";
105};
106
107&ttc2 {
108	status = "okay";
109};
110
111&ttc3 {
112	status = "okay";
113};
114
115&uart0 {
116	status = "okay";
117};
118
119&uart1 {
120	status = "okay";
121};
122
123&watchdog0 {
124	status = "okay";
125};
126