1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
4 *
5 * (C) Copyright 2015 - 2018, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk.dtsi"
14
15/ {
16	model = "ZynqMP zc1751-xm018-dc4";
17	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
18
19	aliases {
20		ethernet0 = &gem0;
21		ethernet1 = &gem1;
22		ethernet2 = &gem2;
23		ethernet3 = &gem3;
24		i2c0 = &i2c0;
25		i2c1 = &i2c1;
26		rtc0 = &rtc;
27		serial0 = &uart0;
28		serial1 = &uart1;
29	};
30
31	chosen {
32		bootargs = "earlycon";
33		stdout-path = "serial0:115200n8";
34	};
35
36	memory@0 {
37		device_type = "memory";
38		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
39	};
40};
41
42&can0 {
43	status = "okay";
44};
45
46&can1 {
47	status = "okay";
48};
49
50&fpd_dma_chan1 {
51	status = "okay";
52};
53
54&fpd_dma_chan2 {
55	status = "okay";
56};
57
58&fpd_dma_chan3 {
59	status = "okay";
60};
61
62&fpd_dma_chan4 {
63	status = "okay";
64};
65
66&fpd_dma_chan5 {
67	status = "okay";
68};
69
70&fpd_dma_chan6 {
71	status = "okay";
72};
73
74&fpd_dma_chan7 {
75	status = "okay";
76};
77
78&fpd_dma_chan8 {
79	status = "okay";
80};
81
82&lpd_dma_chan1 {
83	status = "okay";
84};
85
86&lpd_dma_chan2 {
87	status = "okay";
88};
89
90&lpd_dma_chan3 {
91	status = "okay";
92};
93
94&lpd_dma_chan4 {
95	status = "okay";
96};
97
98&lpd_dma_chan5 {
99	status = "okay";
100};
101
102&lpd_dma_chan6 {
103	status = "okay";
104};
105
106&lpd_dma_chan7 {
107	status = "okay";
108};
109
110&lpd_dma_chan8 {
111	status = "okay";
112};
113
114&gem0 {
115	status = "okay";
116	phy-mode = "rgmii-id";
117	phy-handle = <&ethernet_phy0>;
118	ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
119		reg = <0>;
120	};
121	ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
122		reg = <7>;
123	};
124	ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
125		reg = <3>;
126	};
127	ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
128		reg = <8>;
129	};
130};
131
132&gem1 {
133	status = "okay";
134	phy-mode = "rgmii-id";
135	phy-handle = <&ethernet_phy7>;
136};
137
138&gem2 {
139	status = "okay";
140	phy-mode = "rgmii-id";
141	phy-handle = <&ethernet_phy3>;
142};
143
144&gem3 {
145	status = "okay";
146	phy-mode = "rgmii-id";
147	phy-handle = <&ethernet_phy8>;
148};
149
150&gpio {
151	status = "okay";
152};
153
154&i2c0 {
155	clock-frequency = <400000>;
156	status = "okay";
157};
158
159&i2c1 {
160	clock-frequency = <400000>;
161	status = "okay";
162};
163
164&rtc {
165	status = "okay";
166};
167
168&uart0 {
169	status = "okay";
170};
171
172&uart1 {
173	status = "okay";
174};
175
176&watchdog0 {
177	status = "okay";
178};
179