1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm016-dc2
4 *
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10/dts-v1/;
11
12#include "zynqmp.dtsi"
13#include "zynqmp-clk-ccf.dtsi"
14#include <dt-bindings/gpio/gpio.h>
15#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16
17/ {
18	model = "ZynqMP zc1751-xm016-dc2 RevA";
19	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
20
21	aliases {
22		ethernet0 = &gem2;
23		i2c0 = &i2c0;
24		rtc0 = &rtc;
25		serial0 = &uart0;
26		serial1 = &uart1;
27		spi0 = &spi0;
28		spi1 = &spi1;
29		usb0 = &usb1;
30	};
31
32	chosen {
33		bootargs = "earlycon";
34		stdout-path = "serial0:115200n8";
35	};
36
37	memory@0 {
38		device_type = "memory";
39		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
40	};
41};
42
43&can0 {
44	status = "okay";
45	pinctrl-names = "default";
46	pinctrl-0 = <&pinctrl_can0_default>;
47};
48
49&can1 {
50	status = "okay";
51	pinctrl-names = "default";
52	pinctrl-0 = <&pinctrl_can1_default>;
53};
54
55&fpd_dma_chan1 {
56	status = "okay";
57};
58
59&fpd_dma_chan2 {
60	status = "okay";
61};
62
63&fpd_dma_chan3 {
64	status = "okay";
65};
66
67&fpd_dma_chan4 {
68	status = "okay";
69};
70
71&fpd_dma_chan5 {
72	status = "okay";
73};
74
75&fpd_dma_chan6 {
76	status = "okay";
77};
78
79&fpd_dma_chan7 {
80	status = "okay";
81};
82
83&fpd_dma_chan8 {
84	status = "okay";
85};
86
87&gem2 {
88	status = "okay";
89	phy-handle = <&phy0>;
90	phy-mode = "rgmii-id";
91	pinctrl-names = "default";
92	pinctrl-0 = <&pinctrl_gem2_default>;
93	phy0: ethernet-phy@5 {
94		reg = <5>;
95		ti,rx-internal-delay = <0x8>;
96		ti,tx-internal-delay = <0xa>;
97		ti,fifo-depth = <0x1>;
98		ti,dp83867-rxctrl-strap-quirk;
99	};
100};
101
102&gpio {
103	status = "okay";
104};
105
106&i2c0 {
107	status = "okay";
108	clock-frequency = <400000>;
109	pinctrl-names = "default", "gpio";
110	pinctrl-0 = <&pinctrl_i2c0_default>;
111	pinctrl-1 = <&pinctrl_i2c0_gpio>;
112	scl-gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
113	sda-gpios = <&gpio 7 GPIO_ACTIVE_HIGH>;
114
115	tca6416_u26: gpio@20 {
116		compatible = "ti,tca6416";
117		reg = <0x20>;
118		gpio-controller;
119		#gpio-cells = <2>;
120		/* IRQ not connected */
121	};
122
123	rtc@68 {
124		compatible = "dallas,ds1339";
125		reg = <0x68>;
126	};
127};
128
129&nand0 {
130	status = "okay";
131	pinctrl-names = "default";
132	pinctrl-0 = <&pinctrl_nand0_default>;
133	arasan,has-mdma;
134
135	nand@0 {
136		reg = <0x0>;
137		#address-cells = <0x2>;
138		#size-cells = <0x1>;
139		nand-ecc-mode = "soft";
140		nand-ecc-algo = "bch";
141		nand-rb = <0>;
142		label = "main-storage-0";
143	};
144	nand@1 {
145		reg = <0x1>;
146		#address-cells = <0x2>;
147		#size-cells = <0x1>;
148		nand-ecc-mode = "soft";
149		nand-ecc-algo = "bch";
150		nand-rb = <0>;
151		label = "main-storage-1";
152	};
153};
154
155&pinctrl0 {
156	status = "okay";
157	pinctrl_can0_default: can0-default {
158		mux {
159			function = "can0";
160			groups = "can0_9_grp";
161		};
162
163		conf {
164			groups = "can0_9_grp";
165			slew-rate = <SLEW_RATE_SLOW>;
166			power-source = <IO_STANDARD_LVCMOS18>;
167		};
168
169		conf-rx {
170			pins = "MIO38";
171			bias-high-impedance;
172		};
173
174		conf-tx {
175			pins = "MIO39";
176			bias-disable;
177		};
178	};
179
180	pinctrl_can1_default: can1-default {
181		mux {
182			function = "can1";
183			groups = "can1_8_grp";
184		};
185
186		conf {
187			groups = "can1_8_grp";
188			slew-rate = <SLEW_RATE_SLOW>;
189			power-source = <IO_STANDARD_LVCMOS18>;
190		};
191
192		conf-rx {
193			pins = "MIO33";
194			bias-high-impedance;
195		};
196
197		conf-tx {
198			pins = "MIO32";
199			bias-disable;
200		};
201	};
202
203	pinctrl_i2c0_default: i2c0-default {
204		mux {
205			groups = "i2c0_1_grp";
206			function = "i2c0";
207		};
208
209		conf {
210			groups = "i2c0_1_grp";
211			bias-pull-up;
212			slew-rate = <SLEW_RATE_SLOW>;
213			power-source = <IO_STANDARD_LVCMOS18>;
214		};
215	};
216
217	pinctrl_i2c0_gpio: i2c0-gpio {
218		mux {
219			groups = "gpio0_6_grp", "gpio0_7_grp";
220			function = "gpio0";
221		};
222
223		conf {
224			groups = "gpio0_6_grp", "gpio0_7_grp";
225			slew-rate = <SLEW_RATE_SLOW>;
226			power-source = <IO_STANDARD_LVCMOS18>;
227		};
228	};
229
230	pinctrl_uart0_default: uart0-default {
231		mux {
232			groups = "uart0_10_grp";
233			function = "uart0";
234		};
235
236		conf {
237			groups = "uart0_10_grp";
238			slew-rate = <SLEW_RATE_SLOW>;
239			power-source = <IO_STANDARD_LVCMOS18>;
240		};
241
242		conf-rx {
243			pins = "MIO42";
244			bias-high-impedance;
245		};
246
247		conf-tx {
248			pins = "MIO43";
249			bias-disable;
250		};
251	};
252
253	pinctrl_uart1_default: uart1-default {
254		mux {
255			groups = "uart1_10_grp";
256			function = "uart1";
257		};
258
259		conf {
260			groups = "uart1_10_grp";
261			slew-rate = <SLEW_RATE_SLOW>;
262			power-source = <IO_STANDARD_LVCMOS18>;
263		};
264
265		conf-rx {
266			pins = "MIO41";
267			bias-high-impedance;
268		};
269
270		conf-tx {
271			pins = "MIO40";
272			bias-disable;
273		};
274	};
275
276	pinctrl_usb1_default: usb1-default {
277		mux {
278			groups = "usb1_0_grp";
279			function = "usb1";
280		};
281
282		conf {
283			groups = "usb1_0_grp";
284			slew-rate = <SLEW_RATE_SLOW>;
285			power-source = <IO_STANDARD_LVCMOS18>;
286		};
287
288		conf-rx {
289			pins = "MIO64", "MIO65", "MIO67";
290			bias-high-impedance;
291		};
292
293		conf-tx {
294			pins = "MIO66", "MIO68", "MIO69", "MIO70", "MIO71",
295			       "MIO72", "MIO73", "MIO74", "MIO75";
296			bias-disable;
297		};
298	};
299
300	pinctrl_gem2_default: gem2-default {
301		mux {
302			function = "ethernet2";
303			groups = "ethernet2_0_grp";
304		};
305
306		conf {
307			groups = "ethernet2_0_grp";
308			slew-rate = <SLEW_RATE_SLOW>;
309			power-source = <IO_STANDARD_LVCMOS18>;
310		};
311
312		conf-rx {
313			pins = "MIO58", "MIO59", "MIO60", "MIO61", "MIO62",
314									"MIO63";
315			bias-high-impedance;
316			low-power-disable;
317		};
318
319		conf-tx {
320			pins = "MIO52", "MIO53", "MIO54", "MIO55", "MIO56",
321									"MIO57";
322			bias-disable;
323			low-power-enable;
324		};
325
326		mux-mdio {
327			function = "mdio2";
328			groups = "mdio2_0_grp";
329		};
330
331		conf-mdio {
332			groups = "mdio2_0_grp";
333			slew-rate = <SLEW_RATE_SLOW>;
334			power-source = <IO_STANDARD_LVCMOS18>;
335			bias-disable;
336		};
337	};
338
339	pinctrl_nand0_default: nand0-default {
340		mux {
341			groups = "nand0_0_grp";
342			function = "nand0";
343		};
344
345		conf {
346			groups = "nand0_0_grp";
347			bias-pull-up;
348		};
349
350		mux-ce {
351			groups = "nand0_ce_0_grp";
352			function = "nand0_ce";
353		};
354
355		conf-ce {
356			groups = "nand0_ce_0_grp";
357			bias-pull-up;
358		};
359
360		mux-rb {
361			groups = "nand0_rb_0_grp";
362			function = "nand0_rb";
363		};
364
365		conf-rb {
366			groups = "nand0_rb_0_grp";
367			bias-pull-up;
368		};
369
370		mux-dqs {
371			groups = "nand0_dqs_0_grp";
372			function = "nand0_dqs";
373		};
374
375		conf-dqs {
376			groups = "nand0_dqs_0_grp";
377			bias-pull-up;
378		};
379	};
380
381	pinctrl_spi0_default: spi0-default {
382		mux {
383			groups = "spi0_0_grp";
384			function = "spi0";
385		};
386
387		conf {
388			groups = "spi0_0_grp";
389			bias-disable;
390			slew-rate = <SLEW_RATE_SLOW>;
391			power-source = <IO_STANDARD_LVCMOS18>;
392		};
393
394		mux-cs {
395			groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
396							"spi0_ss_2_grp";
397			function = "spi0_ss";
398		};
399
400		conf-cs {
401			groups = "spi0_ss_0_grp", "spi0_ss_1_grp",
402							"spi0_ss_2_grp";
403			bias-disable;
404		};
405	};
406
407	pinctrl_spi1_default: spi1-default {
408		mux {
409			groups = "spi1_3_grp";
410			function = "spi1";
411		};
412
413		conf {
414			groups = "spi1_3_grp";
415			bias-disable;
416			slew-rate = <SLEW_RATE_SLOW>;
417			power-source = <IO_STANDARD_LVCMOS18>;
418		};
419
420		mux-cs {
421			groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
422							"spi1_ss_11_grp";
423			function = "spi1_ss";
424		};
425
426		conf-cs {
427			groups = "spi1_ss_9_grp", "spi1_ss_10_grp",
428							"spi1_ss_11_grp";
429			bias-disable;
430		};
431	};
432};
433
434&rtc {
435	status = "okay";
436};
437
438&spi0 {
439	status = "okay";
440	num-cs = <1>;
441	pinctrl-names = "default";
442	pinctrl-0 = <&pinctrl_spi0_default>;
443
444	spi0_flash0: flash@0 {
445		#address-cells = <1>;
446		#size-cells = <1>;
447		compatible = "sst,sst25wf080", "jedec,spi-nor";
448		spi-max-frequency = <50000000>;
449		reg = <0>;
450
451		partition@0 {
452			label = "spi0-data";
453			reg = <0x0 0x100000>;
454		};
455	};
456};
457
458&spi1 {
459	status = "okay";
460	num-cs = <1>;
461	pinctrl-names = "default";
462	pinctrl-0 = <&pinctrl_spi1_default>;
463
464	spi1_flash0: flash@0 {
465		#address-cells = <1>;
466		#size-cells = <1>;
467		compatible = "atmel,at45db041e", "atmel,at45", "atmel,dataflash";
468		spi-max-frequency = <20000000>;
469		reg = <0>;
470
471		partition@0 {
472			label = "spi1-data";
473			reg = <0x0 0x84000>;
474		};
475	};
476};
477
478/* ULPI SMSC USB3320 */
479&usb1 {
480	status = "okay";
481	pinctrl-names = "default";
482	pinctrl-0 = <&pinctrl_usb1_default>;
483};
484
485&dwc3_1 {
486	status = "okay";
487	dr_mode = "host";
488	snps,usb3_lpm_capable;
489	maximum-speed = "super-speed";
490};
491
492&uart0 {
493	status = "okay";
494	pinctrl-names = "default";
495	pinctrl-0 = <&pinctrl_uart0_default>;
496};
497
498&uart1 {
499	status = "okay";
500	pinctrl-names = "default";
501	pinctrl-0 = <&pinctrl_uart1_default>;
502};
503