1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
4 *
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * Michal Simek <michal.simek@amd.com>
9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk-ccf.dtsi"
15#include <dt-bindings/phy/phy.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18
19/ {
20	model = "ZynqMP zc1751-xm015-dc1 RevA";
21	compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
22
23	aliases {
24		ethernet0 = &gem3;
25		i2c0 = &i2c1;
26		mmc0 = &sdhci0;
27		mmc1 = &sdhci1;
28		rtc0 = &rtc;
29		serial0 = &uart0;
30		spi0 = &qspi;
31		usb0 = &usb0;
32	};
33
34	chosen {
35		bootargs = "earlycon";
36		stdout-path = "serial0:115200n8";
37	};
38
39	memory@0 {
40		device_type = "memory";
41		reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
42	};
43
44	clock_si5338_0: clk27 {	/* u55 SI5338-GM */
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <27000000>;
48	};
49
50	clock_si5338_2: clk26 {
51		compatible = "fixed-clock";
52		#clock-cells = <0>;
53		clock-frequency = <26000000>;
54	};
55
56	clock_si5338_3: clk150 {
57		compatible = "fixed-clock";
58		#clock-cells = <0>;
59		clock-frequency = <150000000>;
60	};
61};
62
63&fpd_dma_chan1 {
64	status = "okay";
65};
66
67&fpd_dma_chan2 {
68	status = "okay";
69};
70
71&fpd_dma_chan3 {
72	status = "okay";
73};
74
75&fpd_dma_chan4 {
76	status = "okay";
77};
78
79&fpd_dma_chan5 {
80	status = "okay";
81};
82
83&fpd_dma_chan6 {
84	status = "okay";
85};
86
87&fpd_dma_chan7 {
88	status = "okay";
89};
90
91&fpd_dma_chan8 {
92	status = "okay";
93};
94
95&gem3 {
96	status = "okay";
97	phy-handle = <&phy0>;
98	phy-mode = "rgmii-id";
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_gem3_default>;
101	phy0: ethernet-phy@0 {
102		reg = <0>;
103	};
104};
105
106&gpio {
107	status = "okay";
108	pinctrl-names = "default";
109	pinctrl-0 = <&pinctrl_gpio_default>;
110};
111
112&gpu {
113	status = "okay";
114};
115
116&i2c1 {
117	status = "okay";
118	clock-frequency = <400000>;
119	pinctrl-names = "default", "gpio";
120	pinctrl-0 = <&pinctrl_i2c1_default>;
121	pinctrl-1 = <&pinctrl_i2c1_gpio>;
122	scl-gpios = <&gpio 36 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
123	sda-gpios = <&gpio 37 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
124
125	eeprom: eeprom@55 {
126		compatible = "atmel,24c64"; /* 24AA64 */
127		reg = <0x55>;
128	};
129};
130
131&pinctrl0 {
132	status = "okay";
133	pinctrl_i2c1_default: i2c1-default {
134		mux {
135			groups = "i2c1_9_grp";
136			function = "i2c1";
137		};
138
139		conf {
140			groups = "i2c1_9_grp";
141			bias-pull-up;
142			slew-rate = <SLEW_RATE_SLOW>;
143			power-source = <IO_STANDARD_LVCMOS18>;
144		};
145	};
146
147	pinctrl_i2c1_gpio: i2c1-gpio {
148		mux {
149			groups = "gpio0_36_grp", "gpio0_37_grp";
150			function = "gpio0";
151		};
152
153		conf {
154			groups = "gpio0_36_grp", "gpio0_37_grp";
155			slew-rate = <SLEW_RATE_SLOW>;
156			power-source = <IO_STANDARD_LVCMOS18>;
157		};
158	};
159
160	pinctrl_uart0_default: uart0-default {
161		mux {
162			groups = "uart0_8_grp";
163			function = "uart0";
164		};
165
166		conf {
167			groups = "uart0_8_grp";
168			slew-rate = <SLEW_RATE_SLOW>;
169			power-source = <IO_STANDARD_LVCMOS18>;
170		};
171
172		conf-rx {
173			pins = "MIO34";
174			bias-high-impedance;
175		};
176
177		conf-tx {
178			pins = "MIO35";
179			bias-disable;
180		};
181	};
182
183	pinctrl_usb0_default: usb0-default {
184		mux {
185			groups = "usb0_0_grp";
186			function = "usb0";
187		};
188
189		conf {
190			groups = "usb0_0_grp";
191			power-source = <IO_STANDARD_LVCMOS18>;
192		};
193
194		conf-rx {
195			pins = "MIO52", "MIO53", "MIO55";
196			bias-high-impedance;
197			drive-strength = <12>;
198			slew-rate = <SLEW_RATE_FAST>;
199		};
200
201		conf-tx {
202			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
203			       "MIO60", "MIO61", "MIO62", "MIO63";
204			bias-disable;
205			drive-strength = <4>;
206			slew-rate = <SLEW_RATE_SLOW>;
207		};
208	};
209
210	pinctrl_gem3_default: gem3-default {
211		mux {
212			function = "ethernet3";
213			groups = "ethernet3_0_grp";
214		};
215
216		conf {
217			groups = "ethernet3_0_grp";
218			slew-rate = <SLEW_RATE_SLOW>;
219			power-source = <IO_STANDARD_LVCMOS18>;
220		};
221
222		conf-rx {
223			pins = "MIO70", "MIO71", "MIO72", "MIO73", "MIO74",
224									"MIO75";
225			bias-high-impedance;
226			low-power-disable;
227		};
228
229		conf-tx {
230			pins = "MIO64", "MIO65", "MIO66", "MIO67", "MIO68",
231									"MIO69";
232			bias-disable;
233			low-power-enable;
234		};
235
236		mux-mdio {
237			function = "mdio3";
238			groups = "mdio3_0_grp";
239		};
240
241		conf-mdio {
242			groups = "mdio3_0_grp";
243			slew-rate = <SLEW_RATE_SLOW>;
244			power-source = <IO_STANDARD_LVCMOS18>;
245			bias-disable;
246		};
247	};
248
249	pinctrl_sdhci0_default: sdhci0-default {
250		mux {
251			groups = "sdio0_0_grp";
252			function = "sdio0";
253		};
254
255		conf {
256			groups = "sdio0_0_grp";
257			slew-rate = <SLEW_RATE_SLOW>;
258			power-source = <IO_STANDARD_LVCMOS18>;
259			bias-disable;
260		};
261
262		mux-cd {
263			groups = "sdio0_cd_0_grp";
264			function = "sdio0_cd";
265		};
266
267		conf-cd {
268			groups = "sdio0_cd_0_grp";
269			bias-high-impedance;
270			bias-pull-up;
271			slew-rate = <SLEW_RATE_SLOW>;
272			power-source = <IO_STANDARD_LVCMOS18>;
273		};
274
275		mux-wp {
276			groups = "sdio0_wp_0_grp";
277			function = "sdio0_wp";
278		};
279
280		conf-wp {
281			groups = "sdio0_wp_0_grp";
282			bias-high-impedance;
283			bias-pull-up;
284			slew-rate = <SLEW_RATE_SLOW>;
285			power-source = <IO_STANDARD_LVCMOS18>;
286		};
287	};
288
289	pinctrl_sdhci1_default: sdhci1-default {
290		mux {
291			groups = "sdio1_0_grp";
292			function = "sdio1";
293		};
294
295		conf {
296			groups = "sdio1_0_grp";
297			slew-rate = <SLEW_RATE_SLOW>;
298			power-source = <IO_STANDARD_LVCMOS18>;
299			bias-disable;
300		};
301
302		mux-cd {
303			groups = "sdio1_cd_0_grp";
304			function = "sdio1_cd";
305		};
306
307		conf-cd {
308			groups = "sdio1_cd_0_grp";
309			bias-high-impedance;
310			bias-pull-up;
311			slew-rate = <SLEW_RATE_SLOW>;
312			power-source = <IO_STANDARD_LVCMOS18>;
313		};
314
315		mux-wp {
316			groups = "sdio1_wp_0_grp";
317			function = "sdio1_wp";
318		};
319
320		conf-wp {
321			groups = "sdio1_wp_0_grp";
322			bias-high-impedance;
323			bias-pull-up;
324			slew-rate = <SLEW_RATE_SLOW>;
325			power-source = <IO_STANDARD_LVCMOS18>;
326		};
327	};
328
329	pinctrl_gpio_default: gpio-default {
330		mux {
331			function = "gpio0";
332			groups = "gpio0_38_grp";
333		};
334
335		conf {
336			groups = "gpio0_38_grp";
337			bias-disable;
338			slew-rate = <SLEW_RATE_SLOW>;
339			power-source = <IO_STANDARD_LVCMOS18>;
340		};
341	};
342};
343
344&psgtr {
345	status = "okay";
346	/* dp, usb3, sata */
347	clocks = <&clock_si5338_0>, <&clock_si5338_2>, <&clock_si5338_3>;
348	clock-names = "ref1", "ref2", "ref3";
349};
350
351&qspi {
352	status = "okay";
353	flash@0 {
354		compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
355		#address-cells = <1>;
356		#size-cells = <1>;
357		reg = <0x0>;
358		spi-tx-bus-width = <4>;
359		spi-rx-bus-width = <4>;
360		spi-max-frequency = <108000000>; /* Based on DC1 spec */
361	};
362};
363
364&rtc {
365	status = "okay";
366};
367
368&sata {
369	status = "okay";
370	/* SATA phy OOB timing settings */
371	ceva,p0-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
372	ceva,p0-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
373	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
374	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
375	ceva,p1-cominit-params = /bits/ 8 <0x1B 0x4D 0x18 0x28>;
376	ceva,p1-comwake-params = /bits/ 8 <0x06 0x19 0x08 0x0E>;
377	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
378	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
379	phy-names = "sata-phy";
380	phys = <&psgtr 3 PHY_TYPE_SATA 1 3>;
381};
382
383/* eMMC */
384&sdhci0 {
385	status = "okay";
386	pinctrl-names = "default";
387	pinctrl-0 = <&pinctrl_sdhci0_default>;
388	bus-width = <8>;
389	xlnx,mio-bank = <0>;
390};
391
392/* SD1 with level shifter */
393&sdhci1 {
394	status = "okay";
395	/*
396	 * This property should be removed for supporting UHS mode
397	 */
398	no-1-8-v;
399	pinctrl-names = "default";
400	pinctrl-0 = <&pinctrl_sdhci1_default>;
401	xlnx,mio-bank = <1>;
402};
403
404&uart0 {
405	status = "okay";
406	pinctrl-names = "default";
407	pinctrl-0 = <&pinctrl_uart0_default>;
408};
409
410/* ULPI SMSC USB3320 */
411&usb0 {
412	status = "okay";
413	pinctrl-names = "default";
414	pinctrl-0 = <&pinctrl_usb0_default>;
415	phy-names = "usb3-phy";
416	phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
417};
418
419&dwc3_0 {
420	status = "okay";
421	dr_mode = "host";
422	snps,usb3_lpm_capable;
423	maximum-speed = "super-speed";
424};
425
426&zynqmp_dpdma {
427	status = "okay";
428};
429
430&zynqmp_dpsub {
431	status = "okay";
432	phy-names = "dp-phy0", "dp-phy1";
433	phys = <&psgtr 1 PHY_TYPE_DP 0 0>,
434	       <&psgtr 0 PHY_TYPE_DP 1 1>;
435};
436