1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for KV260 revA Carrier Card
4 *
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
7 *
8 * SD level shifter:
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
12 *
13 * Michal Simek <michal.simek@amd.com>
14 */
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/net/ti-dp83867.h>
18#include <dt-bindings/phy/phy.h>
19#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20
21/dts-v1/;
22/plugin/;
23
24&i2c1 { /* I2C_SCK C23/C24 - MIO from SOM */
25	#address-cells = <1>;
26	#size-cells = <0>;
27	pinctrl-names = "default", "gpio";
28	pinctrl-0 = <&pinctrl_i2c1_default>;
29	pinctrl-1 = <&pinctrl_i2c1_gpio>;
30	scl-gpios = <&gpio 24 GPIO_ACTIVE_HIGH>;
31	sda-gpios = <&gpio 25 GPIO_ACTIVE_HIGH>;
32
33	/* u14 - 0x40 - ina260 */
34	/* u27 - 0xe0 - STDP4320 DP/HDMI splitter */
35};
36
37&amba {
38	si5332_0: si5332_0 { /* u17 */
39		compatible = "fixed-clock";
40		#clock-cells = <0>;
41		clock-frequency = <125000000>;
42	};
43
44	si5332_1: si5332_1 { /* u17 */
45		compatible = "fixed-clock";
46		#clock-cells = <0>;
47		clock-frequency = <25000000>;
48	};
49
50	si5332_2: si5332_2 { /* u17 */
51		compatible = "fixed-clock";
52		#clock-cells = <0>;
53		clock-frequency = <48000000>;
54	};
55
56	si5332_3: si5332_3 { /* u17 */
57		compatible = "fixed-clock";
58		#clock-cells = <0>;
59		clock-frequency = <24000000>;
60	};
61
62	si5332_4: si5332_4 { /* u17 */
63		compatible = "fixed-clock";
64		#clock-cells = <0>;
65		clock-frequency = <26000000>;
66	};
67
68	si5332_5: si5332_5 { /* u17 */
69		compatible = "fixed-clock";
70		#clock-cells = <0>;
71		clock-frequency = <27000000>;
72	};
73};
74
75/* DP/USB 3.0 and SATA */
76&psgtr {
77	status = "okay";
78	/* pcie, usb3, sata */
79	clocks = <&si5332_5>, <&si5332_4>, <&si5332_0>;
80	clock-names = "ref0", "ref1", "ref2";
81};
82
83&sata {
84	status = "okay";
85	/* SATA OOB timing settings */
86	ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
87	ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
88	ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
89	ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
90	ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
91	ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
92	ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
93	ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
94	phy-names = "sata-phy";
95	phys = <&psgtr 3 PHY_TYPE_SATA 1 2>;
96};
97
98&zynqmp_dpsub {
99	status = "okay";
100	phy-names = "dp-phy0", "dp-phy1";
101	phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>;
102	assigned-clock-rates = <27000000>, <25000000>, <300000000>;
103};
104
105&zynqmp_dpdma {
106	status = "okay";
107	assigned-clock-rates = <600000000>;
108};
109
110&usb0 {
111	status = "okay";
112	pinctrl-names = "default";
113	pinctrl-0 = <&pinctrl_usb0_default>;
114	phy-names = "usb3-phy";
115	phys = <&psgtr 2 PHY_TYPE_USB3 0 1>;
116	/* missing usb5744 - u43 */
117};
118
119&dwc3_0 {
120	status = "okay";
121	dr_mode = "host";
122	snps,usb3_lpm_capable;
123	maximum-speed = "super-speed";
124};
125
126&sdhci1 { /* on CC with tuned parameters */
127	status = "okay";
128	pinctrl-names = "default";
129	pinctrl-0 = <&pinctrl_sdhci1_default>;
130	/*
131	 * SD 3.0 requires level shifter and this property
132	 * should be removed if the board has level shifter and
133	 * need to work in UHS mode
134	 */
135	no-1-8-v;
136	disable-wp;
137	xlnx,mio-bank = <1>;
138	assigned-clock-rates = <187498123>;
139	bus-width = <4>;
140};
141
142&gem3 { /* required by spec */
143	status = "okay";
144	pinctrl-names = "default";
145	pinctrl-0 = <&pinctrl_gem3_default>;
146	phy-handle = <&phy0>;
147	phy-mode = "rgmii-id";
148
149	mdio: mdio {
150		#address-cells = <1>;
151		#size-cells = <0>;
152
153		phy0: ethernet-phy@1 {
154			#phy-cells = <1>;
155			reg = <1>;
156			compatible = "ethernet-phy-id2000.a231";
157			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
158			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
159			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
160			ti,dp83867-rxctrl-strap-quirk;
161			reset-assert-us = <100>;
162			reset-deassert-us = <280>;
163			reset-gpios = <&gpio 38 GPIO_ACTIVE_LOW>;
164		};
165	};
166};
167
168&pinctrl0 { /* required by spec */
169	status = "okay";
170
171	pinctrl_uart1_default: uart1-default {
172		conf {
173			groups = "uart1_9_grp";
174			slew-rate = <SLEW_RATE_SLOW>;
175			power-source = <IO_STANDARD_LVCMOS18>;
176			drive-strength = <12>;
177		};
178
179		conf-rx {
180			pins = "MIO37";
181			bias-high-impedance;
182		};
183
184		conf-tx {
185			pins = "MIO36";
186			bias-disable;
187		};
188
189		mux {
190			groups = "uart1_9_grp";
191			function = "uart1";
192		};
193	};
194
195	pinctrl_i2c1_default: i2c1-default {
196		conf {
197			groups = "i2c1_6_grp";
198			bias-pull-up;
199			slew-rate = <SLEW_RATE_SLOW>;
200			power-source = <IO_STANDARD_LVCMOS18>;
201		};
202
203		mux {
204			groups = "i2c1_6_grp";
205			function = "i2c1";
206		};
207	};
208
209	pinctrl_i2c1_gpio: i2c1-gpio {
210		conf {
211			groups = "gpio0_24_grp", "gpio0_25_grp";
212			slew-rate = <SLEW_RATE_SLOW>;
213			power-source = <IO_STANDARD_LVCMOS18>;
214		};
215
216		mux {
217			groups = "gpio0_24_grp", "gpio0_25_grp";
218			function = "gpio0";
219		};
220	};
221
222	pinctrl_gem3_default: gem3-default {
223		conf {
224			groups = "ethernet3_0_grp";
225			slew-rate = <SLEW_RATE_SLOW>;
226			power-source = <IO_STANDARD_LVCMOS18>;
227		};
228
229		conf-rx {
230			pins = "MIO70", "MIO72", "MIO74";
231			bias-high-impedance;
232			low-power-disable;
233		};
234
235		conf-bootstrap {
236			pins = "MIO71", "MIO73", "MIO75";
237			bias-disable;
238			low-power-disable;
239		};
240
241		conf-tx {
242			pins = "MIO64", "MIO65", "MIO66",
243				"MIO67", "MIO68", "MIO69";
244			bias-disable;
245			low-power-enable;
246		};
247
248		conf-mdio {
249			groups = "mdio3_0_grp";
250			slew-rate = <SLEW_RATE_SLOW>;
251			power-source = <IO_STANDARD_LVCMOS18>;
252			bias-disable;
253		};
254
255		mux-mdio {
256			function = "mdio3";
257			groups = "mdio3_0_grp";
258		};
259
260		mux {
261			function = "ethernet3";
262			groups = "ethernet3_0_grp";
263		};
264	};
265
266	pinctrl_usb0_default: usb0-default {
267		conf {
268			groups = "usb0_0_grp";
269			power-source = <IO_STANDARD_LVCMOS18>;
270		};
271
272		conf-rx {
273			pins = "MIO52", "MIO53", "MIO55";
274			bias-high-impedance;
275			drive-strength = <12>;
276			slew-rate = <SLEW_RATE_FAST>;
277		};
278
279		conf-tx {
280			pins = "MIO54", "MIO56", "MIO57", "MIO58", "MIO59",
281			"MIO60", "MIO61", "MIO62", "MIO63";
282			bias-disable;
283			drive-strength = <4>;
284			slew-rate = <SLEW_RATE_SLOW>;
285		};
286
287		mux {
288			groups = "usb0_0_grp";
289			function = "usb0";
290		};
291	};
292
293	pinctrl_sdhci1_default: sdhci1-default {
294		conf {
295			groups = "sdio1_0_grp";
296			slew-rate = <SLEW_RATE_SLOW>;
297			power-source = <IO_STANDARD_LVCMOS18>;
298			bias-disable;
299		};
300
301		conf-cd {
302			groups = "sdio1_cd_0_grp";
303			bias-high-impedance;
304			bias-pull-up;
305			slew-rate = <SLEW_RATE_SLOW>;
306			power-source = <IO_STANDARD_LVCMOS18>;
307		};
308
309		mux-cd {
310			groups = "sdio1_cd_0_grp";
311			function = "sdio1_cd";
312		};
313
314		mux {
315			groups = "sdio1_0_grp";
316			function = "sdio1";
317		};
318	};
319};
320
321&uart1 {
322	status = "okay";
323	pinctrl-names = "default";
324	pinctrl-0 = <&pinctrl_uart1_default>;
325};
326