1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Clock specification for Xilinx ZynqMP
4 *
5 * (C) Copyright 2017 - 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9
10#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
11/ {
12	pss_ref_clk: pss_ref_clk {
13		u-boot,dm-pre-reloc;
14		compatible = "fixed-clock";
15		#clock-cells = <0>;
16		clock-frequency = <33333333>;
17	};
18
19	video_clk: video_clk {
20		u-boot,dm-pre-reloc;
21		compatible = "fixed-clock";
22		#clock-cells = <0>;
23		clock-frequency = <27000000>;
24	};
25
26	pss_alt_ref_clk: pss_alt_ref_clk {
27		u-boot,dm-pre-reloc;
28		compatible = "fixed-clock";
29		#clock-cells = <0>;
30		clock-frequency = <0>;
31	};
32
33	gt_crx_ref_clk: gt_crx_ref_clk {
34		u-boot,dm-pre-reloc;
35		compatible = "fixed-clock";
36		#clock-cells = <0>;
37		clock-frequency = <108000000>;
38	};
39
40	aux_ref_clk: aux_ref_clk {
41		u-boot,dm-pre-reloc;
42		compatible = "fixed-clock";
43		#clock-cells = <0>;
44		clock-frequency = <27000000>;
45	};
46};
47
48&can0 {
49	clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
50};
51
52&can1 {
53	clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
54};
55
56&cpu0 {
57	clocks = <&zynqmp_clk ACPU>;
58};
59
60&fpd_dma_chan1 {
61	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
62};
63
64&fpd_dma_chan2 {
65	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
66};
67
68&fpd_dma_chan3 {
69	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
70};
71
72&fpd_dma_chan4 {
73	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
74};
75
76&fpd_dma_chan5 {
77	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
78};
79
80&fpd_dma_chan6 {
81	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
82};
83
84&fpd_dma_chan7 {
85	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
86};
87
88&fpd_dma_chan8 {
89	clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
90};
91
92&lpd_dma_chan1 {
93	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
94};
95
96&lpd_dma_chan2 {
97	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
98};
99
100&lpd_dma_chan3 {
101	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
102};
103
104&lpd_dma_chan4 {
105	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
106};
107
108&lpd_dma_chan5 {
109	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
110};
111
112&lpd_dma_chan6 {
113	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
114};
115
116&lpd_dma_chan7 {
117	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
118};
119
120&lpd_dma_chan8 {
121	clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
122};
123
124&gem0 {
125	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
126		 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
127		 <&zynqmp_clk GEM_TSU>;
128	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
129};
130
131&gem1 {
132	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
133		 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
134		 <&zynqmp_clk GEM_TSU>;
135	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
136};
137
138&gem2 {
139	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
140		 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
141		 <&zynqmp_clk GEM_TSU>;
142	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
143};
144
145&gem3 {
146	clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
147		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
148		 <&zynqmp_clk GEM_TSU>;
149	clock-names = "pclk", "hclk", "tx_clk", "rx_clk", "tsu_clk";
150};
151
152&gpio {
153	clocks = <&zynqmp_clk LPD_LSBUS>;
154};
155
156&i2c0 {
157	clocks = <&zynqmp_clk I2C0_REF>;
158};
159
160&i2c1 {
161	clocks = <&zynqmp_clk I2C1_REF>;
162};
163
164&pcie {
165	clocks = <&zynqmp_clk PCIE_REF>;
166};
167
168&sata {
169	clocks = <&zynqmp_clk SATA_REF>;
170};
171
172&sdhci0 {
173	clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
174};
175
176&sdhci1 {
177	clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
178};
179
180&spi0 {
181	clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
182};
183
184&spi1 {
185	clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
186};
187
188&ttc0 {
189	clocks = <&zynqmp_clk LPD_LSBUS>;
190};
191
192&ttc1 {
193	clocks = <&zynqmp_clk LPD_LSBUS>;
194};
195
196&ttc2 {
197	clocks = <&zynqmp_clk LPD_LSBUS>;
198};
199
200&ttc3 {
201	clocks = <&zynqmp_clk LPD_LSBUS>;
202};
203
204&uart0 {
205	clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
206};
207
208&uart1 {
209	clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
210};
211
212&usb0 {
213	clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
214};
215
216&usb1 {
217	clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
218};
219
220&watchdog0 {
221	clocks = <&zynqmp_clk WDT>;
222};
223