1*518d432fSYuji Ishikawa// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2*518d432fSYuji Ishikawa/* 3*518d432fSYuji Ishikawa * Device Tree File for TMPV7708 VisROBO VRB board 4*518d432fSYuji Ishikawa * 5*518d432fSYuji Ishikawa * (C) Copyright 2020, 2021, Toshiba Corporation. 6*518d432fSYuji Ishikawa * (C) Copyright 2020, Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp> 7*518d432fSYuji Ishikawa */ 8*518d432fSYuji Ishikawa 9*518d432fSYuji Ishikawa/dts-v1/; 10*518d432fSYuji Ishikawa 11*518d432fSYuji Ishikawa#include "tmpv7708-visrobo-vrc.dtsi" 12*518d432fSYuji Ishikawa 13*518d432fSYuji Ishikawa/ { 14*518d432fSYuji Ishikawa model = "Toshiba TMPV7708 VisROBO (VRB) board"; 15*518d432fSYuji Ishikawa compatible = "toshiba,tmpv7708-visrobo-vrb", "toshiba,tmpv7708"; 16*518d432fSYuji Ishikawa 17*518d432fSYuji Ishikawa aliases { 18*518d432fSYuji Ishikawa serial0 = &uart0; 19*518d432fSYuji Ishikawa serial1 = &uart1; 20*518d432fSYuji Ishikawa }; 21*518d432fSYuji Ishikawa 22*518d432fSYuji Ishikawa chosen { 23*518d432fSYuji Ishikawa stdout-path = "serial0:115200n8"; 24*518d432fSYuji Ishikawa }; 25*518d432fSYuji Ishikawa 26*518d432fSYuji Ishikawa /* 768MB memory */ 27*518d432fSYuji Ishikawa memory@80000000 { 28*518d432fSYuji Ishikawa device_type = "memory"; 29*518d432fSYuji Ishikawa reg = <0x0 0x80000000 0x0 0x30000000>; 30*518d432fSYuji Ishikawa }; 31*518d432fSYuji Ishikawa}; 32*518d432fSYuji Ishikawa 33*518d432fSYuji Ishikawa&uart0 { 34*518d432fSYuji Ishikawa status = "okay"; 35*518d432fSYuji Ishikawa clocks = <&uart_clk>; 36*518d432fSYuji Ishikawa clock-names = "apb_pclk"; 37*518d432fSYuji Ishikawa}; 38*518d432fSYuji Ishikawa 39*518d432fSYuji Ishikawa&uart1 { 40*518d432fSYuji Ishikawa status = "okay"; 41*518d432fSYuji Ishikawa clocks = <&uart_clk>; 42*518d432fSYuji Ishikawa clock-names = "apb_pclk"; 43*518d432fSYuji Ishikawa}; 44*518d432fSYuji Ishikawa 45*518d432fSYuji Ishikawa&piether { 46*518d432fSYuji Ishikawa status = "okay"; 47*518d432fSYuji Ishikawa phy-handle = <&phy0>; 48*518d432fSYuji Ishikawa phy-mode = "rgmii-id"; 49*518d432fSYuji Ishikawa clocks = <&clk300mhz>, <&clk125mhz>; 50*518d432fSYuji Ishikawa clock-names = "stmmaceth", "phy_ref_clk"; 51*518d432fSYuji Ishikawa 52*518d432fSYuji Ishikawa mdio0 { 53*518d432fSYuji Ishikawa #address-cells = <1>; 54*518d432fSYuji Ishikawa #size-cells = <0>; 55*518d432fSYuji Ishikawa compatible = "snps,dwmac-mdio"; 56*518d432fSYuji Ishikawa phy0: ethernet-phy@1 { 57*518d432fSYuji Ishikawa device_type = "ethernet-phy"; 58*518d432fSYuji Ishikawa reg = <0x1>; 59*518d432fSYuji Ishikawa }; 60*518d432fSYuji Ishikawa }; 61*518d432fSYuji Ishikawa}; 62