1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 chipid@43000014 { 38 compatible = "ti,am654-chipid"; 39 reg = <0x00 0x43000014 0x00 0x4>; 40 }; 41 42 mcu_ram: sram@41c00000 { 43 compatible = "mmio-sram"; 44 reg = <0x00 0x41c00000 0x00 0x100000>; 45 ranges = <0x00 0x00 0x41c00000 0x100000>; 46 #address-cells = <1>; 47 #size-cells = <1>; 48 }; 49 50 wkup_pmx0: pinctrl@4301c000 { 51 compatible = "pinctrl-single"; 52 /* Proxy 0 addressing */ 53 reg = <0x00 0x4301c000 0x00 0x178>; 54 #pinctrl-cells = <1>; 55 pinctrl-single,register-width = <32>; 56 pinctrl-single,function-mask = <0xffffffff>; 57 }; 58 59 wkup_gpio_intr: interrupt-controller@42200000 { 60 compatible = "ti,sci-intr"; 61 reg = <0x00 0x42200000 0x00 0x400>; 62 ti,intr-trigger-type = <1>; 63 interrupt-controller; 64 interrupt-parent = <&gic500>; 65 #interrupt-cells = <1>; 66 ti,sci = <&sms>; 67 ti,sci-dev-id = <177>; 68 ti,interrupt-ranges = <16 928 16>; 69 }; 70 71 mcu_conf: syscon@40f00000 { 72 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 73 reg = <0x00 0x40f00000 0x00 0x20000>; 74 #address-cells = <1>; 75 #size-cells = <1>; 76 ranges = <0x00 0x00 0x40f00000 0x20000>; 77 78 phy_gmii_sel: phy@4040 { 79 compatible = "ti,am654-phy-gmii-sel"; 80 reg = <0x4040 0x4>; 81 #phy-cells = <1>; 82 }; 83 }; 84 85 wkup_uart0: serial@42300000 { 86 compatible = "ti,j721e-uart", "ti,am654-uart"; 87 reg = <0x00 0x42300000 0x00 0x200>; 88 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 89 current-speed = <115200>; 90 clocks = <&k3_clks 397 0>; 91 clock-names = "fclk"; 92 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>; 93 status = "disabled"; 94 }; 95 96 mcu_uart0: serial@40a00000 { 97 compatible = "ti,j721e-uart", "ti,am654-uart"; 98 reg = <0x00 0x40a00000 0x00 0x200>; 99 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 100 current-speed = <115200>; 101 clocks = <&k3_clks 149 0>; 102 clock-names = "fclk"; 103 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 104 status = "disabled"; 105 }; 106 107 wkup_gpio0: gpio@42110000 { 108 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 109 reg = <0x00 0x42110000 0x00 0x100>; 110 gpio-controller; 111 #gpio-cells = <2>; 112 interrupt-parent = <&wkup_gpio_intr>; 113 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 114 interrupt-controller; 115 #interrupt-cells = <2>; 116 ti,ngpio = <89>; 117 ti,davinci-gpio-unbanked = <0>; 118 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 119 clocks = <&k3_clks 167 0>; 120 clock-names = "gpio"; 121 status = "disabled"; 122 }; 123 124 wkup_gpio1: gpio@42100000 { 125 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 126 reg = <0x00 0x42100000 0x00 0x100>; 127 gpio-controller; 128 #gpio-cells = <2>; 129 interrupt-parent = <&wkup_gpio_intr>; 130 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 131 interrupt-controller; 132 #interrupt-cells = <2>; 133 ti,ngpio = <89>; 134 ti,davinci-gpio-unbanked = <0>; 135 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 136 clocks = <&k3_clks 168 0>; 137 clock-names = "gpio"; 138 status = "disabled"; 139 }; 140 141 wkup_i2c0: i2c@42120000 { 142 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 143 reg = <0x00 0x42120000 0x00 0x100>; 144 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 145 #address-cells = <1>; 146 #size-cells = <0>; 147 clocks = <&k3_clks 279 2>; 148 clock-names = "fck"; 149 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 150 status = "disabled"; 151 }; 152 153 mcu_i2c0: i2c@40b00000 { 154 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 155 reg = <0x00 0x40b00000 0x00 0x100>; 156 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 157 #address-cells = <1>; 158 #size-cells = <0>; 159 clocks = <&k3_clks 277 2>; 160 clock-names = "fck"; 161 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 162 status = "disabled"; 163 }; 164 165 mcu_i2c1: i2c@40b10000 { 166 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 167 reg = <0x00 0x40b10000 0x00 0x100>; 168 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 169 #address-cells = <1>; 170 #size-cells = <0>; 171 clocks = <&k3_clks 278 2>; 172 clock-names = "fck"; 173 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 174 status = "disabled"; 175 }; 176 177 mcu_mcan0: can@40528000 { 178 compatible = "bosch,m_can"; 179 reg = <0x00 0x40528000 0x00 0x200>, 180 <0x00 0x40500000 0x00 0x8000>; 181 reg-names = "m_can", "message_ram"; 182 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>; 183 clocks = <&k3_clks 263 6>, <&k3_clks 263 1>; 184 clock-names = "hclk", "cclk"; 185 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 187 interrupt-names = "int0", "int1"; 188 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 189 status = "disabled"; 190 }; 191 192 mcu_mcan1: can@40568000 { 193 compatible = "bosch,m_can"; 194 reg = <0x00 0x40568000 0x00 0x200>, 195 <0x00 0x40540000 0x00 0x8000>; 196 reg-names = "m_can", "message_ram"; 197 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 198 clocks = <&k3_clks 264 6>, <&k3_clks 264 1>; 199 clock-names = "hclk", "cclk"; 200 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-names = "int0", "int1"; 203 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 204 status = "disabled"; 205 }; 206 207 mcu_navss: bus@28380000{ 208 compatible = "simple-bus"; 209 #address-cells = <2>; 210 #size-cells = <2>; 211 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 212 dma-coherent; 213 dma-ranges; 214 215 mcu_ringacc: ringacc@2b800000 { 216 compatible = "ti,am654-navss-ringacc"; 217 reg = <0x00 0x2b800000 0x00 0x400000>, 218 <0x00 0x2b000000 0x00 0x400000>, 219 <0x00 0x28590000 0x00 0x100>, 220 <0x00 0x2a500000 0x00 0x40000>; 221 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 222 ti,num-rings = <286>; 223 ti,sci-rm-range-gp-rings = <0x1>; 224 ti,sci = <&sms>; 225 ti,sci-dev-id = <328>; 226 msi-parent = <&main_udmass_inta>; 227 }; 228 229 mcu_udmap: dma-controller@285c0000 { 230 compatible = "ti,j721e-navss-mcu-udmap"; 231 reg = <0x00 0x285c0000 0x00 0x100>, 232 <0x00 0x2a800000 0x00 0x40000>, 233 <0x00 0x2aa00000 0x00 0x40000>; 234 reg-names = "gcfg", "rchanrt", "tchanrt"; 235 msi-parent = <&main_udmass_inta>; 236 #dma-cells = <1>; 237 238 ti,sci = <&sms>; 239 ti,sci-dev-id = <329>; 240 ti,ringacc = <&mcu_ringacc>; 241 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 242 <0x0f>; /* TX_HCHAN */ 243 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 244 <0x0b>; /* RX_HCHAN */ 245 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 246 }; 247 }; 248 249 mcu_cpsw: ethernet@46000000 { 250 compatible = "ti,j721e-cpsw-nuss"; 251 #address-cells = <2>; 252 #size-cells = <2>; 253 reg = <0x00 0x46000000 0x00 0x200000>; 254 reg-names = "cpsw_nuss"; 255 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 256 dma-coherent; 257 clocks = <&k3_clks 63 0>; 258 clock-names = "fck"; 259 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 260 261 dmas = <&mcu_udmap 0xf000>, 262 <&mcu_udmap 0xf001>, 263 <&mcu_udmap 0xf002>, 264 <&mcu_udmap 0xf003>, 265 <&mcu_udmap 0xf004>, 266 <&mcu_udmap 0xf005>, 267 <&mcu_udmap 0xf006>, 268 <&mcu_udmap 0xf007>, 269 <&mcu_udmap 0x7000>; 270 dma-names = "tx0", "tx1", "tx2", "tx3", 271 "tx4", "tx5", "tx6", "tx7", 272 "rx"; 273 status = "disabled"; 274 275 ethernet-ports { 276 #address-cells = <1>; 277 #size-cells = <0>; 278 279 mcu_cpsw_port1: port@1 { 280 reg = <1>; 281 ti,mac-only; 282 label = "port1"; 283 ti,syscon-efuse = <&mcu_conf 0x200>; 284 phys = <&phy_gmii_sel 1>; 285 }; 286 }; 287 288 davinci_mdio: mdio@f00 { 289 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 290 reg = <0x00 0xf00 0x00 0x100>; 291 #address-cells = <1>; 292 #size-cells = <0>; 293 clocks = <&k3_clks 63 0>; 294 clock-names = "fck"; 295 bus_freq = <1000000>; 296 }; 297 298 cpts@3d000 { 299 compatible = "ti,am65-cpts"; 300 reg = <0x00 0x3d000 0x00 0x400>; 301 clocks = <&k3_clks 63 3>; 302 clock-names = "cpts"; 303 assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */ 304 assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */ 305 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 306 interrupt-names = "cpts"; 307 ti,cpts-ext-ts-inputs = <4>; 308 ti,cpts-periodic-outputs = <2>; 309 }; 310 }; 311}; 312