1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_mcu_wakeup { 9 sms: system-controller@44083000 { 10 compatible = "ti,k2g-sci"; 11 ti,host-id = <12>; 12 13 mbox-names = "rx", "tx"; 14 15 mboxes = <&secure_proxy_main 11>, 16 <&secure_proxy_main 13>; 17 18 reg-names = "debug_messages"; 19 reg = <0x00 0x44083000 0x00 0x1000>; 20 21 k3_pds: power-controller { 22 compatible = "ti,sci-pm-domain"; 23 #power-domain-cells = <2>; 24 }; 25 26 k3_clks: clock-controller { 27 compatible = "ti,k2g-sci-clk"; 28 #clock-cells = <2>; 29 }; 30 31 k3_reset: reset-controller { 32 compatible = "ti,sci-reset"; 33 #reset-cells = <2>; 34 }; 35 }; 36 37 chipid@43000014 { 38 compatible = "ti,am654-chipid"; 39 reg = <0x00 0x43000014 0x00 0x4>; 40 }; 41 42 secure_proxy_sa3: mailbox@43600000 { 43 compatible = "ti,am654-secure-proxy"; 44 #mbox-cells = <1>; 45 reg-names = "target_data", "rt", "scfg"; 46 reg = <0x00 0x43600000 0x00 0x10000>, 47 <0x00 0x44880000 0x00 0x20000>, 48 <0x00 0x44860000 0x00 0x20000>; 49 /* 50 * Marked Disabled: 51 * Node is incomplete as it is meant for bootloaders and 52 * firmware on non-MPU processors 53 */ 54 status = "disabled"; 55 }; 56 57 mcu_ram: sram@41c00000 { 58 compatible = "mmio-sram"; 59 reg = <0x00 0x41c00000 0x00 0x100000>; 60 ranges = <0x00 0x00 0x41c00000 0x100000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 }; 64 65 wkup_pmx0: pinctrl@4301c000 { 66 compatible = "pinctrl-single"; 67 /* Proxy 0 addressing */ 68 reg = <0x00 0x4301c000 0x00 0x034>; 69 #pinctrl-cells = <1>; 70 pinctrl-single,register-width = <32>; 71 pinctrl-single,function-mask = <0xffffffff>; 72 }; 73 74 wkup_pmx1: pinctrl@4301c038 { 75 compatible = "pinctrl-single"; 76 /* Proxy 0 addressing */ 77 reg = <0x00 0x4301c038 0x00 0x02c>; 78 #pinctrl-cells = <1>; 79 pinctrl-single,register-width = <32>; 80 pinctrl-single,function-mask = <0xffffffff>; 81 }; 82 83 wkup_pmx2: pinctrl@4301c068 { 84 compatible = "pinctrl-single"; 85 /* Proxy 0 addressing */ 86 reg = <0x00 0x4301c068 0x00 0x120>; 87 #pinctrl-cells = <1>; 88 pinctrl-single,register-width = <32>; 89 pinctrl-single,function-mask = <0xffffffff>; 90 }; 91 92 wkup_pmx3: pinctrl@4301c190 { 93 compatible = "pinctrl-single"; 94 /* Proxy 0 addressing */ 95 reg = <0x00 0x4301c190 0x00 0x004>; 96 #pinctrl-cells = <1>; 97 pinctrl-single,register-width = <32>; 98 pinctrl-single,function-mask = <0xffffffff>; 99 }; 100 101 wkup_gpio_intr: interrupt-controller@42200000 { 102 compatible = "ti,sci-intr"; 103 reg = <0x00 0x42200000 0x00 0x400>; 104 ti,intr-trigger-type = <1>; 105 interrupt-controller; 106 interrupt-parent = <&gic500>; 107 #interrupt-cells = <1>; 108 ti,sci = <&sms>; 109 ti,sci-dev-id = <177>; 110 ti,interrupt-ranges = <16 928 16>; 111 }; 112 113 /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */ 114 mcu_timerio_input: pinctrl@40f04200 { 115 compatible = "pinctrl-single"; 116 reg = <0x00 0x40f04200 0x00 0x28>; 117 #pinctrl-cells = <1>; 118 pinctrl-single,register-width = <32>; 119 pinctrl-single,function-mask = <0x0000000f>; 120 /* Non-MPU Firmware usage */ 121 status = "reserved"; 122 }; 123 124 /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */ 125 mcu_timerio_output: pinctrl@40f04280 { 126 compatible = "pinctrl-single"; 127 reg = <0x00 0x40f04280 0x00 0x28>; 128 #pinctrl-cells = <1>; 129 pinctrl-single,register-width = <32>; 130 pinctrl-single,function-mask = <0x0000000f>; 131 /* Non-MPU Firmware usage */ 132 status = "reserved"; 133 }; 134 135 mcu_conf: syscon@40f00000 { 136 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd"; 137 reg = <0x00 0x40f00000 0x00 0x20000>; 138 #address-cells = <1>; 139 #size-cells = <1>; 140 ranges = <0x00 0x00 0x40f00000 0x20000>; 141 142 phy_gmii_sel: phy@4040 { 143 compatible = "ti,am654-phy-gmii-sel"; 144 reg = <0x4040 0x4>; 145 #phy-cells = <1>; 146 }; 147 }; 148 149 mcu_timer0: timer@40400000 { 150 compatible = "ti,am654-timer"; 151 reg = <0x00 0x40400000 0x00 0x400>; 152 interrupts = <GIC_SPI 816 IRQ_TYPE_LEVEL_HIGH>; 153 clocks = <&k3_clks 35 2>; 154 clock-names = "fck"; 155 assigned-clocks = <&k3_clks 35 2>; 156 assigned-clock-parents = <&k3_clks 35 3>; 157 power-domains = <&k3_pds 35 TI_SCI_PD_EXCLUSIVE>; 158 ti,timer-pwm; 159 /* Non-MPU Firmware usage */ 160 status = "reserved"; 161 }; 162 163 mcu_timer1: timer@40410000 { 164 compatible = "ti,am654-timer"; 165 reg = <0x00 0x40410000 0x00 0x400>; 166 interrupts = <GIC_SPI 817 IRQ_TYPE_LEVEL_HIGH>; 167 clocks = <&k3_clks 117 2>; 168 clock-names = "fck"; 169 assigned-clocks = <&k3_clks 117 2>; 170 assigned-clock-parents = <&k3_clks 117 3>; 171 power-domains = <&k3_pds 117 TI_SCI_PD_EXCLUSIVE>; 172 ti,timer-pwm; 173 /* Non-MPU Firmware usage */ 174 status = "reserved"; 175 }; 176 177 mcu_timer2: timer@40420000 { 178 compatible = "ti,am654-timer"; 179 reg = <0x00 0x40420000 0x00 0x400>; 180 interrupts = <GIC_SPI 818 IRQ_TYPE_LEVEL_HIGH>; 181 clocks = <&k3_clks 118 2>; 182 clock-names = "fck"; 183 assigned-clocks = <&k3_clks 118 2>; 184 assigned-clock-parents = <&k3_clks 118 3>; 185 power-domains = <&k3_pds 118 TI_SCI_PD_EXCLUSIVE>; 186 ti,timer-pwm; 187 /* Non-MPU Firmware usage */ 188 status = "reserved"; 189 }; 190 191 mcu_timer3: timer@40430000 { 192 compatible = "ti,am654-timer"; 193 reg = <0x00 0x40430000 0x00 0x400>; 194 interrupts = <GIC_SPI 819 IRQ_TYPE_LEVEL_HIGH>; 195 clocks = <&k3_clks 119 2>; 196 clock-names = "fck"; 197 assigned-clocks = <&k3_clks 119 2>; 198 assigned-clock-parents = <&k3_clks 119 3>; 199 power-domains = <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; 200 ti,timer-pwm; 201 /* Non-MPU Firmware usage */ 202 status = "reserved"; 203 }; 204 205 mcu_timer4: timer@40440000 { 206 compatible = "ti,am654-timer"; 207 reg = <0x00 0x40440000 0x00 0x400>; 208 interrupts = <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&k3_clks 120 2>; 210 clock-names = "fck"; 211 assigned-clocks = <&k3_clks 120 2>; 212 assigned-clock-parents = <&k3_clks 120 3>; 213 power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>; 214 ti,timer-pwm; 215 /* Non-MPU Firmware usage */ 216 status = "reserved"; 217 }; 218 219 mcu_timer5: timer@40450000 { 220 compatible = "ti,am654-timer"; 221 reg = <0x00 0x40450000 0x00 0x400>; 222 interrupts = <GIC_SPI 821 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&k3_clks 121 2>; 224 clock-names = "fck"; 225 assigned-clocks = <&k3_clks 121 2>; 226 assigned-clock-parents = <&k3_clks 121 3>; 227 power-domains = <&k3_pds 121 TI_SCI_PD_EXCLUSIVE>; 228 ti,timer-pwm; 229 /* Non-MPU Firmware usage */ 230 status = "reserved"; 231 }; 232 233 mcu_timer6: timer@40460000 { 234 compatible = "ti,am654-timer"; 235 reg = <0x00 0x40460000 0x00 0x400>; 236 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 237 clocks = <&k3_clks 122 2>; 238 clock-names = "fck"; 239 assigned-clocks = <&k3_clks 122 2>; 240 assigned-clock-parents = <&k3_clks 122 3>; 241 power-domains = <&k3_pds 122 TI_SCI_PD_EXCLUSIVE>; 242 ti,timer-pwm; 243 /* Non-MPU Firmware usage */ 244 status = "reserved"; 245 }; 246 247 mcu_timer7: timer@40470000 { 248 compatible = "ti,am654-timer"; 249 reg = <0x00 0x40470000 0x00 0x400>; 250 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&k3_clks 123 2>; 252 clock-names = "fck"; 253 assigned-clocks = <&k3_clks 123 2>; 254 assigned-clock-parents = <&k3_clks 123 3>; 255 power-domains = <&k3_pds 123 TI_SCI_PD_EXCLUSIVE>; 256 ti,timer-pwm; 257 /* Non-MPU Firmware usage */ 258 status = "reserved"; 259 }; 260 261 mcu_timer8: timer@40480000 { 262 compatible = "ti,am654-timer"; 263 reg = <0x00 0x40480000 0x00 0x400>; 264 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 265 clocks = <&k3_clks 124 2>; 266 clock-names = "fck"; 267 assigned-clocks = <&k3_clks 124 2>; 268 assigned-clock-parents = <&k3_clks 124 3>; 269 power-domains = <&k3_pds 124 TI_SCI_PD_EXCLUSIVE>; 270 ti,timer-pwm; 271 /* Non-MPU Firmware usage */ 272 status = "reserved"; 273 }; 274 275 mcu_timer9: timer@40490000 { 276 compatible = "ti,am654-timer"; 277 reg = <0x00 0x40490000 0x00 0x400>; 278 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&k3_clks 125 2>; 280 clock-names = "fck"; 281 assigned-clocks = <&k3_clks 125 2>; 282 assigned-clock-parents = <&k3_clks 125 3>; 283 power-domains = <&k3_pds 125 TI_SCI_PD_EXCLUSIVE>; 284 ti,timer-pwm; 285 /* Non-MPU Firmware usage */ 286 status = "reserved"; 287 }; 288 289 wkup_uart0: serial@42300000 { 290 compatible = "ti,j721e-uart", "ti,am654-uart"; 291 reg = <0x00 0x42300000 0x00 0x200>; 292 interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>; 293 current-speed = <115200>; 294 clocks = <&k3_clks 397 0>; 295 clock-names = "fclk"; 296 power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>; 297 status = "disabled"; 298 }; 299 300 mcu_uart0: serial@40a00000 { 301 compatible = "ti,j721e-uart", "ti,am654-uart"; 302 reg = <0x00 0x40a00000 0x00 0x200>; 303 interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>; 304 current-speed = <115200>; 305 clocks = <&k3_clks 149 0>; 306 clock-names = "fclk"; 307 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>; 308 status = "disabled"; 309 }; 310 311 wkup_gpio0: gpio@42110000 { 312 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 313 reg = <0x00 0x42110000 0x00 0x100>; 314 gpio-controller; 315 #gpio-cells = <2>; 316 interrupt-parent = <&wkup_gpio_intr>; 317 interrupts = <103>, <104>, <105>, <106>, <107>, <108>; 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 ti,ngpio = <89>; 321 ti,davinci-gpio-unbanked = <0>; 322 power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>; 323 clocks = <&k3_clks 167 0>; 324 clock-names = "gpio"; 325 status = "disabled"; 326 }; 327 328 wkup_gpio1: gpio@42100000 { 329 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 330 reg = <0x00 0x42100000 0x00 0x100>; 331 gpio-controller; 332 #gpio-cells = <2>; 333 interrupt-parent = <&wkup_gpio_intr>; 334 interrupts = <112>, <113>, <114>, <115>, <116>, <117>; 335 interrupt-controller; 336 #interrupt-cells = <2>; 337 ti,ngpio = <89>; 338 ti,davinci-gpio-unbanked = <0>; 339 power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>; 340 clocks = <&k3_clks 168 0>; 341 clock-names = "gpio"; 342 status = "disabled"; 343 }; 344 345 wkup_i2c0: i2c@42120000 { 346 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 347 reg = <0x00 0x42120000 0x00 0x100>; 348 interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 clocks = <&k3_clks 279 2>; 352 clock-names = "fck"; 353 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>; 354 status = "disabled"; 355 }; 356 357 mcu_i2c0: i2c@40b00000 { 358 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 359 reg = <0x00 0x40b00000 0x00 0x100>; 360 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 361 #address-cells = <1>; 362 #size-cells = <0>; 363 clocks = <&k3_clks 277 2>; 364 clock-names = "fck"; 365 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>; 366 status = "disabled"; 367 }; 368 369 mcu_i2c1: i2c@40b10000 { 370 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 371 reg = <0x00 0x40b10000 0x00 0x100>; 372 interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 clocks = <&k3_clks 278 2>; 376 clock-names = "fck"; 377 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>; 378 status = "disabled"; 379 }; 380 381 mcu_mcan0: can@40528000 { 382 compatible = "bosch,m_can"; 383 reg = <0x00 0x40528000 0x00 0x200>, 384 <0x00 0x40500000 0x00 0x8000>; 385 reg-names = "m_can", "message_ram"; 386 power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>; 387 clocks = <&k3_clks 263 6>, <&k3_clks 263 1>; 388 clock-names = "hclk", "cclk"; 389 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 391 interrupt-names = "int0", "int1"; 392 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 393 status = "disabled"; 394 }; 395 396 mcu_mcan1: can@40568000 { 397 compatible = "bosch,m_can"; 398 reg = <0x00 0x40568000 0x00 0x200>, 399 <0x00 0x40540000 0x00 0x8000>; 400 reg-names = "m_can", "message_ram"; 401 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>; 402 clocks = <&k3_clks 264 6>, <&k3_clks 264 1>; 403 clock-names = "hclk", "cclk"; 404 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>, 405 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 406 interrupt-names = "int0", "int1"; 407 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 408 status = "disabled"; 409 }; 410 411 mcu_spi0: spi@40300000 { 412 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 413 reg = <0x00 0x040300000 0x00 0x400>; 414 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 power-domains = <&k3_pds 384 TI_SCI_PD_EXCLUSIVE>; 418 clocks = <&k3_clks 384 0>; 419 status = "disabled"; 420 }; 421 422 mcu_spi1: spi@40310000 { 423 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 424 reg = <0x00 0x040310000 0x00 0x400>; 425 interrupts = <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 power-domains = <&k3_pds 385 TI_SCI_PD_EXCLUSIVE>; 429 clocks = <&k3_clks 385 0>; 430 status = "disabled"; 431 }; 432 433 mcu_spi2: spi@40320000 { 434 compatible = "ti,am654-mcspi", "ti,omap4-mcspi"; 435 reg = <0x00 0x040320000 0x00 0x400>; 436 interrupts = <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 power-domains = <&k3_pds 386 TI_SCI_PD_EXCLUSIVE>; 440 clocks = <&k3_clks 386 0>; 441 status = "disabled"; 442 }; 443 444 mcu_navss: bus@28380000 { 445 compatible = "simple-bus"; 446 #address-cells = <2>; 447 #size-cells = <2>; 448 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>; 449 ti,sci-dev-id = <323>; 450 dma-coherent; 451 dma-ranges; 452 453 mcu_ringacc: ringacc@2b800000 { 454 compatible = "ti,am654-navss-ringacc"; 455 reg = <0x00 0x2b800000 0x00 0x400000>, 456 <0x00 0x2b000000 0x00 0x400000>, 457 <0x00 0x28590000 0x00 0x100>, 458 <0x00 0x2a500000 0x00 0x40000>, 459 <0x00 0x28440000 0x00 0x40000>; 460 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; 461 ti,num-rings = <286>; 462 ti,sci-rm-range-gp-rings = <0x1>; 463 ti,sci = <&sms>; 464 ti,sci-dev-id = <328>; 465 msi-parent = <&main_udmass_inta>; 466 }; 467 468 mcu_udmap: dma-controller@285c0000 { 469 compatible = "ti,j721e-navss-mcu-udmap"; 470 reg = <0x00 0x285c0000 0x00 0x100>, 471 <0x00 0x2a800000 0x00 0x40000>, 472 <0x00 0x2aa00000 0x00 0x40000>; 473 reg-names = "gcfg", "rchanrt", "tchanrt"; 474 msi-parent = <&main_udmass_inta>; 475 #dma-cells = <1>; 476 477 ti,sci = <&sms>; 478 ti,sci-dev-id = <329>; 479 ti,ringacc = <&mcu_ringacc>; 480 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 481 <0x0f>; /* TX_HCHAN */ 482 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 483 <0x0b>; /* RX_HCHAN */ 484 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 485 }; 486 }; 487 488 secure_proxy_mcu: mailbox@2a480000 { 489 compatible = "ti,am654-secure-proxy"; 490 #mbox-cells = <1>; 491 reg-names = "target_data", "rt", "scfg"; 492 reg = <0x00 0x2a480000 0x00 0x80000>, 493 <0x00 0x2a380000 0x00 0x80000>, 494 <0x00 0x2a400000 0x00 0x80000>; 495 /* 496 * Marked Disabled: 497 * Node is incomplete as it is meant for bootloaders and 498 * firmware on non-MPU processors 499 */ 500 status = "disabled"; 501 }; 502 503 mcu_cpsw: ethernet@46000000 { 504 compatible = "ti,j721e-cpsw-nuss"; 505 #address-cells = <2>; 506 #size-cells = <2>; 507 reg = <0x00 0x46000000 0x00 0x200000>; 508 reg-names = "cpsw_nuss"; 509 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>; 510 dma-coherent; 511 clocks = <&k3_clks 63 0>; 512 clock-names = "fck"; 513 power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>; 514 515 dmas = <&mcu_udmap 0xf000>, 516 <&mcu_udmap 0xf001>, 517 <&mcu_udmap 0xf002>, 518 <&mcu_udmap 0xf003>, 519 <&mcu_udmap 0xf004>, 520 <&mcu_udmap 0xf005>, 521 <&mcu_udmap 0xf006>, 522 <&mcu_udmap 0xf007>, 523 <&mcu_udmap 0x7000>; 524 dma-names = "tx0", "tx1", "tx2", "tx3", 525 "tx4", "tx5", "tx6", "tx7", 526 "rx"; 527 status = "disabled"; 528 529 ethernet-ports { 530 #address-cells = <1>; 531 #size-cells = <0>; 532 533 mcu_cpsw_port1: port@1 { 534 reg = <1>; 535 ti,mac-only; 536 label = "port1"; 537 ti,syscon-efuse = <&mcu_conf 0x200>; 538 phys = <&phy_gmii_sel 1>; 539 }; 540 }; 541 542 davinci_mdio: mdio@f00 { 543 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 544 reg = <0x00 0xf00 0x00 0x100>; 545 #address-cells = <1>; 546 #size-cells = <0>; 547 clocks = <&k3_clks 63 0>; 548 clock-names = "fck"; 549 bus_freq = <1000000>; 550 }; 551 552 cpts@3d000 { 553 compatible = "ti,am65-cpts"; 554 reg = <0x00 0x3d000 0x00 0x400>; 555 clocks = <&k3_clks 63 3>; 556 clock-names = "cpts"; 557 assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */ 558 assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */ 559 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 560 interrupt-names = "cpts"; 561 ti,cpts-ext-ts-inputs = <4>; 562 ti,cpts-periodic-outputs = <2>; 563 }; 564 }; 565 566 mcu_r5fss0: r5fss@41000000 { 567 compatible = "ti,j721s2-r5fss"; 568 ti,cluster-mode = <1>; 569 #address-cells = <1>; 570 #size-cells = <1>; 571 ranges = <0x41000000 0x00 0x41000000 0x20000>, 572 <0x41400000 0x00 0x41400000 0x20000>; 573 power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>; 574 575 mcu_r5fss0_core0: r5f@41000000 { 576 compatible = "ti,j721s2-r5f"; 577 reg = <0x41000000 0x00010000>, 578 <0x41010000 0x00010000>; 579 reg-names = "atcm", "btcm"; 580 ti,sci = <&sms>; 581 ti,sci-dev-id = <346>; 582 ti,sci-proc-ids = <0x01 0xff>; 583 resets = <&k3_reset 346 1>; 584 firmware-name = "j784s4-mcu-r5f0_0-fw"; 585 ti,atcm-enable = <1>; 586 ti,btcm-enable = <1>; 587 ti,loczrama = <1>; 588 }; 589 590 mcu_r5fss0_core1: r5f@41400000 { 591 compatible = "ti,j721s2-r5f"; 592 reg = <0x41400000 0x00010000>, 593 <0x41410000 0x00010000>; 594 reg-names = "atcm", "btcm"; 595 ti,sci = <&sms>; 596 ti,sci-dev-id = <347>; 597 ti,sci-proc-ids = <0x02 0xff>; 598 resets = <&k3_reset 347 1>; 599 firmware-name = "j784s4-mcu-r5f0_1-fw"; 600 ti,atcm-enable = <1>; 601 ti,btcm-enable = <1>; 602 ti,loczrama = <1>; 603 }; 604 }; 605 606 wkup_vtm0: temperature-sensor@42040000 { 607 compatible = "ti,j7200-vtm"; 608 reg = <0x00 0x42040000 0x00 0x350>, 609 <0x00 0x42050000 0x00 0x350>; 610 power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>; 611 #thermal-sensor-cells = <1>; 612 }; 613 614 tscadc0: tscadc@40200000 { 615 compatible = "ti,am3359-tscadc"; 616 reg = <0x00 0x40200000 0x00 0x1000>; 617 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 618 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>; 619 clocks = <&k3_clks 0 0>; 620 assigned-clocks = <&k3_clks 0 2>; 621 assigned-clock-rates = <60000000>; 622 clock-names = "fck"; 623 dmas = <&main_udmap 0x7400>, 624 <&main_udmap 0x7401>; 625 dma-names = "fifo0", "fifo1"; 626 status = "disabled"; 627 628 adc { 629 #io-channel-cells = <1>; 630 compatible = "ti,am3359-adc"; 631 }; 632 }; 633 634 tscadc1: tscadc@40210000 { 635 compatible = "ti,am3359-tscadc"; 636 reg = <0x00 0x40210000 0x00 0x1000>; 637 interrupts = <GIC_SPI 861 IRQ_TYPE_LEVEL_HIGH>; 638 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>; 639 clocks = <&k3_clks 1 0>; 640 assigned-clocks = <&k3_clks 1 2>; 641 assigned-clock-rates = <60000000>; 642 clock-names = "fck"; 643 dmas = <&main_udmap 0x7402>, 644 <&main_udmap 0x7403>; 645 dma-names = "fifo0", "fifo1"; 646 status = "disabled"; 647 648 adc { 649 #io-channel-cells = <1>; 650 compatible = "ti,am3359-adc"; 651 }; 652 }; 653 654 fss: bus@47000000 { 655 compatible = "simple-bus"; 656 reg = <0x00 0x47000000 0x00 0x100>; 657 #address-cells = <2>; 658 #size-cells = <2>; 659 ranges; 660 661 ospi0: spi@47040000 { 662 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 663 reg = <0x00 0x47040000 0x00 0x100>, 664 <0x05 0x0000000 0x01 0x0000000>; 665 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 666 cdns,fifo-depth = <256>; 667 cdns,fifo-width = <4>; 668 cdns,trigger-address = <0x0>; 669 clocks = <&k3_clks 161 7>; 670 assigned-clocks = <&k3_clks 161 7>; 671 assigned-clock-parents = <&k3_clks 161 9>; 672 assigned-clock-rates = <166666666>; 673 power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 status = "disabled"; 677 }; 678 679 ospi1: spi@47050000 { 680 compatible = "ti,am654-ospi", "cdns,qspi-nor"; 681 reg = <0x00 0x47050000 0x00 0x100>, 682 <0x07 0x0000000 0x01 0x0000000>; 683 interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>; 684 cdns,fifo-depth = <256>; 685 cdns,fifo-width = <4>; 686 cdns,trigger-address = <0x0>; 687 clocks = <&k3_clks 162 7>; 688 power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>; 689 #address-cells = <1>; 690 #size-cells = <0>; 691 status = "disabled"; 692 }; 693 }; 694}; 695