1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J784S4 SoC Family Main Domain peripherals 4 * 5 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 6 */ 7 8&cbass_main { 9 msmc_ram: sram@70000000 { 10 compatible = "mmio-sram"; 11 reg = <0x00 0x70000000 0x00 0x800000>; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 ranges = <0x00 0x00 0x70000000 0x800000>; 15 16 atf-sram@0 { 17 reg = <0x00 0x20000>; 18 }; 19 20 tifs-sram@1f0000 { 21 reg = <0x1f0000 0x10000>; 22 }; 23 24 l3cache-sram@200000 { 25 reg = <0x200000 0x200000>; 26 }; 27 }; 28 29 gic500: interrupt-controller@1800000 { 30 compatible = "arm,gic-v3"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 #interrupt-cells = <3>; 35 interrupt-controller; 36 reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */ 37 <0x00 0x01900000 0x00 0x100000>, /* GICR */ 38 <0x00 0x6f000000 0x00 0x2000>, /* GICC */ 39 <0x00 0x6f010000 0x00 0x1000>, /* GICH */ 40 <0x00 0x6f020000 0x00 0x2000>; /* GICV */ 41 42 /* vcpumntirq: virtual CPU interface maintenance interrupt */ 43 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 44 45 gic_its: msi-controller@1820000 { 46 compatible = "arm,gic-v3-its"; 47 reg = <0x00 0x01820000 0x00 0x10000>; 48 socionext,synquacer-pre-its = <0x1000000 0x400000>; 49 msi-controller; 50 #msi-cells = <1>; 51 }; 52 }; 53 54 main_gpio_intr: interrupt-controller@a00000 { 55 compatible = "ti,sci-intr"; 56 reg = <0x00 0x00a00000 0x00 0x800>; 57 ti,intr-trigger-type = <1>; 58 interrupt-controller; 59 interrupt-parent = <&gic500>; 60 #interrupt-cells = <1>; 61 ti,sci = <&sms>; 62 ti,sci-dev-id = <10>; 63 ti,interrupt-ranges = <8 360 56>; 64 }; 65 66 main_pmx0: pinctrl@11c000 { 67 compatible = "pinctrl-single"; 68 /* Proxy 0 addressing */ 69 reg = <0x00 0x11c000 0x00 0x120>; 70 #pinctrl-cells = <1>; 71 pinctrl-single,register-width = <32>; 72 pinctrl-single,function-mask = <0xffffffff>; 73 }; 74 75 main_uart0: serial@2800000 { 76 compatible = "ti,j721e-uart", "ti,am654-uart"; 77 reg = <0x00 0x02800000 0x00 0x200>; 78 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 79 current-speed = <115200>; 80 clocks = <&k3_clks 146 0>; 81 clock-names = "fclk"; 82 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>; 83 status = "disabled"; 84 }; 85 86 main_uart1: serial@2810000 { 87 compatible = "ti,j721e-uart", "ti,am654-uart"; 88 reg = <0x00 0x02810000 0x00 0x200>; 89 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 90 current-speed = <115200>; 91 clocks = <&k3_clks 388 0>; 92 clock-names = "fclk"; 93 power-domains = <&k3_pds 388 TI_SCI_PD_EXCLUSIVE>; 94 status = "disabled"; 95 }; 96 97 main_uart2: serial@2820000 { 98 compatible = "ti,j721e-uart", "ti,am654-uart"; 99 reg = <0x00 0x02820000 0x00 0x200>; 100 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 101 current-speed = <115200>; 102 clocks = <&k3_clks 389 0>; 103 clock-names = "fclk"; 104 power-domains = <&k3_pds 389 TI_SCI_PD_EXCLUSIVE>; 105 status = "disabled"; 106 }; 107 108 main_uart3: serial@2830000 { 109 compatible = "ti,j721e-uart", "ti,am654-uart"; 110 reg = <0x00 0x02830000 0x00 0x200>; 111 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 112 current-speed = <115200>; 113 clocks = <&k3_clks 390 0>; 114 clock-names = "fclk"; 115 power-domains = <&k3_pds 390 TI_SCI_PD_EXCLUSIVE>; 116 status = "disabled"; 117 }; 118 119 main_uart4: serial@2840000 { 120 compatible = "ti,j721e-uart", "ti,am654-uart"; 121 reg = <0x00 0x02840000 0x00 0x200>; 122 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 123 current-speed = <115200>; 124 clocks = <&k3_clks 391 0>; 125 clock-names = "fclk"; 126 power-domains = <&k3_pds 391 TI_SCI_PD_EXCLUSIVE>; 127 status = "disabled"; 128 }; 129 130 main_uart5: serial@2850000 { 131 compatible = "ti,j721e-uart", "ti,am654-uart"; 132 reg = <0x00 0x02850000 0x00 0x200>; 133 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 134 current-speed = <115200>; 135 clocks = <&k3_clks 392 0>; 136 clock-names = "fclk"; 137 power-domains = <&k3_pds 392 TI_SCI_PD_EXCLUSIVE>; 138 status = "disabled"; 139 }; 140 141 main_uart6: serial@2860000 { 142 compatible = "ti,j721e-uart", "ti,am654-uart"; 143 reg = <0x00 0x02860000 0x00 0x200>; 144 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 145 current-speed = <115200>; 146 clocks = <&k3_clks 393 0>; 147 clock-names = "fclk"; 148 power-domains = <&k3_pds 393 TI_SCI_PD_EXCLUSIVE>; 149 status = "disabled"; 150 }; 151 152 main_uart7: serial@2870000 { 153 compatible = "ti,j721e-uart", "ti,am654-uart"; 154 reg = <0x00 0x02870000 0x00 0x200>; 155 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 156 current-speed = <115200>; 157 clocks = <&k3_clks 394 0>; 158 clock-names = "fclk"; 159 power-domains = <&k3_pds 394 TI_SCI_PD_EXCLUSIVE>; 160 status = "disabled"; 161 }; 162 163 main_uart8: serial@2880000 { 164 compatible = "ti,j721e-uart", "ti,am654-uart"; 165 reg = <0x00 0x02880000 0x00 0x200>; 166 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 167 current-speed = <115200>; 168 clocks = <&k3_clks 395 0>; 169 clock-names = "fclk"; 170 power-domains = <&k3_pds 395 TI_SCI_PD_EXCLUSIVE>; 171 status = "disabled"; 172 }; 173 174 main_uart9: serial@2890000 { 175 compatible = "ti,j721e-uart", "ti,am654-uart"; 176 reg = <0x00 0x02890000 0x00 0x200>; 177 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 178 current-speed = <115200>; 179 clocks = <&k3_clks 396 0>; 180 clock-names = "fclk"; 181 power-domains = <&k3_pds 396 TI_SCI_PD_EXCLUSIVE>; 182 status = "disabled"; 183 }; 184 185 main_gpio0: gpio@600000 { 186 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 187 reg = <0x00 0x00600000 0x00 0x100>; 188 gpio-controller; 189 #gpio-cells = <2>; 190 interrupt-parent = <&main_gpio_intr>; 191 interrupts = <145>, <146>, <147>, <148>, <149>; 192 interrupt-controller; 193 #interrupt-cells = <2>; 194 ti,ngpio = <66>; 195 ti,davinci-gpio-unbanked = <0>; 196 power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>; 197 clocks = <&k3_clks 163 0>; 198 clock-names = "gpio"; 199 status = "disabled"; 200 }; 201 202 main_gpio2: gpio@610000 { 203 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 204 reg = <0x00 0x00610000 0x00 0x100>; 205 gpio-controller; 206 #gpio-cells = <2>; 207 interrupt-parent = <&main_gpio_intr>; 208 interrupts = <154>, <155>, <156>, <157>, <158>; 209 interrupt-controller; 210 #interrupt-cells = <2>; 211 ti,ngpio = <66>; 212 ti,davinci-gpio-unbanked = <0>; 213 power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>; 214 clocks = <&k3_clks 164 0>; 215 clock-names = "gpio"; 216 status = "disabled"; 217 }; 218 219 main_gpio4: gpio@620000 { 220 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 221 reg = <0x00 0x00620000 0x00 0x100>; 222 gpio-controller; 223 #gpio-cells = <2>; 224 interrupt-parent = <&main_gpio_intr>; 225 interrupts = <163>, <164>, <165>, <166>, <167>; 226 interrupt-controller; 227 #interrupt-cells = <2>; 228 ti,ngpio = <66>; 229 ti,davinci-gpio-unbanked = <0>; 230 power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>; 231 clocks = <&k3_clks 165 0>; 232 clock-names = "gpio"; 233 status = "disabled"; 234 }; 235 236 main_gpio6: gpio@630000 { 237 compatible = "ti,j721e-gpio", "ti,keystone-gpio"; 238 reg = <0x00 0x00630000 0x00 0x100>; 239 gpio-controller; 240 #gpio-cells = <2>; 241 interrupt-parent = <&main_gpio_intr>; 242 interrupts = <172>, <173>, <174>, <175>, <176>; 243 interrupt-controller; 244 #interrupt-cells = <2>; 245 ti,ngpio = <66>; 246 ti,davinci-gpio-unbanked = <0>; 247 power-domains = <&k3_pds 166 TI_SCI_PD_EXCLUSIVE>; 248 clocks = <&k3_clks 166 0>; 249 clock-names = "gpio"; 250 status = "disabled"; 251 }; 252 253 main_i2c0: i2c@2000000 { 254 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 255 reg = <0x00 0x02000000 0x00 0x100>; 256 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 257 #address-cells = <1>; 258 #size-cells = <0>; 259 clocks = <&k3_clks 270 2>; 260 clock-names = "fck"; 261 power-domains = <&k3_pds 270 TI_SCI_PD_EXCLUSIVE>; 262 status = "disabled"; 263 }; 264 265 main_i2c1: i2c@2010000 { 266 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 267 reg = <0x00 0x02010000 0x00 0x100>; 268 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 269 #address-cells = <1>; 270 #size-cells = <0>; 271 clocks = <&k3_clks 271 2>; 272 clock-names = "fck"; 273 power-domains = <&k3_pds 271 TI_SCI_PD_EXCLUSIVE>; 274 status = "disabled"; 275 }; 276 277 main_i2c2: i2c@2020000 { 278 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 279 reg = <0x00 0x02020000 0x00 0x100>; 280 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>; 281 #address-cells = <1>; 282 #size-cells = <0>; 283 clocks = <&k3_clks 272 2>; 284 clock-names = "fck"; 285 power-domains = <&k3_pds 272 TI_SCI_PD_EXCLUSIVE>; 286 status = "disabled"; 287 }; 288 289 main_i2c3: i2c@2030000 { 290 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 291 reg = <0x00 0x02030000 0x00 0x100>; 292 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 293 #address-cells = <1>; 294 #size-cells = <0>; 295 clocks = <&k3_clks 273 2>; 296 clock-names = "fck"; 297 power-domains = <&k3_pds 273 TI_SCI_PD_EXCLUSIVE>; 298 status = "disabled"; 299 }; 300 301 main_i2c4: i2c@2040000 { 302 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 303 reg = <0x00 0x02040000 0x00 0x100>; 304 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 305 #address-cells = <1>; 306 #size-cells = <0>; 307 clocks = <&k3_clks 274 2>; 308 clock-names = "fck"; 309 power-domains = <&k3_pds 274 TI_SCI_PD_EXCLUSIVE>; 310 status = "disabled"; 311 }; 312 313 main_i2c5: i2c@2050000 { 314 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 315 reg = <0x00 0x02050000 0x00 0x100>; 316 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 317 #address-cells = <1>; 318 #size-cells = <0>; 319 clocks = <&k3_clks 275 2>; 320 clock-names = "fck"; 321 power-domains = <&k3_pds 275 TI_SCI_PD_EXCLUSIVE>; 322 status = "disabled"; 323 }; 324 325 main_i2c6: i2c@2060000 { 326 compatible = "ti,j721e-i2c", "ti,omap4-i2c"; 327 reg = <0x00 0x02060000 0x00 0x100>; 328 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 329 #address-cells = <1>; 330 #size-cells = <0>; 331 clocks = <&k3_clks 276 2>; 332 clock-names = "fck"; 333 power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; 334 status = "disabled"; 335 }; 336 337 main_sdhci0: mmc@4f80000 { 338 compatible = "ti,j721e-sdhci-8bit"; 339 reg = <0x00 0x04f80000 0x00 0x1000>, 340 <0x00 0x04f88000 0x00 0x400>; 341 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 342 power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>; 343 clocks = <&k3_clks 140 1>, <&k3_clks 140 2>; 344 clock-names = "clk_ahb", "clk_xin"; 345 assigned-clocks = <&k3_clks 140 2>; 346 assigned-clock-parents = <&k3_clks 140 3>; 347 bus-width = <8>; 348 ti,otap-del-sel-legacy = <0x0>; 349 ti,otap-del-sel-mmc-hs = <0x0>; 350 ti,otap-del-sel-ddr52 = <0x6>; 351 ti,otap-del-sel-hs200 = <0x8>; 352 ti,otap-del-sel-hs400 = <0x5>; 353 ti,itap-del-sel-legacy = <0x10>; 354 ti,itap-del-sel-mmc-hs = <0xa>; 355 ti,strobe-sel = <0x77>; 356 ti,clkbuf-sel = <0x7>; 357 ti,trm-icp = <0x8>; 358 mmc-ddr-1_8v; 359 mmc-hs200-1_8v; 360 mmc-hs400-1_8v; 361 dma-coherent; 362 no-1-8-v; 363 status = "disabled"; 364 }; 365 366 main_sdhci1: mmc@4fb0000 { 367 compatible = "ti,j721e-sdhci-4bit"; 368 reg = <0x00 0x04fb0000 0x00 0x1000>, 369 <0x00 0x04fb8000 0x00 0x400>; 370 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 371 power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>; 372 clocks = <&k3_clks 141 3>, <&k3_clks 141 4>; 373 clock-names = "clk_ahb", "clk_xin"; 374 assigned-clocks = <&k3_clks 141 4>; 375 assigned-clock-parents = <&k3_clks 141 5>; 376 bus-width = <4>; 377 ti,otap-del-sel-legacy = <0x0>; 378 ti,otap-del-sel-sd-hs = <0x0>; 379 ti,otap-del-sel-sdr12 = <0xf>; 380 ti,otap-del-sel-sdr25 = <0xf>; 381 ti,otap-del-sel-sdr50 = <0xc>; 382 ti,otap-del-sel-sdr104 = <0x5>; 383 ti,otap-del-sel-ddr50 = <0xc>; 384 ti,itap-del-sel-legacy = <0x0>; 385 ti,itap-del-sel-sd-hs = <0x0>; 386 ti,itap-del-sel-sdr12 = <0x0>; 387 ti,itap-del-sel-sdr25 = <0x0>; 388 ti,clkbuf-sel = <0x7>; 389 ti,trm-icp = <0x8>; 390 dma-coherent; 391 sdhci-caps-mask = <0x00000003 0x00000000>; 392 no-1-8-v; 393 status = "disabled"; 394 }; 395 396 main_navss: bus@30000000 { 397 compatible = "simple-bus"; 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; 401 dma-coherent; 402 dma-ranges; 403 404 main_navss_intr: interrupt-controller@310e0000 { 405 compatible = "ti,sci-intr"; 406 reg = <0x00 0x310e0000 0x00 0x4000>; 407 ti,intr-trigger-type = <4>; 408 interrupt-controller; 409 interrupt-parent = <&gic500>; 410 #interrupt-cells = <1>; 411 ti,sci = <&sms>; 412 ti,sci-dev-id = <283>; 413 ti,interrupt-ranges = <0 64 64>, 414 <64 448 64>, 415 <128 672 64>; 416 }; 417 418 main_udmass_inta: msi-controller@33d00000 { 419 compatible = "ti,sci-inta"; 420 reg = <0x00 0x33d00000 0x00 0x100000>; 421 interrupt-controller; 422 #interrupt-cells = <0>; 423 interrupt-parent = <&main_navss_intr>; 424 msi-controller; 425 ti,sci = <&sms>; 426 ti,sci-dev-id = <321>; 427 ti,interrupt-ranges = <0 0 256>; 428 }; 429 430 secure_proxy_main: mailbox@32c00000 { 431 compatible = "ti,am654-secure-proxy"; 432 #mbox-cells = <1>; 433 reg-names = "target_data", "rt", "scfg"; 434 reg = <0x00 0x32c00000 0x00 0x100000>, 435 <0x00 0x32400000 0x00 0x100000>, 436 <0x00 0x32800000 0x00 0x100000>; 437 interrupt-names = "rx_011"; 438 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 439 }; 440 441 hwspinlock: hwlock@30e00000 { 442 compatible = "ti,am654-hwspinlock"; 443 reg = <0x00 0x30e00000 0x00 0x1000>; 444 #hwlock-cells = <1>; 445 }; 446 447 mailbox0_cluster0: mailbox@31f80000 { 448 compatible = "ti,am654-mailbox"; 449 reg = <0x00 0x31f80000 0x00 0x200>; 450 #mbox-cells = <1>; 451 ti,mbox-num-users = <4>; 452 ti,mbox-num-fifos = <16>; 453 interrupt-parent = <&main_navss_intr>; 454 status = "disabled"; 455 }; 456 457 mailbox0_cluster1: mailbox@31f81000 { 458 compatible = "ti,am654-mailbox"; 459 reg = <0x00 0x31f81000 0x00 0x200>; 460 #mbox-cells = <1>; 461 ti,mbox-num-users = <4>; 462 ti,mbox-num-fifos = <16>; 463 interrupt-parent = <&main_navss_intr>; 464 status = "disabled"; 465 }; 466 467 mailbox0_cluster2: mailbox@31f82000 { 468 compatible = "ti,am654-mailbox"; 469 reg = <0x00 0x31f82000 0x00 0x200>; 470 #mbox-cells = <1>; 471 ti,mbox-num-users = <4>; 472 ti,mbox-num-fifos = <16>; 473 interrupt-parent = <&main_navss_intr>; 474 status = "disabled"; 475 }; 476 477 mailbox0_cluster3: mailbox@31f83000 { 478 compatible = "ti,am654-mailbox"; 479 reg = <0x00 0x31f83000 0x00 0x200>; 480 #mbox-cells = <1>; 481 ti,mbox-num-users = <4>; 482 ti,mbox-num-fifos = <16>; 483 interrupt-parent = <&main_navss_intr>; 484 status = "disabled"; 485 }; 486 487 mailbox0_cluster4: mailbox@31f84000 { 488 compatible = "ti,am654-mailbox"; 489 reg = <0x00 0x31f84000 0x00 0x200>; 490 #mbox-cells = <1>; 491 ti,mbox-num-users = <4>; 492 ti,mbox-num-fifos = <16>; 493 interrupt-parent = <&main_navss_intr>; 494 status = "disabled"; 495 }; 496 497 mailbox0_cluster5: mailbox@31f85000 { 498 compatible = "ti,am654-mailbox"; 499 reg = <0x00 0x31f85000 0x00 0x200>; 500 #mbox-cells = <1>; 501 ti,mbox-num-users = <4>; 502 ti,mbox-num-fifos = <16>; 503 interrupt-parent = <&main_navss_intr>; 504 status = "disabled"; 505 }; 506 507 mailbox0_cluster6: mailbox@31f86000 { 508 compatible = "ti,am654-mailbox"; 509 reg = <0x00 0x31f86000 0x00 0x200>; 510 #mbox-cells = <1>; 511 ti,mbox-num-users = <4>; 512 ti,mbox-num-fifos = <16>; 513 interrupt-parent = <&main_navss_intr>; 514 status = "disabled"; 515 }; 516 517 mailbox0_cluster7: mailbox@31f87000 { 518 compatible = "ti,am654-mailbox"; 519 reg = <0x00 0x31f87000 0x00 0x200>; 520 #mbox-cells = <1>; 521 ti,mbox-num-users = <4>; 522 ti,mbox-num-fifos = <16>; 523 interrupt-parent = <&main_navss_intr>; 524 status = "disabled"; 525 }; 526 527 mailbox0_cluster8: mailbox@31f88000 { 528 compatible = "ti,am654-mailbox"; 529 reg = <0x00 0x31f88000 0x00 0x200>; 530 #mbox-cells = <1>; 531 ti,mbox-num-users = <4>; 532 ti,mbox-num-fifos = <16>; 533 interrupt-parent = <&main_navss_intr>; 534 status = "disabled"; 535 }; 536 537 mailbox0_cluster9: mailbox@31f89000 { 538 compatible = "ti,am654-mailbox"; 539 reg = <0x00 0x31f89000 0x00 0x200>; 540 #mbox-cells = <1>; 541 ti,mbox-num-users = <4>; 542 ti,mbox-num-fifos = <16>; 543 interrupt-parent = <&main_navss_intr>; 544 status = "disabled"; 545 }; 546 547 mailbox0_cluster10: mailbox@31f8a000 { 548 compatible = "ti,am654-mailbox"; 549 reg = <0x00 0x31f8a000 0x00 0x200>; 550 #mbox-cells = <1>; 551 ti,mbox-num-users = <4>; 552 ti,mbox-num-fifos = <16>; 553 interrupt-parent = <&main_navss_intr>; 554 status = "disabled"; 555 }; 556 557 mailbox0_cluster11: mailbox@31f8b000 { 558 compatible = "ti,am654-mailbox"; 559 reg = <0x00 0x31f8b000 0x00 0x200>; 560 #mbox-cells = <1>; 561 ti,mbox-num-users = <4>; 562 ti,mbox-num-fifos = <16>; 563 interrupt-parent = <&main_navss_intr>; 564 status = "disabled"; 565 }; 566 567 mailbox1_cluster0: mailbox@31f90000 { 568 compatible = "ti,am654-mailbox"; 569 reg = <0x00 0x31f90000 0x00 0x200>; 570 #mbox-cells = <1>; 571 ti,mbox-num-users = <4>; 572 ti,mbox-num-fifos = <16>; 573 interrupt-parent = <&main_navss_intr>; 574 status = "disabled"; 575 }; 576 577 mailbox1_cluster1: mailbox@31f91000 { 578 compatible = "ti,am654-mailbox"; 579 reg = <0x00 0x31f91000 0x00 0x200>; 580 #mbox-cells = <1>; 581 ti,mbox-num-users = <4>; 582 ti,mbox-num-fifos = <16>; 583 interrupt-parent = <&main_navss_intr>; 584 status = "disabled"; 585 }; 586 587 mailbox1_cluster2: mailbox@31f92000 { 588 compatible = "ti,am654-mailbox"; 589 reg = <0x00 0x31f92000 0x00 0x200>; 590 #mbox-cells = <1>; 591 ti,mbox-num-users = <4>; 592 ti,mbox-num-fifos = <16>; 593 interrupt-parent = <&main_navss_intr>; 594 status = "disabled"; 595 }; 596 597 mailbox1_cluster3: mailbox@31f93000 { 598 compatible = "ti,am654-mailbox"; 599 reg = <0x00 0x31f93000 0x00 0x200>; 600 #mbox-cells = <1>; 601 ti,mbox-num-users = <4>; 602 ti,mbox-num-fifos = <16>; 603 interrupt-parent = <&main_navss_intr>; 604 status = "disabled"; 605 }; 606 607 mailbox1_cluster4: mailbox@31f94000 { 608 compatible = "ti,am654-mailbox"; 609 reg = <0x00 0x31f94000 0x00 0x200>; 610 #mbox-cells = <1>; 611 ti,mbox-num-users = <4>; 612 ti,mbox-num-fifos = <16>; 613 interrupt-parent = <&main_navss_intr>; 614 status = "disabled"; 615 }; 616 617 mailbox1_cluster5: mailbox@31f95000 { 618 compatible = "ti,am654-mailbox"; 619 reg = <0x00 0x31f95000 0x00 0x200>; 620 #mbox-cells = <1>; 621 ti,mbox-num-users = <4>; 622 ti,mbox-num-fifos = <16>; 623 interrupt-parent = <&main_navss_intr>; 624 status = "disabled"; 625 }; 626 627 mailbox1_cluster6: mailbox@31f96000 { 628 compatible = "ti,am654-mailbox"; 629 reg = <0x00 0x31f96000 0x00 0x200>; 630 #mbox-cells = <1>; 631 ti,mbox-num-users = <4>; 632 ti,mbox-num-fifos = <16>; 633 interrupt-parent = <&main_navss_intr>; 634 status = "disabled"; 635 }; 636 637 mailbox1_cluster7: mailbox@31f97000 { 638 compatible = "ti,am654-mailbox"; 639 reg = <0x00 0x31f97000 0x00 0x200>; 640 #mbox-cells = <1>; 641 ti,mbox-num-users = <4>; 642 ti,mbox-num-fifos = <16>; 643 interrupt-parent = <&main_navss_intr>; 644 status = "disabled"; 645 }; 646 647 mailbox1_cluster8: mailbox@31f98000 { 648 compatible = "ti,am654-mailbox"; 649 reg = <0x00 0x31f98000 0x00 0x200>; 650 #mbox-cells = <1>; 651 ti,mbox-num-users = <4>; 652 ti,mbox-num-fifos = <16>; 653 interrupt-parent = <&main_navss_intr>; 654 status = "disabled"; 655 }; 656 657 mailbox1_cluster9: mailbox@31f99000 { 658 compatible = "ti,am654-mailbox"; 659 reg = <0x00 0x31f99000 0x00 0x200>; 660 #mbox-cells = <1>; 661 ti,mbox-num-users = <4>; 662 ti,mbox-num-fifos = <16>; 663 interrupt-parent = <&main_navss_intr>; 664 status = "disabled"; 665 }; 666 667 mailbox1_cluster10: mailbox@31f9a000 { 668 compatible = "ti,am654-mailbox"; 669 reg = <0x00 0x31f9a000 0x00 0x200>; 670 #mbox-cells = <1>; 671 ti,mbox-num-users = <4>; 672 ti,mbox-num-fifos = <16>; 673 interrupt-parent = <&main_navss_intr>; 674 status = "disabled"; 675 }; 676 677 mailbox1_cluster11: mailbox@31f9b000 { 678 compatible = "ti,am654-mailbox"; 679 reg = <0x00 0x31f9b000 0x00 0x200>; 680 #mbox-cells = <1>; 681 ti,mbox-num-users = <4>; 682 ti,mbox-num-fifos = <16>; 683 interrupt-parent = <&main_navss_intr>; 684 status = "disabled"; 685 }; 686 687 main_ringacc: ringacc@3c000000 { 688 compatible = "ti,am654-navss-ringacc"; 689 reg = <0x00 0x3c000000 0x00 0x400000>, 690 <0x00 0x38000000 0x00 0x400000>, 691 <0x00 0x31120000 0x00 0x100>, 692 <0x00 0x33000000 0x00 0x40000>; 693 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target"; 694 ti,num-rings = <1024>; 695 ti,sci-rm-range-gp-rings = <0x1>; 696 ti,sci = <&sms>; 697 ti,sci-dev-id = <315>; 698 msi-parent = <&main_udmass_inta>; 699 }; 700 701 main_udmap: dma-controller@31150000 { 702 compatible = "ti,j721e-navss-main-udmap"; 703 reg = <0x00 0x31150000 0x00 0x100>, 704 <0x00 0x34000000 0x00 0x80000>, 705 <0x00 0x35000000 0x00 0x200000>; 706 reg-names = "gcfg", "rchanrt", "tchanrt"; 707 msi-parent = <&main_udmass_inta>; 708 #dma-cells = <1>; 709 710 ti,sci = <&sms>; 711 ti,sci-dev-id = <319>; 712 ti,ringacc = <&main_ringacc>; 713 714 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */ 715 <0x0f>, /* TX_HCHAN */ 716 <0x10>; /* TX_UHCHAN */ 717 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */ 718 <0x0b>, /* RX_HCHAN */ 719 <0x0c>; /* RX_UHCHAN */ 720 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */ 721 }; 722 723 cpts@310d0000 { 724 compatible = "ti,j721e-cpts"; 725 reg = <0x00 0x310d0000 0x00 0x400>; 726 reg-names = "cpts"; 727 clocks = <&k3_clks 282 0>; 728 clock-names = "cpts"; 729 assigned-clocks = <&k3_clks 62 3>; /* CPTS_RFT_CLK */ 730 assigned-clock-parents = <&k3_clks 62 5>; /* MAIN_0_HSDIV6_CLK */ 731 interrupts-extended = <&main_navss_intr 391>; 732 interrupt-names = "cpts"; 733 ti,cpts-periodic-outputs = <6>; 734 ti,cpts-ext-ts-inputs = <8>; 735 }; 736 }; 737 738 main_mcan0: can@2701000 { 739 compatible = "bosch,m_can"; 740 reg = <0x00 0x02701000 0x00 0x200>, 741 <0x00 0x02708000 0x00 0x8000>; 742 reg-names = "m_can", "message_ram"; 743 power-domains = <&k3_pds 245 TI_SCI_PD_EXCLUSIVE>; 744 clocks = <&k3_clks 245 6>, <&k3_clks 245 1>; 745 clock-names = "hclk", "cclk"; 746 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 748 interrupt-names = "int0", "int1"; 749 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 750 status = "disabled"; 751 }; 752 753 main_mcan1: can@2711000 { 754 compatible = "bosch,m_can"; 755 reg = <0x00 0x02711000 0x00 0x200>, 756 <0x00 0x02718000 0x00 0x8000>; 757 reg-names = "m_can", "message_ram"; 758 power-domains = <&k3_pds 246 TI_SCI_PD_EXCLUSIVE>; 759 clocks = <&k3_clks 246 6>, <&k3_clks 246 1>; 760 clock-names = "hclk", "cclk"; 761 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 763 interrupt-names = "int0", "int1"; 764 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 765 status = "disabled"; 766 }; 767 768 main_mcan2: can@2721000 { 769 compatible = "bosch,m_can"; 770 reg = <0x00 0x02721000 0x00 0x200>, 771 <0x00 0x02728000 0x00 0x8000>; 772 reg-names = "m_can", "message_ram"; 773 power-domains = <&k3_pds 247 TI_SCI_PD_EXCLUSIVE>; 774 clocks = <&k3_clks 247 6>, <&k3_clks 247 1>; 775 clock-names = "hclk", "cclk"; 776 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 778 interrupt-names = "int0", "int1"; 779 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 780 status = "disabled"; 781 }; 782 783 main_mcan3: can@2731000 { 784 compatible = "bosch,m_can"; 785 reg = <0x00 0x02731000 0x00 0x200>, 786 <0x00 0x02738000 0x00 0x8000>; 787 reg-names = "m_can", "message_ram"; 788 power-domains = <&k3_pds 248 TI_SCI_PD_EXCLUSIVE>; 789 clocks = <&k3_clks 248 6>, <&k3_clks 248 1>; 790 clock-names = "hclk", "cclk"; 791 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 793 interrupt-names = "int0", "int1"; 794 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 795 status = "disabled"; 796 }; 797 798 main_mcan4: can@2741000 { 799 compatible = "bosch,m_can"; 800 reg = <0x00 0x02741000 0x00 0x200>, 801 <0x00 0x02748000 0x00 0x8000>; 802 reg-names = "m_can", "message_ram"; 803 power-domains = <&k3_pds 249 TI_SCI_PD_EXCLUSIVE>; 804 clocks = <&k3_clks 249 6>, <&k3_clks 249 1>; 805 clock-names = "hclk", "cclk"; 806 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 807 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 808 interrupt-names = "int0", "int1"; 809 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 810 status = "disabled"; 811 }; 812 813 main_mcan5: can@2751000 { 814 compatible = "bosch,m_can"; 815 reg = <0x00 0x02751000 0x00 0x200>, 816 <0x00 0x02758000 0x00 0x8000>; 817 reg-names = "m_can", "message_ram"; 818 power-domains = <&k3_pds 250 TI_SCI_PD_EXCLUSIVE>; 819 clocks = <&k3_clks 250 6>, <&k3_clks 250 1>; 820 clock-names = "hclk", "cclk"; 821 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 823 interrupt-names = "int0", "int1"; 824 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 825 status = "disabled"; 826 }; 827 828 main_mcan6: can@2761000 { 829 compatible = "bosch,m_can"; 830 reg = <0x00 0x02761000 0x00 0x200>, 831 <0x00 0x02768000 0x00 0x8000>; 832 reg-names = "m_can", "message_ram"; 833 power-domains = <&k3_pds 251 TI_SCI_PD_EXCLUSIVE>; 834 clocks = <&k3_clks 251 6>, <&k3_clks 251 1>; 835 clock-names = "hclk", "cclk"; 836 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 838 interrupt-names = "int0", "int1"; 839 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 840 status = "disabled"; 841 }; 842 843 main_mcan7: can@2771000 { 844 compatible = "bosch,m_can"; 845 reg = <0x00 0x02771000 0x00 0x200>, 846 <0x00 0x02778000 0x00 0x8000>; 847 reg-names = "m_can", "message_ram"; 848 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>; 849 clocks = <&k3_clks 252 6>, <&k3_clks 252 1>; 850 clock-names = "hclk", "cclk"; 851 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 852 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 853 interrupt-names = "int0", "int1"; 854 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 855 status = "disabled"; 856 }; 857 858 main_mcan8: can@2781000 { 859 compatible = "bosch,m_can"; 860 reg = <0x00 0x02781000 0x00 0x200>, 861 <0x00 0x02788000 0x00 0x8000>; 862 reg-names = "m_can", "message_ram"; 863 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>; 864 clocks = <&k3_clks 253 6>, <&k3_clks 253 1>; 865 clock-names = "hclk", "cclk"; 866 interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>; 868 interrupt-names = "int0", "int1"; 869 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 870 status = "disabled"; 871 }; 872 873 main_mcan9: can@2791000 { 874 compatible = "bosch,m_can"; 875 reg = <0x00 0x02791000 0x00 0x200>, 876 <0x00 0x02798000 0x00 0x8000>; 877 reg-names = "m_can", "message_ram"; 878 power-domains = <&k3_pds 254 TI_SCI_PD_EXCLUSIVE>; 879 clocks = <&k3_clks 254 6>, <&k3_clks 254 1>; 880 clock-names = "hclk", "cclk"; 881 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>; 883 interrupt-names = "int0", "int1"; 884 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 885 status = "disabled"; 886 }; 887 888 main_mcan10: can@27a1000 { 889 compatible = "bosch,m_can"; 890 reg = <0x00 0x027a1000 0x00 0x200>, 891 <0x00 0x027a8000 0x00 0x8000>; 892 reg-names = "m_can", "message_ram"; 893 power-domains = <&k3_pds 255 TI_SCI_PD_EXCLUSIVE>; 894 clocks = <&k3_clks 255 6>, <&k3_clks 255 1>; 895 clock-names = "hclk", "cclk"; 896 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 898 interrupt-names = "int0", "int1"; 899 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 900 status = "disabled"; 901 }; 902 903 main_mcan11: can@27b1000 { 904 compatible = "bosch,m_can"; 905 reg = <0x00 0x027b1000 0x00 0x200>, 906 <0x00 0x027b8000 0x00 0x8000>; 907 reg-names = "m_can", "message_ram"; 908 power-domains = <&k3_pds 256 TI_SCI_PD_EXCLUSIVE>; 909 clocks = <&k3_clks 256 6>, <&k3_clks 256 1>; 910 clock-names = "hclk", "cclk"; 911 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 913 interrupt-names = "int0", "int1"; 914 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 915 status = "disabled"; 916 }; 917 918 main_mcan12: can@27c1000 { 919 compatible = "bosch,m_can"; 920 reg = <0x00 0x027c1000 0x00 0x200>, 921 <0x00 0x027c8000 0x00 0x8000>; 922 reg-names = "m_can", "message_ram"; 923 power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>; 924 clocks = <&k3_clks 257 6>, <&k3_clks 257 1>; 925 clock-names = "hclk", "cclk"; 926 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 928 interrupt-names = "int0", "int1"; 929 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 930 status = "disabled"; 931 }; 932 933 main_mcan13: can@27d1000 { 934 compatible = "bosch,m_can"; 935 reg = <0x00 0x027d1000 0x00 0x200>, 936 <0x00 0x027d8000 0x00 0x8000>; 937 reg-names = "m_can", "message_ram"; 938 power-domains = <&k3_pds 258 TI_SCI_PD_EXCLUSIVE>; 939 clocks = <&k3_clks 258 6>, <&k3_clks 258 1>; 940 clock-names = "hclk", "cclk"; 941 interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>; 943 interrupt-names = "int0", "int1"; 944 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 945 status = "disabled"; 946 }; 947 948 main_mcan14: can@2681000 { 949 compatible = "bosch,m_can"; 950 reg = <0x00 0x02681000 0x00 0x200>, 951 <0x00 0x02688000 0x00 0x8000>; 952 reg-names = "m_can", "message_ram"; 953 power-domains = <&k3_pds 259 TI_SCI_PD_EXCLUSIVE>; 954 clocks = <&k3_clks 259 6>, <&k3_clks 259 1>; 955 clock-names = "hclk", "cclk"; 956 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>; 958 interrupt-names = "int0", "int1"; 959 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 960 status = "disabled"; 961 }; 962 963 main_mcan15: can@2691000 { 964 compatible = "bosch,m_can"; 965 reg = <0x00 0x02691000 0x00 0x200>, 966 <0x00 0x02698000 0x00 0x8000>; 967 reg-names = "m_can", "message_ram"; 968 power-domains = <&k3_pds 260 TI_SCI_PD_EXCLUSIVE>; 969 clocks = <&k3_clks 260 6>, <&k3_clks 260 1>; 970 clock-names = "hclk", "cclk"; 971 interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 972 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>; 973 interrupt-names = "int0", "int1"; 974 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 975 status = "disabled"; 976 }; 977 978 main_mcan16: can@26a1000 { 979 compatible = "bosch,m_can"; 980 reg = <0x00 0x026a1000 0x00 0x200>, 981 <0x00 0x026a8000 0x00 0x8000>; 982 reg-names = "m_can", "message_ram"; 983 power-domains = <&k3_pds 261 TI_SCI_PD_EXCLUSIVE>; 984 clocks = <&k3_clks 261 6>, <&k3_clks 261 1>; 985 clock-names = "hclk", "cclk"; 986 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 988 interrupt-names = "int0", "int1"; 989 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 990 status = "disabled"; 991 }; 992 993 main_mcan17: can@26b1000 { 994 compatible = "bosch,m_can"; 995 reg = <0x00 0x026b1000 0x00 0x200>, 996 <0x00 0x026b8000 0x00 0x8000>; 997 reg-names = "m_can", "message_ram"; 998 power-domains = <&k3_pds 262 TI_SCI_PD_EXCLUSIVE>; 999 clocks = <&k3_clks 262 6>, <&k3_clks 262 1>; 1000 clock-names = "hclk", "cclk"; 1001 interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>; 1003 interrupt-names = "int0", "int1"; 1004 bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>; 1005 status = "disabled"; 1006 }; 1007}; 1008