1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "k3-j784s4.dtsi" 13 14/ { 15 compatible = "ti,j784s4-evm", "ti,j784s4"; 16 model = "Texas Instruments J784S4 EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 aliases { 23 serial0 = &wkup_uart0; 24 serial1 = &mcu_uart0; 25 serial2 = &main_uart8; 26 mmc0 = &main_sdhci0; 27 mmc1 = &main_sdhci1; 28 i2c0 = &wkup_i2c0; 29 i2c3 = &main_i2c0; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 /* 32G RAM */ 35 reg = <0x00 0x80000000 0x00 0x80000000>, 36 <0x08 0x80000000 0x07 0x80000000>; 37 }; 38 39 reserved_memory: reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 secure_ddr: optee@9e800000 { 45 reg = <0x00 0x9e800000 0x00 0x01800000>; 46 no-map; 47 }; 48 49 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 50 compatible = "shared-dma-pool"; 51 reg = <0x00 0xa0000000 0x00 0x100000>; 52 no-map; 53 }; 54 55 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 56 compatible = "shared-dma-pool"; 57 reg = <0x00 0xa0100000 0x00 0xf00000>; 58 no-map; 59 }; 60 61 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 62 compatible = "shared-dma-pool"; 63 reg = <0x00 0xa1000000 0x00 0x100000>; 64 no-map; 65 }; 66 67 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0xa1100000 0x00 0xf00000>; 70 no-map; 71 }; 72 73 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x00 0xa2000000 0x00 0x100000>; 76 no-map; 77 }; 78 79 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 80 compatible = "shared-dma-pool"; 81 reg = <0x00 0xa2100000 0x00 0xf00000>; 82 no-map; 83 }; 84 85 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 86 compatible = "shared-dma-pool"; 87 reg = <0x00 0xa3000000 0x00 0x100000>; 88 no-map; 89 }; 90 91 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 92 compatible = "shared-dma-pool"; 93 reg = <0x00 0xa3100000 0x00 0xf00000>; 94 no-map; 95 }; 96 97 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 98 compatible = "shared-dma-pool"; 99 reg = <0x00 0xa4000000 0x00 0x100000>; 100 no-map; 101 }; 102 103 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 104 compatible = "shared-dma-pool"; 105 reg = <0x00 0xa4100000 0x00 0xf00000>; 106 no-map; 107 }; 108 109 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 110 compatible = "shared-dma-pool"; 111 reg = <0x00 0xa5000000 0x00 0x100000>; 112 no-map; 113 }; 114 115 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 116 compatible = "shared-dma-pool"; 117 reg = <0x00 0xa5100000 0x00 0xf00000>; 118 no-map; 119 }; 120 121 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 122 compatible = "shared-dma-pool"; 123 reg = <0x00 0xa6000000 0x00 0x100000>; 124 no-map; 125 }; 126 127 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 128 compatible = "shared-dma-pool"; 129 reg = <0x00 0xa6100000 0x00 0xf00000>; 130 no-map; 131 }; 132 133 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 134 compatible = "shared-dma-pool"; 135 reg = <0x00 0xa7000000 0x00 0x100000>; 136 no-map; 137 }; 138 139 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 140 compatible = "shared-dma-pool"; 141 reg = <0x00 0xa7100000 0x00 0xf00000>; 142 no-map; 143 }; 144 145 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 146 compatible = "shared-dma-pool"; 147 reg = <0x00 0xa8000000 0x00 0x100000>; 148 no-map; 149 }; 150 151 c71_0_memory_region: c71-memory@a8100000 { 152 compatible = "shared-dma-pool"; 153 reg = <0x00 0xa8100000 0x00 0xf00000>; 154 no-map; 155 }; 156 157 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 158 compatible = "shared-dma-pool"; 159 reg = <0x00 0xa9000000 0x00 0x100000>; 160 no-map; 161 }; 162 163 c71_1_memory_region: c71-memory@a9100000 { 164 compatible = "shared-dma-pool"; 165 reg = <0x00 0xa9100000 0x00 0xf00000>; 166 no-map; 167 }; 168 169 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 170 compatible = "shared-dma-pool"; 171 reg = <0x00 0xaa000000 0x00 0x100000>; 172 no-map; 173 }; 174 175 c71_2_memory_region: c71-memory@aa100000 { 176 compatible = "shared-dma-pool"; 177 reg = <0x00 0xaa100000 0x00 0xf00000>; 178 no-map; 179 }; 180 181 c71_3_dma_memory_region: c71-dma-memory@ab000000 { 182 compatible = "shared-dma-pool"; 183 reg = <0x00 0xab000000 0x00 0x100000>; 184 no-map; 185 }; 186 187 c71_3_memory_region: c71-memory@ab100000 { 188 compatible = "shared-dma-pool"; 189 reg = <0x00 0xab100000 0x00 0xf00000>; 190 no-map; 191 }; 192 }; 193 194 evm_12v0: regulator-evm12v0 { 195 /* main supply */ 196 compatible = "regulator-fixed"; 197 regulator-name = "evm_12v0"; 198 regulator-min-microvolt = <12000000>; 199 regulator-max-microvolt = <12000000>; 200 regulator-always-on; 201 regulator-boot-on; 202 }; 203 204 vsys_3v3: regulator-vsys3v3 { 205 /* Output of LM5140 */ 206 compatible = "regulator-fixed"; 207 regulator-name = "vsys_3v3"; 208 regulator-min-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>; 210 vin-supply = <&evm_12v0>; 211 regulator-always-on; 212 regulator-boot-on; 213 }; 214 215 vsys_5v0: regulator-vsys5v0 { 216 /* Output of LM5140 */ 217 compatible = "regulator-fixed"; 218 regulator-name = "vsys_5v0"; 219 regulator-min-microvolt = <5000000>; 220 regulator-max-microvolt = <5000000>; 221 vin-supply = <&evm_12v0>; 222 regulator-always-on; 223 regulator-boot-on; 224 }; 225 226 vdd_mmc1: regulator-sd { 227 /* Output of TPS22918 */ 228 compatible = "regulator-fixed"; 229 regulator-name = "vdd_mmc1"; 230 regulator-min-microvolt = <3300000>; 231 regulator-max-microvolt = <3300000>; 232 regulator-boot-on; 233 enable-active-high; 234 vin-supply = <&vsys_3v3>; 235 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 236 }; 237 238 vdd_sd_dv: regulator-TLV71033 { 239 /* Output of TLV71033 */ 240 compatible = "regulator-gpio"; 241 regulator-name = "tlv71033"; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&vdd_sd_dv_pins_default>; 244 regulator-min-microvolt = <1800000>; 245 regulator-max-microvolt = <3300000>; 246 regulator-boot-on; 247 vin-supply = <&vsys_5v0>; 248 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 249 states = <1800000 0x0>, 250 <3300000 0x1>; 251 }; 252}; 253 254&main_pmx0 { 255 bootph-all; 256 main_uart8_pins_default: main-uart8-default-pins { 257 bootph-all; 258 pinctrl-single,pins = < 259 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 260 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 261 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 262 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 263 >; 264 }; 265 266 main_i2c0_pins_default: main-i2c0-default-pins { 267 pinctrl-single,pins = < 268 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 269 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 270 >; 271 }; 272 273 main_mmc1_pins_default: main-mmc1-default-pins { 274 bootph-all; 275 pinctrl-single,pins = < 276 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 277 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 278 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 279 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 280 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 281 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 282 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 283 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 284 >; 285 }; 286 287 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 288 pinctrl-single,pins = < 289 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 290 >; 291 }; 292}; 293 294&wkup_pmx2 { 295 bootph-all; 296 wkup_uart0_pins_default: wkup-uart0-default-pins { 297 bootph-all; 298 pinctrl-single,pins = < 299 J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ 300 J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ 301 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 302 J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ 303 >; 304 }; 305 306 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 307 bootph-all; 308 pinctrl-single,pins = < 309 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 310 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 311 >; 312 }; 313 314 mcu_uart0_pins_default: mcu-uart0-default-pins { 315 bootph-all; 316 pinctrl-single,pins = < 317 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 318 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ 319 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 320 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 321 >; 322 }; 323 324 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 325 pinctrl-single,pins = < 326 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 327 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 328 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 329 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 330 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 331 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 332 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 333 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 334 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 335 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 336 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 337 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 338 >; 339 }; 340 341 mcu_mdio_pins_default: mcu-mdio-default-pins { 342 pinctrl-single,pins = < 343 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 344 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 345 >; 346 }; 347 348 mcu_adc0_pins_default: mcu-adc0-default-pins { 349 pinctrl-single,pins = < 350 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 351 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 352 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 353 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 354 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 355 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 356 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 357 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 358 >; 359 }; 360 361 mcu_adc1_pins_default: mcu-adc1-default-pins { 362 pinctrl-single,pins = < 363 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 364 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 365 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 366 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 367 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 368 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 369 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 370 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 371 >; 372 }; 373}; 374 375&wkup_pmx0 { 376 bootph-all; 377 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 378 bootph-all; 379 pinctrl-single,pins = < 380 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 381 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 382 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 383 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 384 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 385 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 386 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 387 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 388 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 389 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 390 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 391 >; 392 }; 393}; 394 395&wkup_pmx1 { 396 bootph-all; 397 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 398 bootph-all; 399 pinctrl-single,pins = < 400 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 401 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 402 >; 403 }; 404 405 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 406 bootph-all; 407 pinctrl-single,pins = < 408 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 409 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 410 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 411 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 412 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 413 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 414 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 415 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 416 >; 417 }; 418}; 419 420&wkup_uart0 { 421 /* Firmware usage */ 422 status = "reserved"; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&wkup_uart0_pins_default>; 425}; 426 427&wkup_i2c0 { 428 bootph-all; 429 status = "okay"; 430 pinctrl-names = "default"; 431 pinctrl-0 = <&wkup_i2c0_pins_default>; 432 clock-frequency = <400000>; 433 434 eeprom@50 { 435 /* CAV24C256WE-GT3 */ 436 compatible = "atmel,24c256"; 437 reg = <0x50>; 438 }; 439}; 440 441&mcu_uart0 { 442 bootph-all; 443 status = "okay"; 444 pinctrl-names = "default"; 445 pinctrl-0 = <&mcu_uart0_pins_default>; 446}; 447 448&main_uart8 { 449 bootph-all; 450 status = "okay"; 451 pinctrl-names = "default"; 452 pinctrl-0 = <&main_uart8_pins_default>; 453}; 454 455&ufs_wrapper { 456 status = "okay"; 457}; 458 459&fss { 460 bootph-all; 461 status = "okay"; 462}; 463 464&ospi0 { 465 bootph-all; 466 status = "okay"; 467 pinctrl-names = "default"; 468 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 469 470 flash@0 { 471 bootph-all; 472 compatible = "jedec,spi-nor"; 473 reg = <0x0>; 474 spi-tx-bus-width = <8>; 475 spi-rx-bus-width = <8>; 476 spi-max-frequency = <25000000>; 477 cdns,tshsl-ns = <60>; 478 cdns,tsd2d-ns = <60>; 479 cdns,tchsh-ns = <60>; 480 cdns,tslch-ns = <60>; 481 cdns,read-delay = <4>; 482 483 partitions { 484 compatible = "fixed-partitions"; 485 #address-cells = <1>; 486 #size-cells = <1>; 487 488 partition@0 { 489 label = "ospi.tiboot3"; 490 reg = <0x0 0x80000>; 491 }; 492 493 partition@80000 { 494 label = "ospi.tispl"; 495 reg = <0x80000 0x200000>; 496 }; 497 498 partition@280000 { 499 label = "ospi.u-boot"; 500 reg = <0x280000 0x400000>; 501 }; 502 503 partition@680000 { 504 label = "ospi.env"; 505 reg = <0x680000 0x40000>; 506 }; 507 508 partition@6c0000 { 509 label = "ospi.env.backup"; 510 reg = <0x6c0000 0x40000>; 511 }; 512 513 partition@800000 { 514 label = "ospi.rootfs"; 515 reg = <0x800000 0x37c0000>; 516 }; 517 518 partition@3fc0000 { 519 bootph-all; 520 label = "ospi.phypattern"; 521 reg = <0x3fc0000 0x40000>; 522 }; 523 }; 524 }; 525}; 526 527&ospi1 { 528 bootph-all; 529 status = "okay"; 530 pinctrl-names = "default"; 531 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 532 533 flash@0 { 534 bootph-all; 535 compatible = "jedec,spi-nor"; 536 reg = <0x0>; 537 spi-tx-bus-width = <1>; 538 spi-rx-bus-width = <4>; 539 spi-max-frequency = <40000000>; 540 cdns,tshsl-ns = <60>; 541 cdns,tsd2d-ns = <60>; 542 cdns,tchsh-ns = <60>; 543 cdns,tslch-ns = <60>; 544 cdns,read-delay = <2>; 545 546 partitions { 547 compatible = "fixed-partitions"; 548 #address-cells = <1>; 549 #size-cells = <1>; 550 551 partition@0 { 552 label = "qspi.tiboot3"; 553 reg = <0x0 0x80000>; 554 }; 555 556 partition@80000 { 557 label = "qspi.tispl"; 558 reg = <0x80000 0x200000>; 559 }; 560 561 partition@280000 { 562 label = "qspi.u-boot"; 563 reg = <0x280000 0x400000>; 564 }; 565 566 partition@680000 { 567 label = "qspi.env"; 568 reg = <0x680000 0x40000>; 569 }; 570 571 partition@6c0000 { 572 label = "qspi.env.backup"; 573 reg = <0x6c0000 0x40000>; 574 }; 575 576 partition@800000 { 577 label = "qspi.rootfs"; 578 reg = <0x800000 0x37c0000>; 579 }; 580 581 partition@3fc0000 { 582 bootph-all; 583 label = "qspi.phypattern"; 584 reg = <0x3fc0000 0x40000>; 585 }; 586 }; 587 588 }; 589}; 590 591&main_i2c0 { 592 status = "okay"; 593 pinctrl-names = "default"; 594 pinctrl-0 = <&main_i2c0_pins_default>; 595 596 clock-frequency = <400000>; 597 598 exp1: gpio@20 { 599 compatible = "ti,tca6416"; 600 reg = <0x20>; 601 gpio-controller; 602 #gpio-cells = <2>; 603 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 604 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 605 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 606 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 607 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 608 }; 609 610 exp2: gpio@22 { 611 compatible = "ti,tca6424"; 612 reg = <0x22>; 613 gpio-controller; 614 #gpio-cells = <2>; 615 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 616 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 617 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 618 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 619 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 620 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 621 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 622 "USER_INPUT1", "USER_LED1", "USER_LED2"; 623 }; 624}; 625 626&main_sdhci0 { 627 bootph-all; 628 /* eMMC */ 629 status = "okay"; 630 non-removable; 631 ti,driver-strength-ohm = <50>; 632 disable-wp; 633}; 634 635&main_sdhci1 { 636 bootph-all; 637 /* SD card */ 638 status = "okay"; 639 pinctrl-0 = <&main_mmc1_pins_default>; 640 pinctrl-names = "default"; 641 disable-wp; 642 vmmc-supply = <&vdd_mmc1>; 643 vqmmc-supply = <&vdd_sd_dv>; 644}; 645 646&main_gpio0 { 647 status = "okay"; 648}; 649 650&mcu_cpsw { 651 status = "okay"; 652 pinctrl-names = "default"; 653 pinctrl-0 = <&mcu_cpsw_pins_default>; 654}; 655 656&davinci_mdio { 657 pinctrl-names = "default"; 658 pinctrl-0 = <&mcu_mdio_pins_default>; 659 660 mcu_phy0: ethernet-phy@0 { 661 reg = <0>; 662 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 663 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 664 ti,min-output-impedance; 665 }; 666}; 667 668&mcu_cpsw_port1 { 669 status = "okay"; 670 phy-mode = "rgmii-rxid"; 671 phy-handle = <&mcu_phy0>; 672}; 673 674&mailbox0_cluster0 { 675 status = "okay"; 676 interrupts = <436>; 677 678 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 679 ti,mbox-rx = <0 0 0>; 680 ti,mbox-tx = <1 0 0>; 681 }; 682 683 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 684 ti,mbox-rx = <2 0 0>; 685 ti,mbox-tx = <3 0 0>; 686 }; 687}; 688 689&mailbox0_cluster1 { 690 status = "okay"; 691 interrupts = <432>; 692 693 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 694 ti,mbox-rx = <0 0 0>; 695 ti,mbox-tx = <1 0 0>; 696 }; 697 698 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 699 ti,mbox-rx = <2 0 0>; 700 ti,mbox-tx = <3 0 0>; 701 }; 702}; 703 704&mailbox0_cluster2 { 705 status = "okay"; 706 interrupts = <428>; 707 708 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 709 ti,mbox-rx = <0 0 0>; 710 ti,mbox-tx = <1 0 0>; 711 }; 712 713 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 714 ti,mbox-rx = <2 0 0>; 715 ti,mbox-tx = <3 0 0>; 716 }; 717}; 718 719&mailbox0_cluster3 { 720 status = "okay"; 721 interrupts = <424>; 722 723 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 724 ti,mbox-rx = <0 0 0>; 725 ti,mbox-tx = <1 0 0>; 726 }; 727 728 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 729 ti,mbox-rx = <2 0 0>; 730 ti,mbox-tx = <3 0 0>; 731 }; 732}; 733 734&mailbox0_cluster4 { 735 status = "okay"; 736 interrupts = <420>; 737 738 mbox_c71_0: mbox-c71-0 { 739 ti,mbox-rx = <0 0 0>; 740 ti,mbox-tx = <1 0 0>; 741 }; 742 743 mbox_c71_1: mbox-c71-1 { 744 ti,mbox-rx = <2 0 0>; 745 ti,mbox-tx = <3 0 0>; 746 }; 747}; 748 749&mailbox0_cluster5 { 750 status = "okay"; 751 interrupts = <416>; 752 753 mbox_c71_2: mbox-c71-2 { 754 ti,mbox-rx = <0 0 0>; 755 ti,mbox-tx = <1 0 0>; 756 }; 757 758 mbox_c71_3: mbox-c71-3 { 759 ti,mbox-rx = <2 0 0>; 760 ti,mbox-tx = <3 0 0>; 761 }; 762}; 763 764&mcu_r5fss0_core0 { 765 status = "okay"; 766 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 767 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 768 <&mcu_r5fss0_core0_memory_region>; 769}; 770 771&mcu_r5fss0_core1 { 772 status = "okay"; 773 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 774 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 775 <&mcu_r5fss0_core1_memory_region>; 776}; 777 778&main_r5fss0_core0 { 779 status = "okay"; 780 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 781 memory-region = <&main_r5fss0_core0_dma_memory_region>, 782 <&main_r5fss0_core0_memory_region>; 783}; 784 785&main_r5fss0_core1 { 786 status = "okay"; 787 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 788 memory-region = <&main_r5fss0_core1_dma_memory_region>, 789 <&main_r5fss0_core1_memory_region>; 790}; 791 792&main_r5fss1_core0 { 793 status = "okay"; 794 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 795 memory-region = <&main_r5fss1_core0_dma_memory_region>, 796 <&main_r5fss1_core0_memory_region>; 797}; 798 799&main_r5fss1_core1 { 800 status = "okay"; 801 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 802 memory-region = <&main_r5fss1_core1_dma_memory_region>, 803 <&main_r5fss1_core1_memory_region>; 804}; 805 806&main_r5fss2_core0 { 807 status = "okay"; 808 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 809 memory-region = <&main_r5fss2_core0_dma_memory_region>, 810 <&main_r5fss2_core0_memory_region>; 811}; 812 813&main_r5fss2_core1 { 814 status = "okay"; 815 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 816 memory-region = <&main_r5fss2_core1_dma_memory_region>, 817 <&main_r5fss2_core1_memory_region>; 818}; 819 820&c71_0 { 821 status = "okay"; 822 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 823 memory-region = <&c71_0_dma_memory_region>, 824 <&c71_0_memory_region>; 825}; 826 827&c71_1 { 828 status = "okay"; 829 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 830 memory-region = <&c71_1_dma_memory_region>, 831 <&c71_1_memory_region>; 832}; 833 834&c71_2 { 835 status = "okay"; 836 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 837 memory-region = <&c71_2_dma_memory_region>, 838 <&c71_2_memory_region>; 839}; 840 841&c71_3 { 842 status = "okay"; 843 mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 844 memory-region = <&c71_3_dma_memory_region>, 845 <&c71_3_memory_region>; 846}; 847 848&tscadc0 { 849 pinctrl-0 = <&mcu_adc0_pins_default>; 850 pinctrl-names = "default"; 851 status = "okay"; 852 adc { 853 ti,adc-channels = <0 1 2 3 4 5 6 7>; 854 }; 855}; 856 857&tscadc1 { 858 pinctrl-0 = <&mcu_adc1_pins_default>; 859 pinctrl-names = "default"; 860 status = "okay"; 861 adc { 862 ti,adc-channels = <0 1 2 3 4 5 6 7>; 863 }; 864}; 865