1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics: https://www.ti.com/lit/zip/sprr458 6 */ 7 8/dts-v1/; 9 10#include <dt-bindings/net/ti-dp83867.h> 11#include <dt-bindings/gpio/gpio.h> 12#include "k3-j784s4.dtsi" 13 14/ { 15 compatible = "ti,j784s4-evm", "ti,j784s4"; 16 model = "Texas Instruments J784S4 EVM"; 17 18 chosen { 19 stdout-path = "serial2:115200n8"; 20 }; 21 22 aliases { 23 serial0 = &wkup_uart0; 24 serial1 = &mcu_uart0; 25 serial2 = &main_uart8; 26 mmc0 = &main_sdhci0; 27 mmc1 = &main_sdhci1; 28 i2c0 = &wkup_i2c0; 29 i2c3 = &main_i2c0; 30 }; 31 32 memory@80000000 { 33 device_type = "memory"; 34 /* 32G RAM */ 35 reg = <0x00 0x80000000 0x00 0x80000000>, 36 <0x08 0x80000000 0x07 0x80000000>; 37 }; 38 39 reserved_memory: reserved-memory { 40 #address-cells = <2>; 41 #size-cells = <2>; 42 ranges; 43 44 secure_ddr: optee@9e800000 { 45 reg = <0x00 0x9e800000 0x00 0x01800000>; 46 no-map; 47 }; 48 49 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 50 compatible = "shared-dma-pool"; 51 reg = <0x00 0xa0000000 0x00 0x100000>; 52 no-map; 53 }; 54 55 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 56 compatible = "shared-dma-pool"; 57 reg = <0x00 0xa0100000 0x00 0xf00000>; 58 no-map; 59 }; 60 61 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 62 compatible = "shared-dma-pool"; 63 reg = <0x00 0xa1000000 0x00 0x100000>; 64 no-map; 65 }; 66 67 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 68 compatible = "shared-dma-pool"; 69 reg = <0x00 0xa1100000 0x00 0xf00000>; 70 no-map; 71 }; 72 73 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 74 compatible = "shared-dma-pool"; 75 reg = <0x00 0xa2000000 0x00 0x100000>; 76 no-map; 77 }; 78 79 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 80 compatible = "shared-dma-pool"; 81 reg = <0x00 0xa2100000 0x00 0xf00000>; 82 no-map; 83 }; 84 85 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 86 compatible = "shared-dma-pool"; 87 reg = <0x00 0xa3000000 0x00 0x100000>; 88 no-map; 89 }; 90 91 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 92 compatible = "shared-dma-pool"; 93 reg = <0x00 0xa3100000 0x00 0xf00000>; 94 no-map; 95 }; 96 97 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 98 compatible = "shared-dma-pool"; 99 reg = <0x00 0xa4000000 0x00 0x100000>; 100 no-map; 101 }; 102 103 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 104 compatible = "shared-dma-pool"; 105 reg = <0x00 0xa4100000 0x00 0xf00000>; 106 no-map; 107 }; 108 109 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 110 compatible = "shared-dma-pool"; 111 reg = <0x00 0xa5000000 0x00 0x100000>; 112 no-map; 113 }; 114 115 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 116 compatible = "shared-dma-pool"; 117 reg = <0x00 0xa5100000 0x00 0xf00000>; 118 no-map; 119 }; 120 121 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 122 compatible = "shared-dma-pool"; 123 reg = <0x00 0xa6000000 0x00 0x100000>; 124 no-map; 125 }; 126 127 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 128 compatible = "shared-dma-pool"; 129 reg = <0x00 0xa6100000 0x00 0xf00000>; 130 no-map; 131 }; 132 133 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 134 compatible = "shared-dma-pool"; 135 reg = <0x00 0xa7000000 0x00 0x100000>; 136 no-map; 137 }; 138 139 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 140 compatible = "shared-dma-pool"; 141 reg = <0x00 0xa7100000 0x00 0xf00000>; 142 no-map; 143 }; 144 145 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 146 compatible = "shared-dma-pool"; 147 reg = <0x00 0xa8000000 0x00 0x100000>; 148 no-map; 149 }; 150 151 c71_0_memory_region: c71-memory@a8100000 { 152 compatible = "shared-dma-pool"; 153 reg = <0x00 0xa8100000 0x00 0xf00000>; 154 no-map; 155 }; 156 157 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 158 compatible = "shared-dma-pool"; 159 reg = <0x00 0xa9000000 0x00 0x100000>; 160 no-map; 161 }; 162 163 c71_1_memory_region: c71-memory@a9100000 { 164 compatible = "shared-dma-pool"; 165 reg = <0x00 0xa9100000 0x00 0xf00000>; 166 no-map; 167 }; 168 169 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 170 compatible = "shared-dma-pool"; 171 reg = <0x00 0xaa000000 0x00 0x100000>; 172 no-map; 173 }; 174 175 c71_2_memory_region: c71-memory@aa100000 { 176 compatible = "shared-dma-pool"; 177 reg = <0x00 0xaa100000 0x00 0xf00000>; 178 no-map; 179 }; 180 181 c71_3_dma_memory_region: c71-dma-memory@ab000000 { 182 compatible = "shared-dma-pool"; 183 reg = <0x00 0xab000000 0x00 0x100000>; 184 no-map; 185 }; 186 187 c71_3_memory_region: c71-memory@ab100000 { 188 compatible = "shared-dma-pool"; 189 reg = <0x00 0xab100000 0x00 0xf00000>; 190 no-map; 191 }; 192 }; 193 194 evm_12v0: regulator-evm12v0 { 195 /* main supply */ 196 compatible = "regulator-fixed"; 197 regulator-name = "evm_12v0"; 198 regulator-min-microvolt = <12000000>; 199 regulator-max-microvolt = <12000000>; 200 regulator-always-on; 201 regulator-boot-on; 202 }; 203 204 vsys_3v3: regulator-vsys3v3 { 205 /* Output of LM5140 */ 206 compatible = "regulator-fixed"; 207 regulator-name = "vsys_3v3"; 208 regulator-min-microvolt = <3300000>; 209 regulator-max-microvolt = <3300000>; 210 vin-supply = <&evm_12v0>; 211 regulator-always-on; 212 regulator-boot-on; 213 }; 214 215 vsys_5v0: regulator-vsys5v0 { 216 /* Output of LM5140 */ 217 compatible = "regulator-fixed"; 218 regulator-name = "vsys_5v0"; 219 regulator-min-microvolt = <5000000>; 220 regulator-max-microvolt = <5000000>; 221 vin-supply = <&evm_12v0>; 222 regulator-always-on; 223 regulator-boot-on; 224 }; 225 226 vdd_mmc1: regulator-sd { 227 /* Output of TPS22918 */ 228 compatible = "regulator-fixed"; 229 regulator-name = "vdd_mmc1"; 230 regulator-min-microvolt = <3300000>; 231 regulator-max-microvolt = <3300000>; 232 regulator-boot-on; 233 enable-active-high; 234 vin-supply = <&vsys_3v3>; 235 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 236 }; 237 238 vdd_sd_dv: regulator-TLV71033 { 239 /* Output of TLV71033 */ 240 compatible = "regulator-gpio"; 241 regulator-name = "tlv71033"; 242 pinctrl-names = "default"; 243 pinctrl-0 = <&vdd_sd_dv_pins_default>; 244 regulator-min-microvolt = <1800000>; 245 regulator-max-microvolt = <3300000>; 246 regulator-boot-on; 247 vin-supply = <&vsys_5v0>; 248 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 249 states = <1800000 0x0>, 250 <3300000 0x1>; 251 }; 252}; 253 254&main_pmx0 { 255 bootph-all; 256 main_uart8_pins_default: main-uart8-default-pins { 257 bootph-all; 258 pinctrl-single,pins = < 259 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 260 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 261 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 262 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 263 >; 264 }; 265 266 main_i2c0_pins_default: main-i2c0-default-pins { 267 pinctrl-single,pins = < 268 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 269 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 270 >; 271 }; 272 273 main_mmc1_pins_default: main-mmc1-default-pins { 274 bootph-all; 275 pinctrl-single,pins = < 276 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 277 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 278 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 279 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 280 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 281 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 282 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 283 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 284 >; 285 }; 286 287 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 288 pinctrl-single,pins = < 289 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 290 >; 291 }; 292}; 293 294&wkup_pmx2 { 295 bootph-all; 296 wkup_uart0_pins_default: wkup-uart0-default-pins { 297 bootph-all; 298 pinctrl-single,pins = < 299 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 300 J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ 301 >; 302 }; 303 304 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 305 bootph-all; 306 pinctrl-single,pins = < 307 J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 308 J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 309 >; 310 }; 311 312 mcu_uart0_pins_default: mcu-uart0-default-pins { 313 bootph-all; 314 pinctrl-single,pins = < 315 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 316 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ 317 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 318 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 319 >; 320 }; 321 322 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 323 pinctrl-single,pins = < 324 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 325 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 326 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 327 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 328 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 329 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 330 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 331 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 332 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 333 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 334 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 335 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 336 >; 337 }; 338 339 mcu_mdio_pins_default: mcu-mdio-default-pins { 340 pinctrl-single,pins = < 341 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 342 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 343 >; 344 }; 345 346 mcu_adc0_pins_default: mcu-adc0-default-pins { 347 pinctrl-single,pins = < 348 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 349 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 350 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 351 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 352 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 353 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 354 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 355 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 356 >; 357 }; 358 359 mcu_adc1_pins_default: mcu-adc1-default-pins { 360 pinctrl-single,pins = < 361 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 362 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 363 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 364 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 365 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 366 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 367 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 368 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 369 >; 370 }; 371}; 372 373&wkup_pmx0 { 374 bootph-all; 375 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 376 bootph-all; 377 pinctrl-single,pins = < 378 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 379 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 380 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 381 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 382 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 383 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 384 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 385 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 386 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 387 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 388 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 389 >; 390 }; 391}; 392 393&wkup_pmx1 { 394 bootph-all; 395 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 396 bootph-all; 397 pinctrl-single,pins = < 398 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 399 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 400 >; 401 }; 402 403 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 404 bootph-all; 405 pinctrl-single,pins = < 406 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 407 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 408 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 409 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 410 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 411 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 412 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 413 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 414 >; 415 }; 416}; 417 418&wkup_uart0 { 419 /* Firmware usage */ 420 status = "reserved"; 421 pinctrl-names = "default"; 422 pinctrl-0 = <&wkup_uart0_pins_default>; 423}; 424 425&wkup_i2c0 { 426 bootph-all; 427 status = "okay"; 428 pinctrl-names = "default"; 429 pinctrl-0 = <&wkup_i2c0_pins_default>; 430 clock-frequency = <400000>; 431 432 eeprom@50 { 433 /* CAV24C256WE-GT3 */ 434 compatible = "atmel,24c256"; 435 reg = <0x50>; 436 }; 437}; 438 439&mcu_uart0 { 440 bootph-all; 441 status = "okay"; 442 pinctrl-names = "default"; 443 pinctrl-0 = <&mcu_uart0_pins_default>; 444}; 445 446&main_uart8 { 447 bootph-all; 448 status = "okay"; 449 pinctrl-names = "default"; 450 pinctrl-0 = <&main_uart8_pins_default>; 451}; 452 453&ufs_wrapper { 454 status = "okay"; 455}; 456 457&fss { 458 bootph-all; 459 status = "okay"; 460}; 461 462&ospi0 { 463 bootph-all; 464 status = "okay"; 465 pinctrl-names = "default"; 466 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 467 468 flash@0 { 469 bootph-all; 470 compatible = "jedec,spi-nor"; 471 reg = <0x0>; 472 spi-tx-bus-width = <8>; 473 spi-rx-bus-width = <8>; 474 spi-max-frequency = <25000000>; 475 cdns,tshsl-ns = <60>; 476 cdns,tsd2d-ns = <60>; 477 cdns,tchsh-ns = <60>; 478 cdns,tslch-ns = <60>; 479 cdns,read-delay = <4>; 480 481 partitions { 482 compatible = "fixed-partitions"; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 486 partition@0 { 487 label = "ospi.tiboot3"; 488 reg = <0x0 0x80000>; 489 }; 490 491 partition@80000 { 492 label = "ospi.tispl"; 493 reg = <0x80000 0x200000>; 494 }; 495 496 partition@280000 { 497 label = "ospi.u-boot"; 498 reg = <0x280000 0x400000>; 499 }; 500 501 partition@680000 { 502 label = "ospi.env"; 503 reg = <0x680000 0x40000>; 504 }; 505 506 partition@6c0000 { 507 label = "ospi.env.backup"; 508 reg = <0x6c0000 0x40000>; 509 }; 510 511 partition@800000 { 512 label = "ospi.rootfs"; 513 reg = <0x800000 0x37c0000>; 514 }; 515 516 partition@3fc0000 { 517 bootph-all; 518 label = "ospi.phypattern"; 519 reg = <0x3fc0000 0x40000>; 520 }; 521 }; 522 }; 523}; 524 525&ospi1 { 526 bootph-all; 527 status = "okay"; 528 pinctrl-names = "default"; 529 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 530 531 flash@0 { 532 bootph-all; 533 compatible = "jedec,spi-nor"; 534 reg = <0x0>; 535 spi-tx-bus-width = <1>; 536 spi-rx-bus-width = <4>; 537 spi-max-frequency = <40000000>; 538 cdns,tshsl-ns = <60>; 539 cdns,tsd2d-ns = <60>; 540 cdns,tchsh-ns = <60>; 541 cdns,tslch-ns = <60>; 542 cdns,read-delay = <2>; 543 544 partitions { 545 compatible = "fixed-partitions"; 546 #address-cells = <1>; 547 #size-cells = <1>; 548 549 partition@0 { 550 label = "qspi.tiboot3"; 551 reg = <0x0 0x80000>; 552 }; 553 554 partition@80000 { 555 label = "qspi.tispl"; 556 reg = <0x80000 0x200000>; 557 }; 558 559 partition@280000 { 560 label = "qspi.u-boot"; 561 reg = <0x280000 0x400000>; 562 }; 563 564 partition@680000 { 565 label = "qspi.env"; 566 reg = <0x680000 0x40000>; 567 }; 568 569 partition@6c0000 { 570 label = "qspi.env.backup"; 571 reg = <0x6c0000 0x40000>; 572 }; 573 574 partition@800000 { 575 label = "qspi.rootfs"; 576 reg = <0x800000 0x37c0000>; 577 }; 578 579 partition@3fc0000 { 580 bootph-all; 581 label = "qspi.phypattern"; 582 reg = <0x3fc0000 0x40000>; 583 }; 584 }; 585 586 }; 587}; 588 589&main_i2c0 { 590 status = "okay"; 591 pinctrl-names = "default"; 592 pinctrl-0 = <&main_i2c0_pins_default>; 593 594 clock-frequency = <400000>; 595 596 exp1: gpio@20 { 597 compatible = "ti,tca6416"; 598 reg = <0x20>; 599 gpio-controller; 600 #gpio-cells = <2>; 601 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 602 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 603 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 604 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 605 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 606 }; 607 608 exp2: gpio@22 { 609 compatible = "ti,tca6424"; 610 reg = <0x22>; 611 gpio-controller; 612 #gpio-cells = <2>; 613 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 614 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 615 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 616 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 617 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 618 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 619 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 620 "USER_INPUT1", "USER_LED1", "USER_LED2"; 621 }; 622}; 623 624&main_sdhci0 { 625 bootph-all; 626 /* eMMC */ 627 status = "okay"; 628 non-removable; 629 ti,driver-strength-ohm = <50>; 630 disable-wp; 631}; 632 633&main_sdhci1 { 634 bootph-all; 635 /* SD card */ 636 status = "okay"; 637 pinctrl-0 = <&main_mmc1_pins_default>; 638 pinctrl-names = "default"; 639 disable-wp; 640 vmmc-supply = <&vdd_mmc1>; 641 vqmmc-supply = <&vdd_sd_dv>; 642}; 643 644&main_gpio0 { 645 status = "okay"; 646}; 647 648&mcu_cpsw { 649 status = "okay"; 650 pinctrl-names = "default"; 651 pinctrl-0 = <&mcu_cpsw_pins_default>; 652}; 653 654&davinci_mdio { 655 pinctrl-names = "default"; 656 pinctrl-0 = <&mcu_mdio_pins_default>; 657 658 mcu_phy0: ethernet-phy@0 { 659 reg = <0>; 660 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 661 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 662 ti,min-output-impedance; 663 }; 664}; 665 666&mcu_cpsw_port1 { 667 status = "okay"; 668 phy-mode = "rgmii-rxid"; 669 phy-handle = <&mcu_phy0>; 670}; 671 672&mailbox0_cluster0 { 673 status = "okay"; 674 interrupts = <436>; 675 676 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 677 ti,mbox-rx = <0 0 0>; 678 ti,mbox-tx = <1 0 0>; 679 }; 680 681 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 682 ti,mbox-rx = <2 0 0>; 683 ti,mbox-tx = <3 0 0>; 684 }; 685}; 686 687&mailbox0_cluster1 { 688 status = "okay"; 689 interrupts = <432>; 690 691 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 692 ti,mbox-rx = <0 0 0>; 693 ti,mbox-tx = <1 0 0>; 694 }; 695 696 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 697 ti,mbox-rx = <2 0 0>; 698 ti,mbox-tx = <3 0 0>; 699 }; 700}; 701 702&mailbox0_cluster2 { 703 status = "okay"; 704 interrupts = <428>; 705 706 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 707 ti,mbox-rx = <0 0 0>; 708 ti,mbox-tx = <1 0 0>; 709 }; 710 711 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 712 ti,mbox-rx = <2 0 0>; 713 ti,mbox-tx = <3 0 0>; 714 }; 715}; 716 717&mailbox0_cluster3 { 718 status = "okay"; 719 interrupts = <424>; 720 721 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 722 ti,mbox-rx = <0 0 0>; 723 ti,mbox-tx = <1 0 0>; 724 }; 725 726 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 727 ti,mbox-rx = <2 0 0>; 728 ti,mbox-tx = <3 0 0>; 729 }; 730}; 731 732&mailbox0_cluster4 { 733 status = "okay"; 734 interrupts = <420>; 735 736 mbox_c71_0: mbox-c71-0 { 737 ti,mbox-rx = <0 0 0>; 738 ti,mbox-tx = <1 0 0>; 739 }; 740 741 mbox_c71_1: mbox-c71-1 { 742 ti,mbox-rx = <2 0 0>; 743 ti,mbox-tx = <3 0 0>; 744 }; 745}; 746 747&mailbox0_cluster5 { 748 status = "okay"; 749 interrupts = <416>; 750 751 mbox_c71_2: mbox-c71-2 { 752 ti,mbox-rx = <0 0 0>; 753 ti,mbox-tx = <1 0 0>; 754 }; 755 756 mbox_c71_3: mbox-c71-3 { 757 ti,mbox-rx = <2 0 0>; 758 ti,mbox-tx = <3 0 0>; 759 }; 760}; 761 762&mcu_r5fss0_core0 { 763 status = "okay"; 764 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 765 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 766 <&mcu_r5fss0_core0_memory_region>; 767}; 768 769&mcu_r5fss0_core1 { 770 status = "okay"; 771 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 772 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 773 <&mcu_r5fss0_core1_memory_region>; 774}; 775 776&main_r5fss0_core0 { 777 status = "okay"; 778 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 779 memory-region = <&main_r5fss0_core0_dma_memory_region>, 780 <&main_r5fss0_core0_memory_region>; 781}; 782 783&main_r5fss0_core1 { 784 status = "okay"; 785 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 786 memory-region = <&main_r5fss0_core1_dma_memory_region>, 787 <&main_r5fss0_core1_memory_region>; 788}; 789 790&main_r5fss1_core0 { 791 status = "okay"; 792 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 793 memory-region = <&main_r5fss1_core0_dma_memory_region>, 794 <&main_r5fss1_core0_memory_region>; 795}; 796 797&main_r5fss1_core1 { 798 status = "okay"; 799 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 800 memory-region = <&main_r5fss1_core1_dma_memory_region>, 801 <&main_r5fss1_core1_memory_region>; 802}; 803 804&main_r5fss2_core0 { 805 status = "okay"; 806 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 807 memory-region = <&main_r5fss2_core0_dma_memory_region>, 808 <&main_r5fss2_core0_memory_region>; 809}; 810 811&main_r5fss2_core1 { 812 status = "okay"; 813 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 814 memory-region = <&main_r5fss2_core1_dma_memory_region>, 815 <&main_r5fss2_core1_memory_region>; 816}; 817 818&c71_0 { 819 status = "okay"; 820 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 821 memory-region = <&c71_0_dma_memory_region>, 822 <&c71_0_memory_region>; 823}; 824 825&c71_1 { 826 status = "okay"; 827 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 828 memory-region = <&c71_1_dma_memory_region>, 829 <&c71_1_memory_region>; 830}; 831 832&c71_2 { 833 status = "okay"; 834 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 835 memory-region = <&c71_2_dma_memory_region>, 836 <&c71_2_memory_region>; 837}; 838 839&c71_3 { 840 status = "okay"; 841 mboxes = <&mailbox0_cluster5 &mbox_c71_3>; 842 memory-region = <&c71_3_dma_memory_region>, 843 <&c71_3_memory_region>; 844}; 845 846&tscadc0 { 847 pinctrl-0 = <&mcu_adc0_pins_default>; 848 pinctrl-names = "default"; 849 status = "okay"; 850 adc { 851 ti,adc-channels = <0 1 2 3 4 5 6 7>; 852 }; 853}; 854 855&tscadc1 { 856 pinctrl-0 = <&mcu_adc1_pins_default>; 857 pinctrl-names = "default"; 858 status = "okay"; 859 adc { 860 ti,adc-channels = <0 1 2 3 4 5 6 7>; 861 }; 862}; 863