1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for J721S2 SoC Family 4 * 5 * TRM (SPRUJ28 – NOVEMBER 2021) : http://www.ti.com/lit/pdf/spruj28 6 * 7 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 8 * 9 */ 10 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/k3.h> 14#include <dt-bindings/soc/ti,sci_pm_domain.h> 15 16/ { 17 18 model = "Texas Instruments K3 J721S2 SoC"; 19 compatible = "ti,j721s2"; 20 interrupt-parent = <&gic500>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 serial0 = &wkup_uart0; 26 serial1 = &mcu_uart0; 27 serial2 = &main_uart0; 28 serial3 = &main_uart1; 29 serial4 = &main_uart2; 30 serial5 = &main_uart3; 31 serial6 = &main_uart4; 32 serial7 = &main_uart5; 33 serial8 = &main_uart6; 34 serial9 = &main_uart7; 35 serial10 = &main_uart8; 36 serial11 = &main_uart9; 37 mmc0 = &main_sdhci0; 38 mmc1 = &main_sdhci1; 39 can0 = &main_mcan16; 40 can1 = &mcu_mcan0; 41 can2 = &mcu_mcan1; 42 can3 = &main_mcan3; 43 can4 = &main_mcan5; 44 }; 45 46 chosen { }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 cpu-map { 52 cluster0: cluster0 { 53 core0 { 54 cpu = <&cpu0>; 55 }; 56 57 core1 { 58 cpu = <&cpu1>; 59 }; 60 }; 61 }; 62 63 cpu0: cpu@0 { 64 compatible = "arm,cortex-a72"; 65 reg = <0x000>; 66 device_type = "cpu"; 67 enable-method = "psci"; 68 i-cache-size = <0xc000>; 69 i-cache-line-size = <64>; 70 i-cache-sets = <256>; 71 d-cache-size = <0x8000>; 72 d-cache-line-size = <64>; 73 d-cache-sets = <256>; 74 next-level-cache = <&L2_0>; 75 }; 76 77 cpu1: cpu@1 { 78 compatible = "arm,cortex-a72"; 79 reg = <0x001>; 80 device_type = "cpu"; 81 enable-method = "psci"; 82 i-cache-size = <0xc000>; 83 i-cache-line-size = <64>; 84 i-cache-sets = <256>; 85 d-cache-size = <0x8000>; 86 d-cache-line-size = <64>; 87 d-cache-sets = <256>; 88 next-level-cache = <&L2_0>; 89 }; 90 }; 91 92 L2_0: l2-cache0 { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-size = <0x100000>; 96 cache-line-size = <64>; 97 cache-sets = <1024>; 98 next-level-cache = <&msmc_l3>; 99 }; 100 101 msmc_l3: l3-cache0 { 102 compatible = "cache"; 103 cache-level = <3>; 104 }; 105 106 firmware { 107 optee { 108 compatible = "linaro,optee-tz"; 109 method = "smc"; 110 }; 111 112 psci: psci { 113 compatible = "arm,psci-1.0"; 114 method = "smc"; 115 }; 116 }; 117 118 a72_timer0: timer-cl0-cpu0 { 119 compatible = "arm,armv8-timer"; 120 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 121 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 122 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 123 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 124 125 }; 126 127 pmu: pmu { 128 compatible = "arm,cortex-a72-pmu"; 129 /* Recommendation from GIC500 TRM Table A.3 */ 130 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 131 }; 132 133 cbass_main: bus@100000 { 134 compatible = "simple-bus"; 135 #address-cells = <2>; 136 #size-cells = <2>; 137 ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */ 138 <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */ 139 <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */ 140 <0x00 0x0d800000 0x00 0x0d800000 0x00 0x00800000>, /* PCIe Core*/ 141 <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */ 142 <0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */ 143 <0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */ 144 <0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */ 145 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */ 146 <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */ 147 <0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */ 148 149 /* MCUSS_WKUP Range */ 150 <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, 151 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, 152 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, 153 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, 154 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, 155 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, 156 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, 157 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, 158 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, 159 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, 160 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, 161 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, 162 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; 163 164 cbass_mcu_wakeup: bus@28380000 { 165 compatible = "simple-bus"; 166 #address-cells = <2>; 167 #size-cells = <2>; 168 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/ 169 <0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */ 170 <0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */ 171 <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */ 172 <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */ 173 <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */ 174 <0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */ 175 <0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */ 176 <0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */ 177 <0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */ 178 <0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */ 179 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */ 180 <0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/ 181 182 }; 183 184 }; 185}; 186 187/* Now include peripherals from each bus segment */ 188#include "k3-j721s2-main.dtsi" 189#include "k3-j721s2-mcu-wakeup.dtsi" 190